CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is an International Application of U.S. Application

Number 15/088,557, filed on April 1, 2016, which claims the benefit of priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application Ser. No. 62/255,211, filed November 13, 2015, all of which are incorporated by reference herein in their entirety.

TECHNICAL FIELD

[0002] The present disclosure relates generally to microelectronic system packaging, and more particularly, to a copper interconnect process to enable a face-to- face and wafer-level-chip-scale packaging and to a microelectronic system including hydrogen barriers and copper interconnects.

BACKGROUND

[0003] Wafer-level-chip-scale packaging (WLCSP) is a type of package for integrated circuits (ICs) or Micro-Electromechanical System (MEMS), having an area that no greater than 120% of the area of the chip or die it contains, and is generally surface mountable. Face-to-Face (F2F) packaging is a type of WLCSP in which multiple dies or chips of a microelectronic system are vertically stacked and electrically coupled within a single package reducing a size or footprint of the package. F2F packages utilize copper (CU) pillar or bumps and redistribution layers (RDL) to interconnect bond pads formed on exposed facing surfaces of the chips. CU pillars allow a finer pitch, reduce the probability of CU pillars bridging, and decrease the capacitance load for the circuits, as compared to flip-chip technology using solder bumps, thereby allowing the microelectronic system to operate at higher frequencies. MCM are particular advantageous for integrally packaging chips including circuits or components fabricated using incompatible technologies. For example, F2F packaging can be used where a first chip or substrate including logic circuits or a processor, typically fabricated using complementary metal-oxide-semiconductor (CMOS) technology, is electrically coupled to and integrally packaged with a second chip including an IC, such as a memory, or a MEMS fabricated using processes incompatible with CMOS technology.

[0004] Problems with conventional F2F packaging utilizing CU pillar and/or

RDLs include diffusion of hydrogen through conductive and non-conductive layers surrounding a component in the IC or MEMS including a material susceptible to degradation by hydrogen. For example, a ferroelectric random access memory (F-RAM) including a ferroelectric capacitor with a lead zirconate titanate (PZT) ferroelectric layer or a MEMS with a piezoelectric layer including PZT. It has been observed that PZT is exposed to hydrogen, particular at elevated temperatures, the electrical properties of a PZT layer are severely degraded. Generally, there are two ways in which hydrogen is introduced to F2F packaged components. The first is during standard processing techniques used to form the CU pillars and RDL, or other interconnects which typically require hydrogen species at elevated process temperatures. The second is from hydrogen generated within the chip itself. For example, water adsorbed within permeable layer of the chip structure can react with metals causing dissociation of the water releasing hydrogen.

[0005] Thus, there is a need for a F2F package and packaging method that minimizes hydrogen penetration into ICs or MEMS including a material susceptible to degradation by hydrogen during the packaging process. It is further desirable that structure of the F2F package minimizes penetration into ICs or MEMS of hydrogen generated within the chip itself.

SUMMARY

[0006] A microelectronic system including copper pillars and hydrogen barriers to minimize hydrogen penetration into a component incorporating a material that renders the component susceptible to degradation by hydrogen during forming the copper pillars is provided. The component is formed in a first substrate, and the microelectronic system further includes an insulating hydrogen barrier over a surface of the first substrate, the insulating hydrogen barrier having an opening exposing at least a portion of an electrical contact to the component, and a conducting hydrogen barrier over at least the exposed portion of the electrical contact. The copper pillar is formed over a top surface of the conducting hydrogen barrier and electrically coupled to the component through the conducting hydrogen barrier and the electrical contact. The material that renders the component susceptible to degradation can include lead zirconate titanate (PZT). In one embodiment, the microelectronic system can include a Micro-Electromechanical Systems (MEMS) device including PZT. In another embodiment, the microelectronic system can include a ferroelectric random access memory (F-RAM), and the component includes a ferroelectric capacitor incorporating a PZT ferroelectric layer.

[0007] In one embodiment, a method of fabricating the microelectronic system includes forming an insulating hydrogen barrier over a surface of a first substrate, and exposing at least a portion of an electrical contact to a component in the first substrate by removing a portion of the insulating hydrogen barrier. The component includes a material that renders the component susceptible to degradation by hydrogen. A conducting hydrogen barrier is then formed over the exposed portion of the electrical contact and at least a portion of the insulating hydrogen barrier. A copper pillar is formed over the conducting hydrogen barrier, while the insulating hydrogen barrier and the conducting hydrogen barrier minimizes hydrogen penetration into the material of the component.

[0008] In one embodiment, the method further includes patterning the conducting hydrogen barrier to form a redistribution layer (RDL) prior to forming the copper pillar on the RDL over the insulating hydrogen barrier.

[0009] In another embodiment, the method further includes forming a copper

(CU) RDL on the conducting hydrogen barrier and patterning the CU RDL and conducting hydrogen barrier prior to forming the copper pillar over a portion of the CU RDL over the insulating hydrogen barrier, while the insulating hydrogen barrier and the conducting hydrogen barrier minimizes hydrogen penetration into the material susceptible to degradation during forming the CU RDL.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present invention will be understood more fully from the detailed description that follows and from the accompanying drawings and the appended claims provided below, where:

[0011] FIGs. 1A and IB are a flowchart illustrating an embodiment of a method for packaging a microelectronic system in a face-to-face package including copper pillars and a copper redistribution layer according to an embodiment of the present disclosure; [0012] FIGs. 2A-2L are block diagrams illustrating cross- sectional views of a portion of the microelectronic system formed by the method of the flowchart of FIGs. 1A and IB;

[0013] FIG. 3 is a block diagram illustrating a cross- sectional view of a portion of the microelectronic system according to another embodiment of the method of the present disclosure; and

[0014] FIG.4 is a block diagram illustrating cross-sectional views of a portion of the microelectronic system including a Micro-Electromechanical System (MEMS) formed by the method of the flowchart of FIGs. 1A and IB.

DETAILED DESCRIPTION

[0015] Embodiments of face-to-face (F2F) packages including copper pillars and redistribution layers and methods of fabricating the same to minimize hydrogen penetration into a material susceptible to degradation by hydrogen are described herein with reference to figures. However, particular embodiments may be practiced without one or more of these specific details, or in combination with other known methods, materials, and apparatuses. In the following description, numerous specific details are set forth, such as specific materials, dimensions and processes parameters etc. to provide a thorough understanding of the present invention. In other instances, well-known semiconductor design and fabrication techniques have not been described in particular detail to avoid unnecessarily obscuring the present invention. Reference throughout this specification to "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0016] The terms "over," "under," "between," and "on" as used herein refer to a relative position of one layer with respect to other layers. As such, for example, one layer deposited or disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer deposited or disposed between layers may be directly in contact with the layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in contact with that second layer. Additionally, the relative position of one layer with respect to other layers is provided assuming operations deposit, modify and remove films relative to a starting substrate without consideration of the absolute orientation of the substrate.

[0017] Embodiments of a F2F packaging method to minimize hydrogen penetration into a material susceptible to degradation by hydrogen will now be described in detail with reference to FIGS. 1A and IB, FIGs. 2A-2K and FIG. 3. FIGS. 1A and IB are a flowchart illustrating an embodiment of a method for packaging a microelectronic system in a F2F package including CU pillars and a CU RDL. FIGs. 2A-2K are block diagrams illustrating cross-sectional views of a portion of the microelectronic system formed by the method of the flowchart of FIGs. 1A and IB. FIG. 3 is a block diagram illustrating a cross-sectional view of a portion of the microelectronic system prepared for packaging according to another embodiment of the method of the present disclosure.

[0018] Referring to FIG. 1A and FIG. 2A, the process begins with forming a component of a microelectronic system on or in a first substrate 202 or chip (step 102). In the embodiment shown in FIG 2A, the microelectronic system is or includes a ferroelectric random access memory (F-RAM), and the component is a ferroelectric capacitor 204 incorporating a material susceptible to degradation by hydrogen. The ferroelectric capacitor 204 includes a ferroelectric material 206 between an upper electrode 208 and a lower electrode 210 covered by or embedded in a dielectric layer 212. In addition to the ferroelectric capacitor 204 each cell in the F-RAM further includes a number of transistors (not shown) electrically coupled to the lower electrode 210 through a metallization layer 214 and to the upper electrode 208 through a vertical contact or via 216 extending through the dielectric layer 212 and an electrical contact 218 formed from a second metallization layer. Optionally, the ferroelectric capacitor 204 can further include conductive oxygen (0 ₂ ) barriers between the lower electrode 210 and metallization layer 214 and between the top electrode 208 via 216, and sidewall encapsulation layers between the ferroelectric capacitor and dielectric layer 212.

[0019] The ferroelectric capacitor 204, dielectric layer 212, metallization layer

214, via 216 and electrical contact 218 are formed using a standard deposition and photolithographic process flows. The upper electrode 208 and lower electrode 210 can include one or more layers of iridium or iridium oxide having a thickness of from about 0.05 to about 0.20 μιη, and are deposited or formed using chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD). The metallization layer 214, via 216 and electrical contact 218 can be or include aluminum, titanium, tungsten or alloys or mixtures thereof, and can be deposited by PVD, such as sputtering, evaporation, or electroless plating to a thickness of from about 1000 to about 5000 A. Dielectric layer 212 can include one or more layers of an undoped oxide, such as ferroelectric oxide (FEO) or silicon-dioxide (Si0 ₂ ), a nitride, such as silicon nitride (Si _x N _y ), a silicon-oxynitride (SixO _y N _z ) or phosphosilicate glass (PSG) deposited by CVD to a thickness of from about to about microns (μ).

[0020] The ferroelectric material 206 generally includes a material such as lead zirconate titanate (PZT) Pb [Zr _x Tii_ _x ]0 ₃ , which is susceptible to degradation by hydrogen and is deposited to a thickness of from about 0.04 to about 0.10 μιη, using CVD, ALD or PVD. Data is stored in the ferroelectric capacitor by applying an external electric field across a ferroelectric material, which causes dipoles in the ferroelectric material to align with the field direction. After the electric field is removed data is stored in the cell using a remnant polarization of the ferroelectric material. As hydrogen penetrates or diffuses into the ferroelectric material, the oxide of the PZT undergoes reduction. Electrically this is observed as a decrease in the "remnant polarization", or charge that remains once the applied voltage is removed.

[0021] Next, as indicated in step 104 of FIG. 1A, the surfaces of the electrical contact 218 and dielectric layer 212 are planarized, for example, using a chemical mechanical polishing (CMP) process.

[0022] Referring to FIGs. 1A and 2B an insulating hydrogen barrier 220 is then formed over and/or directly on the planarized surfaces of the electrical contact 218 and dielectric layer 212 (step 106). The insulating hydrogen barrier 220 can be or include one or more layers of aluminum oxide (A1 ₂ 0 ₃ ) having a thickness of from about to about A or a silicon oxynitride (SiON) having a thickness of from about A to about A, and deposited by CVD or ALD. [0023] In some embodiments, such as that shown in FIG. 2B, a passivation layer

222 is formed on the insulating hydrogen barrier 220 (step 108). The passivation layer 222 can be or include one or more layers of dielectric material, such as silicate glass (USG), silicon nitride, silicon oxide, polymer, polyimides or combinations thereof. In one embodiment, the passivation layer 222 includes having a thickness of from about to about A deposited by CVD or ALD. [Ali, 1) can the passivation layer be omitted in some embodiments or is it absolutely necessary for the device to work? 2) What is the material and thickness of the passivation layer and how is it deposited? Also, does either or both of the passivation layer or insulating hydrogen barrier need to be planarized after deposition?]

[0024] Next, referring to FIGs. 1A and 2C a first opening 224 is formed in the insulating hydrogen barrier 220, and passivation layer 222 if present, exposing at least a portion of the electrical contact 218 (step 110). First opening 224 can be etched using standard photolithographic and dry or wet etching techniques. For example, a patterned photoresist layer (not shown) can be formed on the passivation layer 222, and where the passivation layer includes and the insulating hydrogen barrier 220 includes

AI ₂ O ₃ , both layers can be etched in a wet etch process using a buffered oxide etch (BOE), a hydrofluoric (HF) wet etch, a pad etch, or any other similar hydrofluoric -based wet etching chemistry. Alternatively, the etch can be accomplished in a dry or plasma process using a mixture of a based gas, such as , and or . [Ali, please provide some details of the etch process. Is wet or dry? Can both layers be etched in a single process?]

[0025] Referring to FIGs. 1A and 2D a conducting hydrogen barrier 226 is formed over at least the exposed portion of the electrical contact 218 (step 112). Generally, the conducting hydrogen barrier is formed over at least a portion of the passivation layer 222 and insulating hydrogen barrier 220, and in some embodiments, such as that shown, the conducting hydrogen barrier 226 is formed over and directly on substantially an entire surface of the passivation layer 222. The conducting hydrogen barrier 226 can be or include one or more layers of titanium-aluminum-nitride (TiAlN) or aluminum titanium nitride (AlTiN) having a thickness of from about A to about

A, and deposited by CVD or ALD. Alternatively, the conducting hydrogen barrier 226 can include one or more layers of titanium nitride (TiN), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON) or aluminum (Al) having a thickness of from about A to about A, and deposited by CVD or ALD.

[0026] In some embodiments, such as that shown in FIG. 2E, a separate, dedicated redistribution layer (RDL) 228 is formed over the conducting hydrogen barrier 226 (step 114). The RDL 228 serves to redistribute or relocate subsequently formed pads or pillars that are electrically coupled to the contact 218 away from a location directly over the contact. The RDL 228 can be or include one or more layers of conductive material, such as a metal or metal alloy. In one embodiment, the RDL 228 includes copper (Cu) having a thickness of from about to about A deposited by plasma assisted CVD (PACVD). In one embodiment a capacitively coupled radio frequency (RF) hydrogen plasma including a copper precursor, such as hexafluoroacetylacetonate (Cu(HFA) ₂ ), is used to form on a surface of the substrate via a reaction between the precursor adsorbed in the conducting hydrogen barrier 226 and atomic hydrogen. [Ali, is this correct?] [0027] As noted above, the ferroelectric material 206 generally includes a material such PZT, which is susceptible to degradation by hydrogen. In conventional copper deposition processes hydrogen can diffuse into the PZT through the RDL and/or a conventional passivation, the contact 218, via 216 and upper electrode 208. In the method of the present disclosure the insulating hydrogen barrier 220 and the conducting hydrogen barrier 226 isolate the contact 218 from the hydrogen used or generated in the PACVD process, minimizing or substantially eliminating hydrogen penetration into the ferroelectric material 206 of the ferroelectric capacitor 204 during the forming of a Cu RDL 228.

[0028] Generally, the RDL 228 is formed directly on the conducting hydrogen barrier 226 overlying the contact 218, and over at least a portion of conducting hydrogen barrier overlying the passivation layer 222 and insulating hydrogen barrier 220. In some embodiments, such as that shown, the RDL 228 is formed directly on substantially an entire surface of the conducting hydrogen barrier 226 overlying the passivation layer 222 and insulating hydrogen barrier 220.

[0029] Next, in some embodiments, such as that shown in FIG. 2F, under bump metallization (UBM) 230 is formed over the conducting hydrogen barrier 226 and RDL 228 (step 114). The UBM 230 can be or include one or more layers of a metal or metal alloy selected to serve as an adhesion or glue layer, a diffusion barrier and/or a seed layer. Generally, the UBM 230 is formed of titanium, tantalum, titanium nitride, tantalum nitride by PVD. In one embodiment, the UBM 230 can includes having a thickness of from about to about A deposited directly on the RDL 228 by sputtering, evaporation, or electroless plating. [0030] Next, referring to FIGs. 1A and 2G the UBM 230, RDL 228 and conducting hydrogen barrier 226 are patterned (step 116). The UBM 230, RDL 228 and conducting hydrogen barrier 226 can be patterned using standard photolithographic and dry or wet etching techniques. For example, a patterned photoresist layer (not shown) can be formed on the UBM 230, and where UBM includes , RDL 228 includes copper, and the conducting hydrogen barrier 226 includes TiAIN, all of the layers can be etched in a wet etch process using a solution including an acid, such as nitric, acetic or sulfuric acid, and an oxidizing agent, such as hydrogen peroxide, permanganate, ferric ion, bromine or chromium. [Ali, please provide some details of the etch process. Is wet or dry? Can all three layers be etched in a single process?]

[0031] Referring to FIGs. IB and 2H a photoresist (PR) coating 232 is deposited over the patterned UBM 230, RDL 228 and conducting hydrogen barrier 226 and patterned using standard photolithographic techniques to form second openings 234 therein (step 118).

[0032] Next, referring to FIGs. IB and 21 copper (Cu) bumps or pillars 236 are formed in the second openings 234 on the UBM 230 exposed therein, and solder caps 238 formed on the pillars (step 120). The Cu pillars 236 can be deposited to a thickness or height above the UBM 230 of from about to about μ by PACVD using a hydrogen plasma as described above with respect to the Cu RDL 228. The insulating hydrogen barrier 220 and the conducting hydrogen barrier 226 minimizes or substantially eliminates hydrogen penetration into the ferroelectric material 206 of the ferroelectric capacitor 204 during the forming of the copper pillars 236. The solder caps 238 can include tin, silver, lead, Cu, zinc, indium, gold, bismuth, antimony or alloys thereof, and are be deposited directly on the Cu pillars 236 to a thickness of from about to about A by a electroless plating process.

[0033] Referring to FIGs. IB and 2J the patterned PR coating 232 is removed or stripped using standard photolithographic techniques, and exposed portions of the UBM 230, not underlying the copper pillars 236 removed (step 122). As with the step of patterning the UBM 230, step 116, described above, the exposed portions of the UBM can be removed in a wet etch process using a solution including an acid, such as nitric, acetic or sulfuric acid, and an oxidizing agent, such as hydrogen peroxide, permanganate, ferric ion, bromine or chromium. [Ali, is this correct?]

[0034] Next, referring to FIGs. IB and 2K the first substrate 202 is singulated or diced to form individual die or chips, and solder caps 238 are softened or melted in a reflow soldering process in preparation for a face-to-face attachment to a companion-die or second substrate (step 124). Generally, as shown in FIG. 2K each of the individual die or chips include one or more components of the microelectronic system, such as the ferroelectric capacitor 204, and one or more Cu pillars 236 through which the die can be physically attached and electrically coupled to the companion-die or second substrate (not shown in this figure). [Ali, is this correct?]

[0035] Finally, referring to FIGs. IB and 2L the singulated or diced first substrate

202 is physically attached and electrically coupled to the companion-die or second substrate 240 through the molten solder caps 238 to form a WLCSP or F2F package 242 as shown in FIG. 2L (step 126). Referring to FIG. 2L the second substrate 240 includes first pads 244 on a top or facing surface to which the Cu pillars 236 are bonded and through which a number of other components, such as ICs 246, formed on the second substrate can be electrically coupled to components of the microelectronic system on the first substrate 202. Additionally, the second substrate 240 can further include second pads 248 on a lower or opposing surface electrically coupled to the first pads 244 and/or ICs 246 formed in or on the second substrate by means of a number of through silicon vias (TSVs) 250. The first and second substrates 202 and 240 can be encapsulated in a dielectric or plastic molding compound 252 and physically attached and/or electrically coupled to an external circuit via a number of a ball grid array 254 on the second substrate, or a backplane to which the second substrate is attached, to form a flat, no-lead package, such as a Quad Flat-pack No-lead (QFN) package.

[0036] Alternatively, in another embodiment (not shown) the F2F package 242 is an open cavity type package in which the first and second substrates 202 and 240 are positioned in an open cavity and enclosed by plastic, ceramic, glass or metal sidewalls attached to the second substrate, or a backplane and top wall or lid joining the sidewalls. Additionally, the second substrate 240 can be attached or wire bonded to a lead frame through which the first and second substrates 202 and 240 can be electrically coupled to an external circuit.

[0037] In yet another alternative embodiment, shown in FIG. 3, the conducting hydrogen barrier 226a includes a material and a thickness selected to serve as a redistribution layer (RDL) to redistribute or relocate subsequently formed pads or pillars that are electrically coupled to the contact 218 away from a location directly over the contact. The RDL/conducting hydrogen barrier 226a can include a single layer of titanium-aluminum-nitride (TiAlN), aluminum titanium nitride (AlTiN), titanium nitride (TiN), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON) or aluminum (Al) having a thickness of from about A to about A, and can be deposited by

CVD or ALD. In one version of this embodiment the RDL/conducting hydrogen barrier

226a can include a single layer of TiAIN or AlTiN having a thickness of from about μ to about μ deposited by CVD. It will be understood that this embodiment is advantageous in that it eliminates the need for a separate deposition and etch steps for a dedicated RDL 228, and can further minimize hydrogen penetration into the ferroelectric material 206 of the ferroelectric capacitor 204 during processing by eliminating a Cu RDL 228.

[0038] Finally, in another alternative embodiment, the microelectronic system is or can include a Micro-Electromechanical System (MEMS) having a component including a piezoelectric material susceptible to hydrogen degradation. Exemplary MEMS can include microphones, motion or position sensors, such as gyroscopes, accelerometers, and magnetometers, light modulators, resonators, transducers, and actuators or pumps, such as those used in inkjet print heads. An embodiment of a microelectronic system including a motion/positon sensing MEMS 256 having a component and including a piezoelectric material 258, such as PZT, is shown in FIG. 4.

[0039] Referring to FIG. 4, in addition to the piezoelectric material 258 the

MEMS includes an upper electrode 260 and a lower electrode 262 coupled to the piezoelectric material, and a test mass 266 formed on the upper electrode over the piezoelectric material, all enclosed in a cavity 264 formed in the dielectric layer 212. The upper electrode 260 also serves as a spring for the test mass 266. In operation, acceleration of the MEMS 256 exerts a force on the piezoelectric material 258, which can be detected and measured by a change in the electrostatic force or voltage generated by the piezoelectric material across the upper electrode 260 and lower electrode 262. [Ali, we should include an exemplary figure of a MEMS for which the packaging method, i.e., insulating and conducting H2 barrier can be used in order to not limit our claims to F-RAM. I have prepared a drawing of an accelerometer, but I am not certain that the figure or description is accurate or adequate. Could you correct the figure and description OR provide me with a rough diagram of such a MEMS for which the method of the invention can be used. Note, in the event you choose to do later please make certain the MEMS can be covered by a thick ILD and the H2 barriers could be formed over it.]

[0040] Thus, embodiments of ferroelectric random access memories including a copper interconnect process to enable F2F and WLCSP packaging and to a microelectronic system including hydrogen barriers and copper interconnects have been described. Although the present disclosure has been described with reference to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the disclosure. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0041] The Abstract of the Disclosure is provided to comply with 37 C.F.R.

§ 1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of one or more embodiments of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.