Title:
IC CHIP
Document Type and Number:
WIPO Patent Application WO/2019/124211
Kind Code:
A1
Abstract:
This reception-side IC chip (1a) is provided with: a pad (15) connected to a transmission line (2) in which the characteristic impedance (Z0) outside the chip is 50 Ω; a signal line (16) having one end connected to the pad (15); a reception-side input unit circuit (10) which receives a signal (S) transmitted from the reception-side IC chip through the transmission line (2); a termination resistor (11) which has a resistance of 50 Ω and is for impedance matching, the termination resistor being connected between a predetermined voltage and the other end of the signal line (16), and terminating the transmission line (2); and a capacitor (12) inserted between a connection point (A) of the signal line (16) and the termination resistor (11), and an input terminal (In) of the reception-side input unit circuit (10). A DC block circuit comprises the capacitor (12).
Inventors:
NAGATANI MUNEHIKO (JP)
NOSAKA HIDEYUKI (JP)
NAKANO SHINSUKE (JP)
NOSAKA HIDEYUKI (JP)
NAKANO SHINSUKE (JP)
Application Number:
PCT/JP2018/045860
Publication Date:
June 27, 2019
Filing Date:
December 13, 2018
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
H04B3/02; H03H7/06; H04B1/00
Foreign References:
| JP2016162804A | 2016-09-05 | |||
| JP2011009853A | 2011-01-13 | |||
| JPH09200077A | 1997-07-31 |
Other References:
H. WAKITA ET AL.: "36-GHz-Bandwidth Quad-channel Driver Module using Compact QFN Package for Optical Coherent Systems", ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS, 2015
See also references of EP 3731422A4
See also references of EP 3731422A4
Attorney, Agent or Firm:
YAMAKAWA, Shigeki et al. (JP)
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