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Title:
IDENTIFICATION SYSTEM
Document Type and Number:
WIPO Patent Application WO/1996/021209
Kind Code:
A1
Abstract:
An identification system (30) uses an interrogator (32) to provide a reference signal and one or more count signals and uses a plurality of tags (34-36), each being assigned an identification number, N. The tags (34-36) provide a response signal (54, 55, 56) to the interrogator (32) after the interrogator (32) has transmitted a reference signal followed by N count signals. The interrogator (32) receives the response signal (54, 55, 56) from each of the tags (32-34). The tags (32-34) can detect the reference signal, detect the count signals, and transmit the response signal (54, 55, 56).

Inventors:
Smith
Stephen
Dale
Application Number:
PCT/US1995/017088
Publication Date:
July 11, 1996
Filing Date:
December 29, 1995
Export Citation:
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Assignee:
Smith
Stephen
Dale
International Classes:
G08B26/00; (IPC1-7): G08B26/00; G08B13/14; H04Q9/00
Download PDF:
Claims:
WHAT IS CLAIMED IS:
1. An identification system, comprising: an interrogator having means for providing a reference signal and for providing one or more count signals; and a plurality of tags, each of said tags having an identification number, N, and having means for detecting transmission by the interrogator of said reference signal and N of said count signals.
2. An identification system, according to claim 1, wherein each of said tags further includes means for providing a response signal to said interrogator after said interrogator has transmitted a reference signal followed by N count signals, and said interrogator further includes means for receiving said response signal from each of said tags.
3. An identification system, according to claim 1, wherein each of said tags has an identification number different from other ones of said tags.
4. An identification system, according to claim 2, wherein said means for providing a response signal includes means for detecting said reference signal, means for detecting said count signals, and means for transmitting said response signal.
5. An identification system, according to claim 2 , wherein said means for providing a response comprises: an antenna; a detector coupled to said antenna; a clock that generates a digital signal in response to each count signal received by said antenna; an integrator that generates a load signal in response to said antenna receiving said reference signal; a counter, coupled to said clock and said integrator, said counter incrementing by one in response to each digital signal provided by said clock and loading a predetermined value into said counter in response to said load signal; and an oscillator, coupled to said counter, for provided said response signal in response to said counter generating an overflow signal.
6. An identification system, according to claim 1, wherein said means for providing a reference signal and one or more count signals comprises: an oscillator; a power amplifier coupled to said oscillator; an antenna that transmits signals provided by said power amplifier; and a microprocessor that provides signals to said power amplifier to initiate transmission of said reference signal and said one or more count signals.
7. An identification system, according to claim 2, wherein said means for receiving said response from each of said tags comprises: an antenna; a mixer that downconverts signals received by said antenna; and a detector that processes the signal from said mixer and outputs a signal that indicates the presence of said response signal.
8. An identification system, according to claim 5, wherein said means for receiving said response from each of said tags comprises: a mixer that downconverts signals received by said antenna; and a detector that processes the signal from said mixer and outputs a signal that indicates the presence of said response signal.
9. An identification system, according to claim 8, further comprising: a hybrid, for receiving and sending signals via said antenna, wherein said hybrid isolates transmitted signals from received signals.
10. An identification system, according to claim 9, further comprising: a first filter coupled to said hybrid for filtering signals received by said interrogator; a switch, coupled to said first filter and said microprocessor, wherein said switch is controlled by the microprocessor to isolate transmitted signals from received signals; a low noise amplifier, coupled to said switch and said mixer, for amplifying said received signals; a second filter, coupled to said mixer, for lowpass filtering a signal output by said mixer; and an amplifier, coupled to said second filter and said detector, for amplifying an output signal provided by said second filter.
11. An identification system, according to claim 10, wherein said means for providing a response includes means for detecting said reference signal, means for detecting said count signals, and means for transmitting said response signal.
12. An identification system, according to claim 10, wherein said means for providing a response comprises: an antenna; a detector coupled to said antenna; a clock that generates a digital signal in response to each count signal received by said antenna; an integrator that generates a load signal in response to said antenna receiving said reference signal; a counter, coupled to said clock and said integrator, said counter incrementing by one in response to each digital signal provided by said clock and loading a predetermined value into said counter in response to said load signal; and an oscillator, coupled to said counter, for provided said response signal in response to said counter generating an overflow signal.
13. An identification system, according to claim 12, wherein said interrogator and said tags transmit and receive radio frequency signals having substantial frequency components between 912 MHz and 918 MHz.
14. An identification system, according to claim 13, wherein said interrogator and said tags transmit and receive radio frequency signals having substantial frequency components at 915 MHz.
15. An identification system, according to claim 12, wherein said reference signal is a two 100 usec pulses separated by 10 usec and wherein said count signals are 1 usec pulses.
16. An identification system, according to claim 15, wherein said response signals are 4 usec pulses.
17. A method of operating an identification system that includes an interrogator and one or more tags, the method comprising the steps of: the interrogator providing a reference signal and one or more count signals; a particular tag, having an identifier of N, detecting transmission by the interrogator of the reference signal followed by N of the count signals.
18. A method of operating an identification system, according to claim 17, further comprising the steps of: the particular tag providing a response signal to the interrogator after detecting that the interrogator has transmitted a reference signal followed by N count signals; and the interrogator receiving the response signal from the particular tag.
19. A method of operating an identification system, according to claim 17, further comprising the step of: assigning identification numbers to each of the tags such that no tags have the same identification number.
20. A method of operating an identification system, according to claim 17, wherein said step of detecting the reference signal followed by N count signals includes the steps of: setting a counter to a predetermined value in response to the reference signal; and incrementing a counter by one in response to each of the count signals.
21. A method of operating an identification system, according to claim 18, wherein the interrogator and the tags transmit and receive radio frequency signals having substantial frequency components between 912 MHz and 918 MHz.
22. A method of operating an identification system, according to claim 21, wherein the interrogator and the tags transmit and receive radio frequency signals having substantial frequency components at 915 MHz.
23. A method of operating an identification system, according to claim 18, further comprising the steps of: providing the reference signal as two 100 usec pulses separated by 10 usec; and providing the count signals as 1 usec pulses.
24. A method of operating an identification system, according to claim 23, further comprising the step of: providing the response signals as 4 usec pulses.
25. A method of operating an identification system, according to claim 20, wherein the interrogator and the tags transmit and receive radio frequency signals having substantial frequency components between 912 MHz and 918 MHz.
26. A method of operating an identification system, according to claim 25, wherein the interrogator and the tags transmit and receive radio frequency signals having substantial frequency components at 915 MHz.
27. A method of operating an identification system, according to claim 20, further comprising the steps of: providing the reference signal as two 100 usec pulses separated by 10 usec; and providing the count signals as 1 usec pulses.
28. A method of operating an identification system, according to claim 27, further comprising the step of: providing the response signals as 4 usec pulses.
Description:
96/21209

Identification System

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to electronic identification systems. More specifically, the invention relates to a system for ascertaining the presence or absence of one or more electronic tags within a particular area or range.

2. Related Art It is known to provide an identification system that includes an interrogator source which transmits radio frequency signals to multiple receivers, called "tags", in order to determine the presence or absence of each of the tags. A tag or a subset of tags can associated with a specific and unique identifier so that the interrogator can address specific tags with the radio frequency signal. A tag that is within range of the interrogator responds with its own radio frequency signal, thus indicating to the interrogator that the tag is within range. Often, the data transmission scheme allows multiple tags to be individually

identified and detected within the same radio frequency field.

Often, radio frequency identification systems use sophisticated data transmission schemes in order to ensure accuracy. Most systems strive for 99.99% data transmission accuracy with a single interrogation. To achieve this accuracy, the systems transmit digital data, with data integrity checks incorporated therein, between the interrogator and the tags. This requires that multiple data bits for each tag be sent between the interrogator and each of the tags, thus increasing the time it takes to interrogate the tags. Furthermore, a complex digital transmission scheme increases the complexity, and hence the cost, of each of the tags. Furthermore, the complex scheme is relatively slow, resulting in interrogation rates of around 15,000 tags per second.

It is desirable to decrease the cost of the tags while simultaneously decreasing the time needed to interrogate the tags in order to increase the number of tags which can be interrogated in a given amount of time.

SUMMARY OF THE INVENTION

According to the present invention, an identification system uses an interrogator to provide a reference signal and one or more count signals, and uses a plurality of tags, each being assigned an identification number, N. Each of the tags can respond or take some other action after the interrogator has transmitted a reference signal followed by N count signals. Each tag can be assigned a unique identification number different from identification numbers assigned to other ones of the tags. The response can include providing a response signal to the interrogator. The interrogator can receive and process the response signal from each of the tags.

The tags can detect the reference signal, detect the count signals, and transmit the response signal. The interrogator can provide the signals transmitted therefrom by using an oscillator, a power amplifier coupled to the oscillator, an antenna that transmits signals provided by the power amplifier, and a microprocessor that provides signals to the power amplifier to initiate transmission of the reference signal and the count signals. The interrogator can receive signals by using a mixer that down-converts signals received by the antenna and a detector

that processes the signal from the mixer and outputs a signal that indicates the presence of the response signal.

The interrogator can also include a hybrid, for receiving and sending signals via the antenna, where the hybrid isolates transmitted signals from received signals, a first filter coupled to the hybrid for filtering signals received by the interrogator, and a switch, coupled to the first filter and the microprocessor, where the switch is controlled by the microprocessor to isolate transmitted signals from received signals. The interrogator can also include a low noise amplifier, coupled to the switch and to the mixer, for amplifying the received signals, a second filter, coupled to the mixer, for low-pass filtering a signal output by the mixer, and an amplifier, coupled to the second filter and the detector, for amplifying an output signal provided by the second filter.

Each of the tags can include an antenna, a detector coupled to the antenna, a clock that generates a digital signal in response to each count signal received by the antenna, an integrator that generates a load signal in response to the antenna receiving the reference signal, and a counter, coupled to the clock and the integrator. The counter can increment by one in response to each digital

signal provided by the clock and can load a predetermined value into the counter in response to the load signal. An oscillator can be coupled to the counter and used to provide the response signal when the counter generates an overflow signal. The interrogator and the tags can transmit and receive radio frequency signals having substantial frequency components at 915 MHz. The reference signal can be two 100 usec pulses separated by 10 usec and the count signals can be 1 usec pulses. The response signals can be 4 usec pulses.

The identification system according to the present invention is less complex, and hence less costly to build and maintain, than conventional identification systems. The simplicity of the identification system according to the present invention allows for rapid interrogation of the tags, thus facilitating many interrogations in a relatively short period of time. It is therefore practical to rapidly interrogate all of the tags of the system more than once in order to increase the reliability of the system. Unlike prior art identification systems which are primarily directed to the transmission of information between the tags and the interrogator, the present invention relies upon signals, transmitted between the elements, that essentially contain no information other than their presence or absence.

BRIEF DESCRIPTION OF THE DRAWINGS The invention is better understood by reading the following Detailed Description of the Preferred Embodiments with reference to the accompanying drawing figures, in which like reference numerals refer to like elements throughout, and in which:

FIG. 1 illustrates an identification system according to the present invention.

FIG. 2 illustrates a timing diagram for an identification system according to the present invention.

FIG. 3 is a schematic block diagram of a tag for an identification system.

FIG. 4 is a schematic block diagram of an interrogator for an identification system.

FIG. 5 is a schematic diagram showing in detail a preferred embodiment of a tag for an identification system.

FIG. 6 is a schematic diagram showing in detail a receiving portion of a preferred embodiment of an interrogator for an identification system.

FIG. 7 is a schematic diagram showing in detail a transmitting portion of a preferred embodiment of an interrogator for an identification system.

FIG. 8 is a schematic diagram showing a preferred embodiment of a microprocessor for an interrogator.

FIG. 9 is a flowchart showing operation of software of the microprocessor shown in FIG. 4 and FIG. 8.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In describing preferred embodiments of the present invention illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the invention is not intended to be limited to the specific terminology so selected, and it is to be understood that each specific element includes all technical equivalents which operate in a similar manner to accomplish a similar purpose.

Referring to FIG. 1, an identification system 30 includes a interrogator 32 and a plurality of tags 34-36. The interrogator 32 detects the presence or absence of each of the tags 34-36 within the transmission/reception range of the interrogator 32. Although only three tags, TAGA 34, TAGB 35, and TAGN 36, are shown in FIG. 1, it will be

understood from the description which follows that the invention can be practiced using any number of tags and that for a specific implementation of the invention, the number of tags is limited only by design constraints imposed on the interrogator 32 and the tags 34-36, described below. Also note that, depending upon the specific application, the invention can be practiced with all of the tags 34-36 being physically separated from each other, or with one or more subsets of the tags 34-36 being physically grouped together.

The interrogator 32 transmits signals which are received by any of the tags 34-36 that are within the transmission range of the interrogator 32. As described in more detail below, the signals are preferably radio frequency signals, although the invention can be practiced using any type of signals that can be sent by the interrogator 32 and received by one of the tags 34-36, including, but not limited to, microwave signals and light signals. It is also possible to practice the invention by hardwiring the interrogator 32 to the tags 34-36, although this configuration could limit the possible uses for the system 30.

For the embodiment illustrated herein, each of the tags 34-36 has an identification number different from all of the

other ones of the tags 34-36. For example, the tag 34 could be assigned the number one, the tag 35 could be assigned the number two, and the tag 36 could be assigned the number three. The interrogator 32 detects the presence or absence of particular ones of the tags 34-36 using the identification numbers of each of the tags 34-36. Note that, in some instances, it may be desirable to assign the same number to a subset of the tags. In that case, the interrogator 32 would detect the presence or absence of at least one of the tags having the same identifier.

The interrogator 32 begins by first transmitting a RESET signal that is received by any of the tags 34-36 that are within transmission range of the interrogator 32. The RESET signal acts as a reference signal and causes each of the receiving tags 34-36 to enter a known state, as described in detail below. Following the RESET signal, the interrogator 32 transmits a plurality of TAG signals that are received by any of the tags 34-36 that are within range of the interrogator 32. The TAG signals act as count signals for the tags 34-36. When a particular one of the tags 34-36, having a identification number of N, has received N TAG signals from the interrogator 32, then the tag transmits a RESPONSE signal to the interrogator 32, thus indicating that the tag is within range of the interrogator

32. Note that, depending upon the specific application, for some embodiments of the invention it is possible to have the tags 34-36 take some alternative action, other than sending a RESPONSE signal to the interrogator 32, in response to receiving the reference signal followed by N count signals. For example, it is possible to have the tags 34-36 transmit an audible signal after receiving the reference signal and N count signals.

Referring to FIG. 2, a graph 40 illustrates operation of the interrogator 32 and the tags 34-36. The horizontal axis of the graph 40 represents the passage of time so that time increases from left to right on the graph 40. A first trace 42 shows the transmission by the interrogator 32 while second, third, and fourth traces 44-46 show transmissions provided by TAG 34, TAGB 35, and TAGN 36, respectively. The discussion of FIG. 2 which follows assumes, for illustration purposes, that all of the tags 34-36 are within range of the interrogator 32 and that the tag 34 is assigned a unique identifier of one, the tag 35 is assigned an identifier of two, and the tag 36 is assigned an identifier of three.

Initially, the interrogator 32 transmits the RESET signal 52a which is received by all of the tags 34-36 and which places all of the tags 34-36 in a known, initial,

state. In the embodiment illustrated herein, the RESET signal consists of two one hundred usec pulses having ten usec's therebetween. Following the RESET signal 52a, the interrogator 32 transmits a first TAG signal 52b which is received by all of the tags 34-36.

Assigning a unique identifier of one to the tag 34 causes the tag 34 to respond to the first TAG signal 52b transmitted by the interrogator 32. Upon receipt of the first TAG signal 52b, the tag 34 transmits a RESPONSE signal 54 which is shown in the trace 44. For the embodiment illustrated herein, the RESPONSE signal is four usec long. The tags 45,46, which also receive the first TAG signal 52b, do not send any signals since the tags 45,46 do not have an identifier of one.

The interrogator 32 detects the transmission of the RESPONSE signal 54 sent by the tag 34 and thus confirms that the tag 34 is within range of the interrogator 32. If the tag 34 had not been in range of the interrogator 32, then the RESPONSE signal 54 would not have been sent by the tag 34 and the interrogator 32 would deem the first tag 34 not to be in range of the interrogator 32.

Following the first TAG signal 52b, the interrogator 32 transmits a second TAG signal 52c. The tag 35, having been assigned a unique identifier of two, responds to the second TAG signal 52c by transmitting a RESPONSE signal 55. That is, since the tag 35 has been assigned a unique identifier of two, the tag 35 transmits the RESPONSE signal 55 after receiving the two TAG signals 52b,52c. The tags 34,36, which are assigned identifiers other than two, do not transmit in response to receiving the two TAG signals 52b, 52c. Accordingly, the interrogator 32 detects the

RESPONSE signal 55 transmitted by the tag 35 and determines that the tag 35 is within range of the interrogator 32.

Following the second TAG signal 52c, the interrogator 32 transmits a third TAG signal 52d. The tag 36, having been assigned a unique identifier of three, responds to the third TAG signal 52d by transmitting a RESPONSE signal 56. The tag 36 transmits the RESPONSE signal 56 after receiving the three TAG signals 52b-d. The tags 35,36, which are assigned identifiers other than three, do not transmit in response to receiving the three TAG signals 52b-d.

Accordingly, the interrogator 32 detects the RESPONSE signal 56 transmitted by the tag 36 and determines that the tag 36 is within range of the interrogator 32. For the three tags 34-36, the TAG signals 52b-d act as count signals to the

tags 34-36, and allow the tags 34-36 to count up to the unique identifier for each of the tags 34-36. Also, note that the TAG signals 52b-d are simply bursts of energy that do not contain any specific information and that the TAGS 34-36 operate by detecting that the TAG signals 52b-d have been transmitted rather than by decoding or interpreting the contents of the TAG signals 52b-d.

Referring to FIG. 3, a schematic block diagram 60 functionally illustrates operation of one of the tags 34-36. A detailed implementation of a preferred embodiment of the diagram 60 is set forth elsewhere herein.

An antenna 62 receives RESET and TAG signals from the interrogator 32 and transmits the RESPONSE signal. The antenna 62 can be a quarter wavelength patch antenna shorted on one side, a half wavelength patch antenna, a quarter wavelength dipole antenna, or any one of a variety of other conventional antennas suitable for receiving and sending signals. The type and shape of the antenna 62 can be modified in a conventional manner to provide a particular range and/or directionality for the tag, depending upon the specific application.

The antenna 62 is coupled to a detector 64 that processes the received signal. The detector 64 senses the presence of a signal at a particular predetermined frequency and outputs a D.C. voltage signal that varies according to the amount of time that the detected radio frequency signal is present. In a preferred embodiment, the output of the detector 64 ranges from .001 volts to 3 volts.

The output of the detector 64 is coupled to an amplifier 66. The amplifier 66 boosts the output of the detector 64 to a constant three volts whenever the output of the detector 64 is less than three volts but greater than zero volts. The input/output characteristics of the amplifier 66 can be described as follows:

output = 0.0 when input < 0.0 output = 3.0 when input > 0.0

The output of the amplifier 66 is coupled to a clock circuit 68, which provides pulse shaping for the output of the amplifier 66. The output of the clock circuit 68 is a digital signal logic "1" whenever the input signal from the amplifier 66 is approximately 3.0 volts and a logic "0" whenever the output of the amplifier 66 is approximately zero volts. Each digital pulse from the clock circuit 68

corresponds to a single TAG signal being received from the interrogator 32.

The output of the amplifier 66 is also coupled to an integrator 70, which detects the presence of the RESET signal transmitted by the interrogator 32. In response to detecting the RESET signal, the integrator 70 provides a LOAD signal, described in detail below.

The outputs of the clock 68 and the integrator 70 are provided to a counter 72, which is implemented as a conventional digital binary counter. A predetermined constant LOAD VALUE signal is also provided to the counter 72. When the counter 72 receives a LOAD signal from the integrator 70, the value indicated by the LOAD VALUE signal is loaded into the counter 72. For example, if the LOAD VALUE signal is binary 11011001, then asserting the LOAD signal would cause the counter 72 to have the value 11011001.

Receipt of a pulse from the clock circuit 68 causes the counter 72 to increment by one. Therefore, for each TAG signal sent by the interrogator 32, the counter 72 is incremented by one. Eventually, after enough TAG signals have been sent, the counter 72 overflows and generates an

OVERFLOW signal, which is provided to an oscillator 74. Upon receipt of the OVERFLOW signal from the counter 72, the oscillator 74 provides the radio frequency RESPONSE signal to the antenna 62, which in turn transmits the RESPONSE signal to the interrogator 32.

The LOAD VALUE signal is related to the unique tag identification number. For a unique identification number N, LOAD VALUE is set to a binary number that will cause the counter 72 to overflow after being incremented N times. Note that the clock circuit 68 outputs one pulse per received TAG signal and that the counter 72 increments by one for each pulse from the clock circuit 68. If the counter 72 is an eight bit binary counter, then setting LOAD VALUE to 11111111 would cause the counter 72 to overflow after receipt of one TAG signal, setting LOAD VALUE to 11111110 would cause the counter 72 to overflow after receipt of two TAG signals, setting LOAD VALUE to 11111101 would cause the counter 72 to overflow after receipt of three TAG signals, etc.

Referring to FIG. 4, a schematic block diagram 80 functionally illustrates operation of the interrogator 32. A detailed implementation of a preferred embodiment of the diagram 80 is set forth elsewhere herein.

An antenna 81 is used to receive and send signals to and from the interrogator 32. In a preferred embodiment, the antenna 81 is a cross dipole mounted in a tuned cavity. Mounting the antenna 81 in a tuned cavity increases the radio frequency gain and increases the directionality of the antenna 81. It will be appreciated by one of ordinary skill in the art that the type and configuration of the antenna 81 can be modified in a variety of manners in order to adjust the range, directionality, sensitivity and other characteristics of the antenna 81.

The antenna 81 has two connections that are coupled to a hybrid 82 which handles both input and output of the signals to the interrogator 32. The hybrid 82 divides the output signal into two signals of equal magnitude and ninety degrees out of phase with respect to each other. Circular polarization of the output signal is achieved when the hybrid 82 provides one of the signals to one of the connections to the antenna 81 and provides the other of the signals to an other of the connections to the antenna 81. The hybrid 82 also isolates the input signal of the interrogator 32 from the output signal of the interrogator 32, thus protecting the input receiver from saturation.

An input filter 84 is coupled to the output of the hybrid 82. The input filter 84 is a band-pass filter that reduces the input bandwidth of the interrogator 32 by filtering out frequency components of the received signal that are outside the frequency range transmitted by the tags 34-36. In a preferred embodiment, the input filter 84 is a two section helical resonating filter that band-passes signals between 902 MHz and 928 MHz.

The output of the filter 84 is coupled to a switch 86. The switch 86 provides additional isolation of the input signal by electrically disconnecting the output of the filter 84 from the remainder of the receiver portion of the interrogator 32 whenever the interrogator 32 transmits a signal. That is, switch 86 prevents the interrogator 32 from receiving a signal whenever the interrogator 32 is also in the process of transmitting a signal.

The output of the switch 86 is provided to a low noise amplifier 88, which increases the level of the received signal without adding appreciable noise to the signal.

The output of the low noise amplifier 88 is provided to a mixer 90. The mixer 90 also receives an input signal from an oscillator 92. In a preferred embodiment, the oscillator

92 provides a substantially sinusoidal signal at a frequency of 915 MHz. The mixer 90 uses the output of the oscillator 90 to down-convert the received input signal in order to provide an intermediate frequency signal that varies according to the input signal. In a preferred embodiment, the mixer 90 can also amplify the intermediate frequency signal .

The output of the mixer 90 is provided to a low-pass filter 94. In a preferred embodiment, the low-pass filter 94 has a three dB bandwidth at three MHz. The low-pass filter 94 provides additional filtering of the input signal, thus increasing the sensitivity of the interrogator 32. The output of the filter 94 is provided to an amplifier 96, which increases the level of the received signal and thus increases the sensitivity of the interrogator 32.

The output of the amplifier 96 is provided to a detector 98, which converts the analog output of the amplifier 96 to a digital signal. If the output of the amplifier 96 indicates that a pulse was received from one of the tags 34-36, the output of the detector 98 is a digital logic "1". If the output of the amplifier 96 indicates that no pulse was received from one of the tags 34-36, the output of the detector is a logic "0".

The output of the detector 98 is provided to a microprocessor circuit 100, which interacts with user input/output devices (described in more detail hereinafter) to indicate the presence or absence of various ones of the tags 34-36.

The microprocessor 100 also initiates outputting the RESET and TAG pulses 52a-d, shown in FIG. 2 and described above, by providing signals to a power amplifier 102. The power amplifier 102 also receives the sinusoidal signal from the oscillator 92, discussed above. The power amplifier 102 uses the signals from the microprocessor 100 and the oscillator 92 to generate the output signals of the interrogator 32. The output of the power amplifier 102 is provided to the hybrid 82 which transmits the signals via the antenna 81.

The microprocessor 100 also controls operation of the switch 86. When the microprocessor 100 initiates transmission by the interrogator 32, the microprocessor 100 provides a signal to the switch 86 causing the switch 86 to disconnect the output of the filter 84 from the remainder of the receive portion of the interrogator 32. After the interrogator 32 has transmitted a signal, the microprocessor 100 provides a signal to the switch 86 to reconnect the

output of the filter 84 to the remainder of the receive portion of the interrogator 32.

Referring to FIG. 5, an exemplary embodiment of one of the tags 34-36 is shown using the reference numbers from the schematic block diagram 60 of FIG. 3 superimposed thereon.

The antenna 62 can be implemented as a 1/4 wavelength patch antenna made from any one of a variety of suitable high dielectric constant materials, such as Duroid 6010.5 material manufactured by the Rogers Corporation of Chandler, Arizona. In a preferred embodiment, the material is .025 inches thick and is 1 inch by 1 inch square with copper on both sides to provide a dielectric constant of approximately 10.5, one side being a radio frequency ground and the other side being the antenna. FIG. 5 shows that there are two feed points for the antenna 62: One corner which is designated as ANT1B1 on the schematic 60 and the other corner which is designated as ANT1A1 on the schematic 60. On the opposite side of the feed points, the ground and the antenna copper pieces are shorted together. The impedance at the shorted points is zero ohms. Since the antenna is 1/4 wavelength long, the zero ohm impedance transfers to a high impedance at the feed points. Since the feed points are of high impedance, a high radio frequency voltage, low

current point is established. This configuration increases the radio frequency voltage presented to the detector 64 and increases the radio frequency sensitivity of the tag.

Due to the properties of the material used to make the antenna 62, the size of the antenna 62 can be reduced and the thickness is relatively thin. The antenna 62 has a high Quality factor and a narrow bandwidth. Radio frequency signals transmitted outside the frequency of the device are attenuated by the antenna 62, thus providing input filtering to the device.

The detector 64 is comprised of an inductor, a diode, and a capacitor, respectively labeled LI, Dl and C3. The inductor, LI, and the capacitor, C3, provide impedance matching to the diode, Dl. The diode Dl is a Zero Bias Shottkey diode, which is a sensitive radio frequency detector that does not require any DC bias. Accordingly, the detector 64 does not normally draw any current from a battery used to provide power to the tag. DC ground for the anode of the diode Dl is provided by the shorted end of the antenna 62. Detected pulses are present on the cathode side of the diode Dl.

The amplifier 66 comprises the elements labelled Cl, R3, RI, U1:D, C2, R4, R2, U1:E, R5, R6, and UI:F. The elements labeled U1:D, U1:E, and U1:F are part of a single integrated circuit designated as UI. The main amplification elements are U1:D, U1:E, and U1:F, which are low current

CMOS invertors that are biased as amplifiers. The amount of gain of the amplifiers is set by feedback resistors RI and R2 and input resistors R3 and R4. Cl and C2 are DC blocking capacitors. In order to reduce interference, the output of the second amplifier, U1:E, is divided by R5 and R6. The DC threshold is set below the switching threshold of U1:F, thus guaranteeing that the output of U1:F will be a logic high with no radio frequency energy present. As the detector 64 outputs detected radio frequency energy, the threshold of U1:F is crossed and the output of U1:F changes from a logic "1" to a logic "0" .

The clock 68 provides pulse shaping for input to the counter 72. The clock circuit consists of CMOS invertors labeled U1:C and U1:A. The output of the amplifier 66 is fed into the input of U1:C. The CMOS invertors help produce square digital pulses that are used to clock the counter 72.

The integrator 70 generates a LOAD signal upon detection of two relatively long digital pulses (100 usec)

separated by a relatively short time (10 usec) . The LOAD command loads the tag number (i.e., the LOAD VALUE shown on the schematic 60, and discussed above) which is the starting point for the counter 72. The integrator 70 consists of U1:B, R7, C4, U6:D, U6:E, and U6:C. UI:B provides isolation between the resistor-capacitor network and the circuitry of the clock 68. The output of Ul-.B is normally zero volts with no detected radio frequency energy. When radio frequency energy is detected, the output of U1:B goes high. The voltage across the capacitor, C4, begins to increase based on the charging current generated through R7. The voltage across C4 is a ramp voltage increasing with time. The ultimate charging voltage is dependent upon the time length of the pulse coming into the integrator 70. For a short pulse, the voltage across C4 will rise to a low level. For a relatively long pulse, the voltage across C4 will rise to a high level. A LOAD signal is generated when the radio frequency pulse is a long pulse. The voltage across C4 increases above the switching threshold of U6:D, causing the output of U6:D to change logic levels.

When the radio frequency pulse transmitted by the interrogator 32 is a clock pulse, the pulse width is narrow. The voltage across C4 increases, but only slightly. The switching threshold of U6:D is not crossed. Therefore, the

output of U6:D does not change. U6:E and U6:C are used to provide pulse shaping and logic inversion in order to create the correct signals for the counter 72.

The counter 72 consists of U2, U3, U4, and U5. More or less individual counter circuits can be used in order to increase or decrease, respectively, the number of bits used by the counter 72 and hence increase or decrease the maximum possible number of tags. For the embodiment shown herein, U2, U3, U4, and U5 are each four bit counters that are cascaded so that the counter 72 shown in FIG. 5 is a 16 bit counter. The overflow output of U2 is used to clock U3; the overflow output of U3 is used to clock U4; the overflow output of U4 is used to clock U5; and the overflow output of U5 is the overflow signal output by the counter 72. U2 is clocked by the output of the clock 68.

The LOAD VALUE signal, discussed above in connection with the schematic 60 of FIG. 3, is shown in FIG. 5 as a multibit input to U2, U3, U4, and U5. The counter 72 takes on the value of the LOAD VALUE signal whenever the LOAD signal from the integrator 70 is provided, as discussed above. Note that the LOAD VALUE signal can be hardwired into the tag or, for some applications, can instead be user

selectable via an appropriate type of selection device, such as a DIP switch or a rotary switch.

The oscillator 74 has a first stage, consisting of C5, R9, U6:B, R8, and Ql, that acts as a switch to turn the oscillator 74 on and off. When the counter 72 has received a number of clock pulses equal to the assigned unique value of the tag, the counter 72 provides the OVERFLOW signal to the first stage of the oscillator 74. The OVERFLOW signal is differentiated by C5 and R9 into a narrow pulse. U6 shapes the narrow pulse into a square pulse and drives the bias transistor Ql . Ql turns on momentarily and provides a DC bias to the second stage of the oscillator 74.

The second stage of the oscillator consists of Q2, L2, C7, RIO, R12, L4, C9, and CIO. The second stage generates the radio frequency signal when the DC bias is supplied by Ql . A third stage of the oscillator 74 consists of Q3 , L3 , C8, R15 and Cll. The third stage of the oscillator 74 amplifies the output of the second stage of the oscillator 74 and also provides isolation between the antenna 62 and the oscillating element Q2. The output of the third stage of the oscillator is coupled to the antenna 62. The resistors Rll, R13, and R14 provide interstage isolation.

The interrogator 32 is designed to receive tag signals from 912 MHz to 918 MHz. Therefore, the tag frequency of the oscillator 74 is between these limits. The interrogator 32 utilizes a low pass filter which accepts low frequencies and rejects high frequencies. This allows the tolerance of the oscillator 74 to be relaxed. Accordingly, the oscillator 74 does not require any fine tuning, thus reducing manufacturing costs.

The oscillator 74 does not draw any current unless a signal is being transmitted. When answering the interrogator 32, the oscillator 74 is activated for a short period of time. The oscillator 74 can drift in frequency by about 6 MHz, between 912 MHz and 918 MHz, and the interrogator 32 will still receive the response provided by the oscillator 74.

Referring to FIG. 6, an exemplary embodiment of the receiving portion of the interrogator 32 is shown using the reference numbers from the schematic block diagram 80 of FIG. 4 superimposed thereon.

The input filter 84 is a two section, helical resonating filter and is a purchased part, available from Toko America of Mount Pleasant Illinois.

The switch 86 is coupled to the filter 84 and receives a control signal from the microprocessor 100. Isolation for tne switch 86 is provided by diodes D4, D2 and D3. Diodes are turned "ON" by applying a forward current through the diode. During the "ON" state of the switch 86, the diodes D4 and D3 are biased "ON" and the diode D2 is biased "OFF" through L3. The diodes D4 and D3 provide a low series impedance while diode D2 provides a high shunt impedance. When the switch 86 is in the "OFF" state, the diodes D4 and D3 are biased "OFF" and the diode D2 is biased "ON". The diodes D4 and D3 provide a high series impedance while the diode D2 provides a low shunt impedance. The control signal is provided by the output of U7.

The diodes D5 and D6 are biased "ON" during the "OFF" state of the switch 86. The diodes D5 and D6 allow radio frequency energy to pass through DC blocking capacitors C21 and C22 and into the load resistors R12 and R13. The resistors R12 and R13 provide input and output impedance matching when the switch 86 is in the "OFF" state. Bias for the diodes D5 and D6 is provided through L4, R14, L5, and R15. Capacitors C23, C24, and C25 provide radio frequency bypass for the bias circuit. The control input to the switch 86 is provided by the microprocessor 100 and is applied to the negative input of U7. The positive input to

U7 is biased at 2.5 volts and determines the transition voltage for the switch 86. A DC bias path for the switching diodes is provided by L2 and is also provided by the characteristics of the input filter 84.

The low noise amplifier 88 includes silicon monolithic integrated circuits, manufactured by Hewlett-Packard of Palo Alto, California. U5 and U6 are the actual amplifier elements. Resistors R9 and RIO provide DC bias to the amplifiers with C12 and C13 providing radio frequency bypass. C17, C18, and C19 are DC blocking capacitors.

The mixer 90 down-converts the radio frequency output of the low noise amplifier 88 to an intermediate frequency and also amplifies the signal. The active elements of the mixer 90 include a silicon bipolar monolithic microwave integrated circuit (MMIC) manufactured by Hewlett-Packard of Palo Alto, California. The mixer consists of U4, capacitor C16, C14, C9, and CIO, which act as radio frequency bypass capacitors. The intermediate frequency signal is passed into DC blocking capacitor C15.

The oscillator 92 provides two outputs: a local oscillator signal for the mixer 90 and a radio frequency output signal to the power amplifier 102. The oscillator

consists of U8, L7, and C26. Capacitor C26 sets the frequency of the oscillator 92 and is adjusted to the frequency of 915 MHz. U8 is a radio frequency amplifier. L7 and C26 provide a radio frequency feedback path with the proper phase shift. The output power of the oscillator is divided and provided as the two separate outputs of the oscillator 92. Separation is accomplished with a lumped element power divider consisting of C29, L6, L9, C27, C30, and R21, which equally divides the oscillator power for the mixer 90 and the power amp 102. Resistors R23, R22 and R24 provide additional isolation within the oscillator 92. DC bias for the oscillator 92 is provided through L8, Ql, R16, D7, D8, and R19. The frequency of operation of the oscillator 92 is dependent upon the DC bias. As the temperature changes, the characteristics of U8 will change and cause a frequency drift of the oscillator 92. Diodes D7 and D8 provide temperature compensation for the DC bias in order to reduce the effect of temperature on the oscillator 92. The basic amplifier current is set by the value of R16.

The filter 94 processes the output of the mixer in order to prevent outside interference from falsely triggering the detector and to reduce the baseline noise level of the received portion of the interrogator 32. The

filter 94 is a passive, low-pass, filter consisting of LIO, C34, and L12. The filter 94 is designed with input and output impedances of 50 ohms.

The intermediate frequency amplifier 96 provides additional signal amplification and hence increases the sensitivity of the interrogator 32. The amplifier 96 contains silicon monolithic integrated circuits, manufactured by Hewlett-Packard of Palo Alto, California. U2 and U3 are the actual amplifier elements. Resistors R5 and R6 provide DC bias to the amplifiers with Cl and C2 providing radio frequency bypass. C4, C6, and C15 are DC blocking capacitors.

The detector 98 converts the output of the amplifier 96 into a digital pulse such that the detector 98 outputs a digital logic "1" when the output of the amplifier 96 indicates the presence of a received signal and the detector 98 outputs a logic "0" when the output of the amplifier 96 indicates that no input signal is present. Actual detection occurs with one of the diodes in Dl. The other diode in Dl is used to provide a DC reference for the comparator UI.

Inductor LI provides a DC reference point for the detector 98. Resistor R8 provides the DC bias for the detector 98. Capacitor C5 provides high frequency bypass for the detected

signal. RI provides the DC bias for the threshold diode. The output of the comparator is a digital signal that is provided to the microprocessor 100.

Referring to FIG. 7, an exemplary embodiment of the transmission portion of the interrogator 32 is shown using the reference numbers from the schematic block diagram 80 of FIG. 4 superimposed thereon.

The hybrid 82 is a lump element design and consists of Cl, C2, C7, L2, R2, R3, L4, R7, C13, R4, L5, R8, C14, R9,

L10, and C12. These elements are used to transform the radio frequency impedances to the required levels. The design of the hybrid 82 shown in FIG. 7 is conventional and familiar to one of ordinary skill in the art. Note that it is also possible to use other hybrid designs including a microstrip, printed hybrid.

The power amplifier 102 provides two functions: boosting the output of the oscillator 92 and providing amplitude modulation to the radio frequency signal. The power amplifier 102 includes U2 and is similar to conventional power amplifiers used in cellular phones. The output of the power amplifier 102 is proportional to the input modulation DC level. The modulation signal from the

microprocessor 100 is provided to RIO and controls the DC level of the modulation and thus the transmitted output power. The modulation signal is mixed with the signal from the oscillator 92 through C18 and Lll. C19 provides DC blocking for the modulation. Inductors L7, L8, and L9 and capacitors C15, C16, C17, and Cll provide bias in bypass for the intermediate amplifier stages of U2. The output of U2 is fed to the hybrid 82.

Referring to FIG. 8, the microprocessor 100 is a conventional microprocessor system that includes ROM (read only memory) for storing program code and RAM (random access memory) for storing volatile program data and variable values. The user I/O 101 includes a display 110 for displaying results of the interrogation and other data provided by the microprocessor 100 and a keypad 112 for allowing a user to enter data and to initiate an interrogation. The display 110 can be a conventional off-the-shelf LCD assembly consisting of 1 line by 16 character LCD glass and interface logic, purchased as a single assembly. A variety of conventional LCD devices and interface logic parts are available and known to one of ordinary skill in the art.

The user I/O 101 also includes a keypad 112 which provides a method for entering data into the microprocessor 100. The keypad 112 can be used to enter information such as a type of interrogation, tag numbers, number of responses, and other interrogator functions. The keypad 112 can be a conventional off-the-shelf, 16-key, keypad containing the numbers 0 through 9, cursor keys, a mode key, a start key, a stop key, and an enter key. The numbers 0-9 can allow the user to enter tag numbers. The cursor keys can allow the user to change data when errors are made during entering of data, the mode key can be used for entering the mode of interrogation, the start key can start the interrogation, the stop key can stop the interrogation, and the enter key can be used to enter data.

The interface to the computer can be a conventional

RS-232 interface 114. The RS-232 interface 114 can provide the same data to and from the microprocessor 100 that is provided to and from the user I/O 101. The RS-232 interface 114 is implemented in a conventional manner familiar to one of ordinary skill in the art.

Referring to FIG. 9, a flowchart 120 illustrates operation of a portion of the software for the microprocessor 100 that handles interrogating the tags 34-

36. Execution begins at a first step 122 where the data for the microprocessor 100 is initialized and the TAGRES variable is cleared. The TAGRES variable is a byte that indicates the presence or absence of up to eight tags, where each bit represents one tag. Following the step 122 is a step 123 where the transmitter is turned on. Following the step 123 is a step 124 where the processor 100 waits for 100 microseconds. Following the step 124 is a step 125 where the transmitter is turned off. Following the step 125 is a step 126 where the microprocessor 100 waits for 10 microseconds. Following the step 126 is a step 127 where the microprocessor 100 turns on the transmitter. Following the step 127 is a step 128 where the microprocessor 100 waits for 100 microseconds. Following the step 128 is a step 129 where the microprocessor 100 turns off the transmitter. The steps 122-129 of the flowchart 120 represent transmission of the RESET pulse by the interrogator 32. The RESET pulse 52a is shown in FIG. 2 and described elsewhere herein.

Following step 129 is a step 132 where the microprocessor 100 waits for 100 microseconds prior to transmitting the first TAG pulse. Following the step 132 is a step 133 where the microprocessor turns on the transmitter. Following the step 133 is a step 134 where the

microprocessor waits for one microsecond. Following the step 134 is a step 135 where the microprocessor 100 turns off the transmitter. The steps 133-135 represent transmitting one of the TAG pulses 52b-d, which is illustrated in FIG. 2 and described elsewhere herein.

Following step 135 is step 138 where the processor waits for one microsecond after turning off the transmitter. Following the step 138 is a step 139 where the microprocessor 100 determines if a RESPONSE signal has been received. Since, as discussed above and as shown in FIG. 2, the RESPONSE signal is 4 microseconds long, then the step 138 where the processor waits 1 microsecond will cause the test step 139 to be executed approximately 1/4 of the way into the RESPONSE signal.

If the microprocessor 100 determines that a RESPONSE signal has been received, then control transfers from the test step 139 to a step 140 where the microprocessor waits for 2 microseconds. Following the step 140 is a test step 141 where the microprocessor determines if the RESPONSE signal is still present. Note that, as shown in FIG. 2 and as discussed above, since the RESPONSE signal is 4 usec long, then the step 141 is executed approximately 3/4 of the way into the tag RESPONSE signal.

The two test steps 139, 141 are executed in order to verify the results of determining the presence of a tag RESPONSE signal. It is possible that a RESPONSE signal is erroneously detected at the step 139 because of ambient noise or other noise sources. Accordingly, the step 140 of waiting 2 usec and the step 141 of performing the test again to confirm receipt of the tag RESPONSE signal increases the reliability of the system by performing two separate tests 139, 141, that are two usec apart.

If the tag response signal is detected at the step 141, then control passes from the step 141 to a step 144 where the microprocessor carry bit is set to indicate the presence of the tag that transmitted the RESPONSE signal. If, on the other hand, no RESPONSE signal is detected at the step 139 and at the step 141, then control transfers from the step 139 or the step 141 to a step 145 where the carry bit is cleared. Accordingly, the steps 144, 145 illustrate that the carry bit is set to indicate the presence of a particular tag and is cleared to indicate the absence of a particular tag.

Following either the step 144 or the step 145 is a step 146 where the TAGRES variable is rolled right one bit. Since the TAGRES variable is 1 byte, and since the carry bit

is rolled into the far left bit of the TAGRES variable at the step 146, then at the step 146, the left-most bit of TAGRES will be set if the particular tag is present or will be cleared if the particular tag is not present. Following the step 146 is a step 148 where the processor waits one usec. The one usec wait at the step 148 corresponds to the remaining microsecond in the tag response signal and is used for timing purposes.

Following step 148 is a step 150 which determines if eight tags have been interrogated. If not, then control transfers from the step 150 back to the step 133 where the transmitter is turned on again to transmit the next TAG signal. Otherwise, if it is determined at the step 150 that eight tags have been interrogated, then control transfers from the step 150 to a step 151 where the byte that represents the TAGRES variable is saved to RAM. The TAGRES byte represents the state of eight tags wherein each bit indicates whether a particular tag is present or absent . Following the step 151 is a test step 152 which determines if all of the tags of the system 30 have been interrogated. If not, then control transfers from the step 152 back to the step 133 to transmit the next TAG signal. Otherwise, processing is terminated at the step 152 after all the tags have been interrogated.

Modifications and variations of the above-described embodiments of the present invention are possible, as appreciated by those skilled in the art in light of the above teachings. It is therefore to be understood that, within the scope of the appended claims and their equivalents, the invention may be practiced otherwise than as specifically described.