Title:
IMAGE PROCESSING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2023/134417
Kind Code:
A1
Abstract:
An image processing circuit (1000). The image processing circuit (1000) has: a first processing circuit, which executes noise reduction processing for reducing the noise of an image; a second processing circuit, which executes super-resolution processing for improving the resolution of the image; a calculation circuit, which calculates, on the basis of respective intensity settings of the noise reduction processing and the super-resolution processing, a synthesis ratio that represents the ratio of a plurality of images to be synthesized; a neural network circuit (1007), which executes the noise reduction processing or the super-resolution processing on the basis of the intensity setting; a first synthesis circuit (1008), which synthesizes, on the basis of the synthesis ratio, an image on which the noise reduction processing has been implemented by the first processing circuit and an image on which image processing has been implemented by the neural network circuit (1007); and a second synthesis circuit (1010), which synthesizes, on the basis of the synthesis ratio, an image on which the super-resolution processing has been implemented by the second processing circuit and the image on which the image processing has been implemented by the neural network circuit (1007).
Inventors:
MORI SHIZUKA (JP)
Application Number:
PCT/CN2022/140689
Publication Date:
July 20, 2023
Filing Date:
December 21, 2022
Export Citation:
Assignee:
HISENSE VISUAL TECH CO LTD (CN)
TVS REGZA CORP (JP)
TVS REGZA CORP (JP)
International Classes:
G06T5/00
Foreign References:
| CN101646034A | 2010-02-10 | |||
| US20190114742A1 | 2019-04-18 | |||
| CN106165395A | 2016-11-23 | |||
| JP2015108897A | 2015-06-11 | |||
| CN110705699A | 2020-01-17 | |||
| CN110428378A | 2019-11-08 | |||
| US20200372612A1 | 2020-11-26 | |||
| US20190108629A1 | 2019-04-11 |
Attorney, Agent or Firm:
TDIP & PARTNERS (CN)
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