Title:
IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD
Document Type and Number:
WIPO Patent Application WO/2014/069433
Kind Code:
A1
Abstract:
A dividing circuit (11) divides input frames contained in input video (Vi) into a plurality of partial data items that do not overlap each other, and while switching the selection of partial data, outputs one partial data item for one input frame. A memory control circuit (14) writes partial data output from the dividing circuit (11) to a frame memory (15), and reads from the frame memory (15) reconstructed frames having the same size as the input frames and consisting of a plurality of partial data items that are based on the plurality of input frames that are mutually different. A combining circuit (19) combines the reconstructed frames read from the frame memory (15) and finds output video (Vo) containing the combined frames. As a result of the foregoing, without substantially reducing image quality, the access rate related to frame memory is reduced.
Inventors:
TANAKA YUHJI
MIKAMI HIROSHI
MIKAMI HIROSHI
Application Number:
PCT/JP2013/079202
Publication Date:
May 08, 2014
Filing Date:
October 29, 2013
Export Citation:
Assignee:
SHARP KK (JP)
International Classes:
H04N5/66; G09G5/00; G09G5/36; G09G5/377; G09G5/393; G09G5/395
Foreign References:
| JP2003298938A | 2003-10-17 | |||
| JP2002182639A | 2002-06-26 | |||
| JP2002182632A | 2002-06-26 | |||
| JPH05143043A | 1993-06-11 |
Attorney, Agent or Firm:
SHIMADA, AKIHIRO (JP)
Akihiro Shimada (JP)
Akihiro Shimada (JP)
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