TECHNICAL FIELD

[0001] The present disclosure relates to the field of electronic image sensors, and more specifically to a sampling architecture for use in such image sensors.

BACKGROUND

[0002] Digital image sensors, such as CMOS or CCD sensors, include a plurality of photosensitive elements ("photosensors") each configured to convert photons incident upon the photosensors ("captured light") into electric charge. The electric charge can then be converted into image data representing the light captured by each photosensor. The image data includes a digital representation of the captured light, and may be manipulated or processed to produce a digital image capable of display on a viewing device. Image sensors are implemented in integrated circuits ("ICs") with a physical surface that may be divided into a plurality of pixel regions (for instance, one or more photosensors and attendant control circuitry) configured to convert light into an electrical signal (charge, voltage, current, etc.). For convenience, pixel regions within an image sensor may also be referred to as image pixels ("IPs") and the aggregate of the pixel regions or image pixels will be referred to as the image sensor region. An image sensor IC typically will also include areas outside of the image sensor region, for example certain types of control, sampling, or interface circuitry. Most CMOS image sensors contain A/D (analog-to-digital) circuitry to convert pixel electrical signals into digital image data. The A/D circuitry can be one or more ADCs (analog-to-digital converters) located within or at the periphery of the image sensor region.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The various embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0004] Fig. 1 illustrates a cross-section of a portion of an image sensor, according to one embodiment.

[0005] Fig. 2 illustrates partial array circuitry of an analog pixel image sensor with multiple pixel signal thresholds, according to one embodiment useful, e.g., in the layout of Fig. 1. [0006] Fig. 3 illustrates an example image sensor read circuit configured to convert a pixel signal into a multi-bit digital conversion, according to one embodiment useful, e.g., with the embodiments of Figs. 1 and 2.

[0007] Fig. 4 illustrates an example circuit block diagram embodiment of an image sensor system with a multi-bit architecture, according to one embodiment using, e.g., the cross-section of Fig. 1 and the circuitry of Figs. 2 and 3.

[0008] Fig. 5 illustrates another example circuit block diagram of an image sensor system architecture with read circuit arrays located peripherally to an IP array, according to one embodiment using, e.g., the cross-section of Fig. 1 and the circuitry of Figs. 2 and 3.

[0009] Fig. 6a illustrates a top view of a pixel array IC in an example two-layer image sensor system architecture alternative to Figs. 4 and 5, according to one embodiment using, e.g., the array circuitry of Fig. 2.

[0010] Fig. 6b illustrates a top view of a preprocessor IC in an example two-layer image sensor system architecture alternative to Figs. 4 and 5, according to one embodiment using, e.g., the read circuitry of Fig. 3.

[0011] Fig. 6c illustrates a partial cross section of the pixel array IC of Fig. 6a and the preprocessor IC of Fig. 6b in an example two-layer image sensor system architecture, according to one embodiment.

[0012] Fig. 7 illustrates the operation of an image sensor read circuit, such as the read circuit of Fig. 3, according to one embodiment.

[0013] Fig. 8 illustrates data flow in an image capture system, according to one embodiment useful with the systems described herein.

[0014] Fig. 9 illustrates various temporal sampling policies for use by an image sensor read circuit, such as the read circuit of Fig. 3, according to one embodiment.

DETAILED DESCRIPTION

[0015] In some image sensors, electrical information representing a photon response and resulting from light incident upon a pixel region (referred to herein as a "pixel signal") is converted to a digital image data value by read circuitry. The read circuitry can reside within the image sensor, or can be located external to the image sensor. In some approaches, a read circuit can be located within the image sensor for use by one or more pixel regions adjacent or near the read circuit. For read circuits located external to the image sensor, the pixel signals of one or more pixel regions associated with the read circuits can be transferred from the pixel regions to the read circuits. [0016] Each read circuit samples a pixel region, receives a pixel signal from the sampled pixel region, and converts the pixel signal to a multi-bit digital value representative of the pixel signal. In the event that a pixel signal or a digital value representative of the pixel signal exceeds a sampling threshold, the pixel signal stored at the pixel region associated with the pixel signal is reset (for instance, by resetting a photosensitive element associated with the pixel region). If the pixel signal or the digital value do not exceed the sampling threshold, the pixel signal stored at the pixel region is not reset. The sampling of a pixel region and the resetting of a pixel signal at the pixel region only when the pixel signal exceeds a sampling threshold is referred to herein as "non-destructive sampling with conditional reset."

Image Sensor Overview

[0017] Fig. 1 illustrates a partial cross-section of an image sensor 25 useful in an embodiment. In image sensor 25, light passing through a microlens array 10 and a color filter array 12 (useful for color imaging) is incident upon a silicon section 20 of the image sensor. The use of microlenses (or other concentrating optics) and color filters is optional and is shown here for illustrative purposes only. Silicon 20 contains photodiodes (not shown) to collect charge generated by photons absorbed by the silicon, and access transistors (also not shown) to operate the photodiodes. Pixel array IC wiring 14 provides connections used to route signals and supply voltages within the array. As shown, image sensor 25 is a BackSide Illuminated (BSI) sensor because light enters the silicon from the side of the integrated circuit opposite the wiring layers and primary active circuit formation. Optionally, pixel array IC wiring 14 can be arranged between the color filter array 12 and silicon 20 (with primary active circuit formation within the "top" of the silicon as oriented in Fig. 1) for FrontSide Illumination (FSI).

[0018] The image sensor 25 includes a plurality of IPs ("image pixels"), IP1-IP3 shown, upon which light collected by the lenses of the microlens array 10 is respectively incident. Each IP includes one or more photodiodes embedded within the silicon 20. At least some photons entering silicon 20 are converted to electron-hole pairs in the silicon and the resulting electrons (or holes in alternate embodiments) are collected by the IPs. The description herein will refer to this process as the capture and conversion of light by the IPs into image data for the purposes of simplicity. Each IP of the image sensor represents a portion of the surface area of the image sensor, and the IPs of the image sensor may be organized into various arrays of columns and rows. In a CMOS or CCD image pixel technology, each IP (for instance, each photosensor) converts light incident upon the IP into a charge and includes readout circuitry configured to convert the charge into a voltage or current. In one embodiment, the light captured by each IP of the image sensor represents one pixel of image data for an associated digital image, though in other embodiments image data from multiple IPs is combined to represent a fewer number (one or more) of pixels (downscaling).

[0019] The image sensor 25 may include components outside the IP array. Similarly, portions of the IP array may include components that do not convert light into charge. The region defined by the IPs in the aggregate will be referred to as the image sensor region. As described herein, the image sensor may include amplifiers, analog-to-digital converters ("ADCs"), comparators, controllers, counters, accumulators, registers, transistors, photodiodes, and the like. In different architectures, some of these components may be located within the image sensor region or external to the image sensor region, and some components may be located on a companion integrated circuit. In these embodiments, a lens (such as those of the microlens array 10) may be configured to direct light toward the actual light-sensing elements within the IP rather than, for example, on the amplifiers, comparators, controllers, and other components.

[0020] As noted above, an image sensor may include an array of multiple IPs. Each IP, in response to light (for instance, one or more photons), captures and stores a corresponding charge. In one embodiment, upon sampling an IP, if a pixel signal representative of the charge stored at the IP exceeds a sampling threshold, the pixel signal is converted to a digital value representing the pixel signal and the charge stored by the IP is reset. Alternatively, upon sampling an IP, a pixel signal representative of the charge stored at the IP is converted to a digital value representative of the pixel signal, and if the digital value exceeds a sampling threshold, the charge stored by the IP is reset. In other embodiments, an analog-to-digital conversion is begun, and when enough of the conversion has been completed to determine whether the threshold is exceeded, a determination is made as to whether to continue the conversion. For instance, in a successive approximation register ("SAR") ADC, if the threshold is equal to a most-significant-bit(s) pattern, as soon as the pattern is resolved a determination can be made as to whether to continue the conversion and perform a reset of the pixel, or stop the conversion. A determination of whether a pixel signal or a digital value representative of a pixel signal exceeds a sampling threshold can be made through the use of a comparator configured to compare the pixel signal or the digital value to a sampling threshold.

[0021] Fig. 2 illustrates an analog pixel image sensor with multiple pixel signal thresholds, according to one embodiment. The image sensor of Fig. 2 is a CMOS sensor, and includes an IP array 40. The IP array can include any number of columns and rows, with any number of IPs per column and per row. IP column 50, a column representative of full or partial IP columns in the IP array, is highlighted in Fig. 2. The IP column 50 includes a plurality of IPs communicatively coupled via the column line 55. IP 60, an IP representative of IPs in the IP array, is highlighted in Fig. 2.

[0022] The IP 60 includes a photo diode 65 together with control elements that enable the photo diode to be precharged in preparation for exposure and then sampled after exposure. In operation, a transistor 70 is switched on to couple the cathode of the photo diode to a voltage source and thus "precharge" the cathode of the photo diode to a precharge voltage. The transistor 70 is switched off at or before the start of an exposure interval. With the transistor 70 off, the cathode voltage incrementally discharges in response to photon strikes, lowering the photo diode potential, V _DET , in proportion to the amount of light detected. At the conclusion of the exposure interval, an access transistor 72 is switched on to enable a signal representative of the photo diode potential to be amplified/driven onto the column line 55 via follower-transistor 74 as pixel signal 80.

[0023] An ADC 85 is communicatively coupled to the IP column 50 via the column line 55. In the embodiment of Fig. 2, the ADC is located at the edge of the pixel array 40, and may be located within or external to the image sensor on which the IP array is located. The ADC receives the pixel signal 80 (the representation of the analog photo diode potential) from the IP 60. The ADC digitizes the pixel signal to generate a 3 -bit digital value

("Pix[2:0]") representative of the pixel signal. The ADC includes 7 pixel thresholds,

Threshold 1 to Threshold 7 (referred to herein as "V-π to Vn"). If the magnitude of the pixel signal is less than V _pre but greater than Vn, the ADC converts the pixel signal to the digital value "000". Pixel signals less than Vn but greater than V _T2 are converted to the digital value "001", pixel signals between V _T2 and V _T3 are converted to "010", and so forth, up to pixel signals less than V _T7 , which are converted to "111".

[0024] In the embodiment of Fig. 2, the potential difference between successive pixel thresholds is approximately the same (e.g., V _T3 - V _T4 ~ V _T5 - V _T6 ). In other words, the pixel thresholds are linearly distributed between Vn and V _T7 . In addition, in the embodiment of Fig. 2, the potential difference between V _pre and Vn is greater than the potential difference between successive pixel thresholds (e.g., V _pre - Vn > V _T3 - V _T4 ), although in other embodiments all steps are equal. The selection of Vn such that V _pre - Vn > V _T3 - V _T4 reduces the effect of, e.g., dark noise when sampling an IP. The potential difference between V _T7 and floor in the embodiment of Fig. 2 also can be greater than the potential difference between successive pixel thresholds (e.g., V _T7 - V _floor > V _T3 - V _T4 ). Finally, instead of linear threshold spacing, a given embodiment can space the thresholds exponentially, e.g., with each threshold spacing doubling from the one below. For systems that accumulate multiple ADC samples to form an image, exponential spacing is converted to a linear value prior to accumulation.

[0025] Vfloor represents the pixel saturation threshold at which the cathode voltage of the photo diode 65 no longer linearly discharges in response to photon strikes. For pixel signals within the linear sensitivity region 90, the conversion of pixel signals to digital values is shown in graph 95. It should be noted that the maximum number of detectable photon strikes (i.e., the pixel saturation point) is proportional to the capacitance of the photo diode and thus its physical size. Consequently, in a traditional sensor design the photo diode footprint is dictated by the dynamic range required in a given application and does not scale appreciably with shrinking process geometries.

[0026] During the capture of an image, in one embodiment the IPs of a given row or rows in the IP column 50 and each other column in the IP array 40 are successively sampled and the pixel signals associated with each are converted into digital values using the ADC or ADCs associated with each column. The digital values output by the ADCs are accumulated (conditionally in some embodiments, as explained below) and stored during the image capture period. Other types and configurations of IPs than that illustrated in Fig. 2 can be used in the image sensor system. For instance, a different arrangement of transistors can be used than the transistors 70, 72, and 74. In addition, although one ADC 85 is shown in Fig. 2 in conjunction with the IP column 50, in other embodiments, more than one ADC can be used per IP column, with different ADC groups serving different sections of the array rows of the ADC column. Additional combinations of ADCs (in the form of read circuits) and IPs are described below in greater detail. Finally, the output of the ADC (e.g. Pix[2:0] in the embodiment of Fig. 2) can be any multi-bit length, and can be associated with any number of thresholds distributed in any manner between V _pre and V _floor .

Image Sensor System with Multi-bit Sampling and Conditional Reset

[0027] Fig. 3 illustrates an example image sensor read circuit configured to convert a pixel signal into a multi-bit digital conversion, according to one embodiment. The embodiment of Fig. 3 illustrates an IP 100, an IP memory 116, and a read circuit 110, the read circuit including an ADC/comparator circuit 112 (hereinafter "ADC/comparator") and an adder 114. It should be noted that in other embodiments, the modules of Fig. 3 can include additional, fewer, and/or different components. For example, the ADC/comparator can be implemented as separate components, and the adder can be located external to the read circuit.

[0028] The IP 100 represents an IP in an image sensor, and can be, for instance, the IP 60 of Fig. 2. The IP 100 receives one or more control signals, for instance from external control logic. A control signal can enable the IP to begin an image capture, for instance by resetting the IP to Vpre and enabling the exposure of the IP's photosensitive element to light to result in the storing of charge relative to Vpre. Similarly, a control signal can enable the IP to end an image capture, for instance by disabling the exposure of the IP's photosensitive element to light after the passing of an image capture period. A control signal can also enable the outputting of a pixel signal by an IP and the subsequent conversion of the pixel signal to a digital value representative of the pixel signal by a read circuit (referred to herein as

"sampling the IP" or "sampling the pixel signals"). As described above, a pixel signal can be a representation of the integrated charge (e.g., a source follower voltage, an amplified voltage, or a current having a component proportional to the integrated charge).

[0029] The IP 100 receives a reset signal, for instance from external control logic. The reset signal resets the charge stored by the IP to Vpre, for instance at the beginning of an image capture period. The IP also receives a conditional reset signal from the

ADC/comparator 112 (in some circuits, the conditional reset and initial reset are supplied using common circuitry). The conditional reset signal resets the charge stored by the IP, for instance during an image capture period in response to a pixel signal exceeding a sampling threshold when the IP is sampled. It should be noted that in other embodiments, the conditional reset signal is received from a different entity. In one implementation, the ADC/comparator may determine that the pixel signal exceeds a sampling threshold, and may enable external control logic to output a conditional reset signal to the IP; in such an embodiment, the reset signal (a row-wise signal) and the conditional reset signal (a columnwise signal) may be ANDed by the IP to initiate all resets. For simplicity, the remainder of the description will be limited to embodiments in which the ADC/comparator provides conditional reset signals to the IP.

[0030] The read circuit 110 receives a threshold signal, a sample signal (or "sample enable signal"), a compare signal (or "compare enable signal"), a residue signal (or "residue enable signal"), and a reset signal, for instance from external control logic, and receives pixel signals from the IP 100. The IP memory element 116 corresponding to IP 100 receives a readout signal that selects it for readout/write by adder 114 and for external readout. The ADC/comparator 112 samples the IP 100 in response to receiving one or more sample signals. During an image capture, the ADC/comparator receives a sample signal at various sampling intervals, for instance periodically or according to a pre-defined sampling interval pattern (referred to herein as a "sampling policy"). Alternatively, the sample signal received by the ADC/comparator can include a sampling policy, and the ADC/comparator can be configured to sample the IP based on the sampling policy. In other embodiments, the IP receives one or more sample signals and outputs pixel signals based on the received sample signals. In yet other embodiments, the IP outputs pixel signals periodically or according to a sampling policy, or the ADC/comparator samples pixel signals periodically or according to a sampling policy, independent of received sample signals. The ADC/comparator can request a pixel signal from the IP prior to sampling the pixel signal from the IP.

[0031] During a sampling of the IP, the ADC/comparator 112 receives a pixel signal from the IP and converts (optionally in some embodiments based on the pixel signal exceeding the sampling threshold) the pixel signal to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the ADC/comparator outputs a conditional reset signal to reset the charge stored at the IP. If the pixel signal does not exceed a sampling threshold, the ADC/comparator does not output a conditional reset signal to reset the charge stored at the IP. The sampling threshold can be varied during the image capture and received via the threshold signal, or can be pre-determined or preset for a given image capture. One sampling threshold can be used during multiple image captures, different sampling thresholds can be used for different image captures, and multiple sampling thresholds can be used during a single image capture. In one embodiment, the sampling threshold varies in response to detected changing light conditions (for instance, the sampling threshold can decrease in response to low light conditions, and can increase in response to high light conditions).

[0032] In one embodiment, the sampling threshold is an analog signal threshold. In this embodiment, the ADC/comparator 112 includes an analog comparator and compares the pixel signal to the sampling threshold to determine if the pixel signal exceeds the sampling threshold. If the pixel signal includes a voltage representative of the charge stored by the IP 100, the sampling threshold is exceeded if the pixel signal is lower than the sampling threshold. Using the embodiment of Fig. 2 as an example, if the sampling threshold of the ADC/comparator is Threshold 4, then the pixel signal will exceed the sampling threshold only if the pixel signal includes a voltage lower than the voltage associated with Threshold 4.

[0033] In one embodiment, the sampling threshold is a digital signal threshold. In this embodiment, the ADC/comparator 112 includes a digital comparator, and first converts the pixel signal to a digital value representative of the pixel signal. The ADC/comparator then compares the digital value to the sampling threshold to determine if the pixel signal exceeds the sampling threshold. Using the embodiment of Fig. 2 as an example, for a sampling threshold of "101", if the ADC/comparator converts a pixel signal to a digital value of "001" (indicating that the pixel signal is between Threshold 1 and Threshold 2), then the pixel signal does not exceed the sampling threshold and a conditional reset signal is not outputted. However, if the ADC/comparator converts a pixel signal to a digital value of "110"

(indicating that the pixel signal is between Threshold 6 and Threshold 7), then the pixel signal does exceed the sampling threshold and a conditional reset signal is outputted.

[0034] In another embodiment, the sampling threshold is a digital signal threshold that can be evaluated prior to the complete digital conversion of the pixel signal. This can be advantageous in some embodiments or use cases to allow faster conditional reset of a pixel, and/or power savings by avoiding unneeded ADC operations. For instance, with a successive approximation register ADC, multiple clock cycles are used to resolve the digital

representation of the pixel signal. The first clock cycle resolves the most significant bit, the second clock cycle the next most significant bit, etc., until all bit positions have been resolved. Using the embodiment of Fig. 2 as an example, for a sampling threshold of "100," a determination of whether the threshold is met or not can be resolved after the first SAR ADC clock cycle. For a sampling threshold of "110," a determination of whether the threshold is met or not can be resolved after the second SAR ADC clock cycle. For embodiments with a bit depth of, e.g., 6 or 8 bits, making a reset determination after one or two conversion cycles can result in significant time/power savings, which can be realized by selecting a sampling threshold with one or more LSBs that are 0.

[0035] In one embodiment, a row-wise compare signal is supplied to each

ADC/comparator "compare" signal input, and signals the ADC/comparator as to the appropriate clock cycle to perform the comparison. When the compare signal is asserted, the comparison is performed based on the current state of the analog-to-digital conversion. If the threshold is met by the compare for ADC/comparator 112, the conditional reset signal is asserted to IP 100 and to adder 114, and the SAR ADC continues converting the pixel signal. If the threshold is not met, the conditional reset signal is not asserted, and can be used in conjunction with the compare signal to gate the clock signal of SAR ADC to terminate the conversion.

[0036] The ADC/comparator 112 outputs a digital value representative of a pixel signal received by the ADC/comparator (referred to herein as a "digital conversion") to the adder 114. The ADC/comparator 112 can output a digital conversion in response to the pixel signal associated with the digital conversion exceeding a sampling threshold. The conditional reset signal can be used as an enable to signal to the adder 114 to load the digital conversion and add it to the IP memory 116 location corresponding to IP 100 (which in this embodiment is selected from a plurality of such locations by address selection of the readout line). In other embodiments, the ADC/comparator outputs a digital conversion during each sampling of the IP 100, regardless of whether the pixel signal associated with the digital conversion exceeds a sampling threshold. In these embodiments, the adder can be configured to accumulate digital conversions associated with pixel signals that exceed a sampling threshold and to disregard digital conversions associated with pixel signals that do not exceed a sampling threshold. Alternately, if the threshold is set to "001" in Figure 2, for example, the adder can

unconditionally add the digital conversion to IP memory 116 each time IP 100 is read, while still producing correct results.

[0037] In one embodiment, the ADC/comparator 112 also outputs a digital conversion in response to receiving a residue signal assertion (without the compare signal being asserted). The residue signal assertion is associated with the end of an image capture, and enables the ADC/comparator to output a full digital conversion to the adder 114 regardless of whether the pixel signal associated with the digital conversion exceeds a sampling threshold, and asserts the conditional reset. The residue signal can prevent the loss of image information associated with light received by the IP 100 but not surpassing the threshold at the end of a capture period. If the pixel signal representative of such received light does not exceed the sampling threshold, the ADC/comparator otherwise may not output the digital conversion associated with the pixel signal, and the charge stored by the IP would not be reset by the conditional reset signal (which is also triggered by assertion of the residue signal). In embodiments where the ADC/comparator outputs digital conversions to the adder regardless of whether the pixel signals associated with the digital conversions exceed a sampling threshold, the adder can receive the residue signal, and can be configured to accumulate a digital conversion associated with a pixel signal received at the end of a capture period in response to receiving the signal.

[0038] The adder 114 is configured to accumulate digital conversions received during a capture period. As discussed above, in embodiments in which the ADC/comparator 1 12 outputs digital conversions only if the pixel signals associated with the digital conversions exceed a sampling threshold, the adder accumulates all received digital conversions

(including the additional digital conversion output by the ADC/comparator in response to receiving a residue signal) into IP memory 116. In embodiments in which the ADC/comparator outputs digital conversions associated with each received pixel signal, the adder accumulates only the digital conversions associated with pixel signals that exceed the sampling threshold, plus the digital conversion output by the ADC/comparator in response to receive a residue signal, into IP memory 116; such embodiments require the adder to be aware of when pixel signals exceed a sampling threshold and when a residue signal is received, and are not discussed further herein for the purpose of simplicity.

[0039] The adder 114 receives reset/add control signaling, for instance from external control logic. In response to receiving a reset signal (for instance at the beginning of an image capture period), the accumulator stores all zeros to the selected IP memory location 116 the accumulation of received digital conversions as image data. The adder also receives a reset signal and resets the accumulation of received digital conversions.

[0040] In alternative embodiments, the adder is located external to the read circuit 110. For instance, the ADC/comparator can output a stream of conversions to a digital channel (e.g., multiplexed with other conversions from other ADCs) to a separate circuit that supplies the accumulation function. In such a case, the ADC/comparator must also output a symbol for "no conversion," which can be 0. One possibility is for a circuit in the digital channel interface (e.g., PHY 134 in Fig. 4) to code digital conversions to reduce bandwidth. A "no conversion" in one embodiment is output as a "00," a upper threshold exceeded ADC conversion is output as a "01," and all other ADC conversions are output as "lxxxxxx," where an x represents one of the resolved bits of the ADC conversion and the number of x positions is equal to the bit depth of the ADC.

[0041] In one embodiment, the IP is configured to output a pixel signal and receive a conditional reset on the same line. In this embodiment, the IP and the ADC/comparator 112 alternately drive the pixel signal and the conditional reset on the shared line. For example, the IP can output a pixel signal on the shared line during a first portion of a sample period, and can receive conditional resets on the shared line during a second portion of a sample period. Finally, the ADC/comparator can receive a threshold signal, a sample signal, and a residue signal on a shared line. For example, the ADC/comparator can receive a threshold signal at the beginning of an image capture, can receive sample signals throughout the image capture period, and can receive a residue signal at the end of the image capture period. It should also be noted that the reset signal received by the IP can be the same reset signal received by the accumulator 114, and can be received on a shared line. [0042] Fig. 4 illustrates an example embodiment of an image sensor system with a multi- bit architecture, according to one embodiment. The image sensor system 120 of Fig. 4 includes an image sensor region 125, a read circuit array 130, control logic 132, and a physical signaling interface 134. In other embodiments, the image sensor system may include fewer, additional, or different components than illustrated in the embodiment of Fig. 4 (for instance, the circuit may have memory 116 integrated therewith). The image sensor system shown in Fig. 4 can be implemented as a single IC, or can be implemented as multiple ICs (for instance, the image sensor region and the read circuit array can be located on separate ICs). Further, various components (such as the read circuit array, the control logic, and the physical signaling interface) can be integrated within the image sensor region 125.

[0043] For purposes of example, the image sensor system 120 and a host IC (not shown in Fig. 4) communicatively coupled to the image sensor system are assumed to form the primary image acquisition components within a camera (e.g., a still-image or video camera within a mobile device, compact camera, digital SLR camera, stand-alone or platform- integrated webcam, high-definition video camera, security camera, automotive camera, etc.). The image sensor IC and host IC can be more generally deployed alone or together with like or different imaging components within virtually any imaging system or device including without limitation metrology instruments, medical instruments, gaming systems or other consumer electronics devices, military and industrial imaging systems, transportation-related systems, space-based imaging systems and so forth. Operation of the image sensor system generally involves the capture of an image or frame through the exposure of IPs to light, the conversion of stored charge as a result of the exposure into image data, and the outputting of the image data to a storage medium.

[0044] The image sensor region 125 includes an IP array 127 including N-rows (indexed from 0 to N-1) and M-columns (indexed from 0 to M-1). The physical signaling interface 134 is configured to receive commands and configuration information from a host IC (e.g., a general-purpose or special-purpose processor, application-specific integrated circuit (ASIC) or any other control component configured to control the image sensor IC), and is configured to provide the received commands and configuration information to the control logic 132. The physical signaling interface is also configured to receive image data from the read circuit array 130 and to output received image data to the host IC.

[0045] The control logic 132 is configured to receive commands and configuration information from the physical signaling interface 134, and is configured to transmit signals configured to manipulate the operations and functionality of the image sensor system 120. For example, in response to receiving a command to capture an image or frame, the control logic may output a series of exposure signals (configured to cause IPs to reset) and sample signals (configured to cause the read circuits in the read circuit array 130 to sample the pixel signals from the IPs in the IP array 127), enabling the capture of the image or frame by the image sensor system. Similarly, in response to receiving a command to initialize or reset the image sensor system, the control logic may output reset signals configured to reset each IP in the IP array, causing each IP to disregard any accumulated charge. The control signals produced by the control logic identify particular IPs within the IP array for sampling, may control the functionality of read circuits associated with IPs, or may control any other functionality associated with the image sensor system. The control logic is shown in Fig. 4 as external to the image sensor region 125, but as noted above, all or portions of the control logic may be implemented locally within the image sensor region.

[0046] The control logic 132 outputs control and reset signals for each IP in the image sensor region 125. As illustrated in the embodiment of Fig. 4, each IP in an image pixel IP[X][Y] receives a row-parallel Cntrl[X] signal (corresponding to a "row" select control signal for each IP) and a row- parallel Reset[X] signal from the control logic to reset the IPs, wherein "X" and "Y" refer to the coordinates of the IP within the image sensor region.

Although the control signal and reset signals received at any given IP are each only 1 bit as indexed in the embodiment of Fig. 4, it is to be appreciated that such an indexing is done for the purposes of simplicity only, and that these signals may in practice be any width or dimension.

[0047] The read circuit array 130 includes M read circuits, each configured to receive pixel signals from a column of IPs in the IP array 127. It should be noted that in other embodiments, the read circuit array can include multiple read circuits configured to receive pixel signals from each IP column, as is discussed in figures 5a, 5b, and 5c. A pixel signal bus couples the IPs in each IP column in the IP array to the read circuit associated with the IP column within the read circuit array. Each IP is configured to output a pixel signal produced by the IP to the pixel signal bus, and each read circuit is configured to sample the pixel signals from the IPs in the IP column associated with the read circuit. For example, read circuit 0 is configured to sample pixel signals from pixel signal bus 0, and so forth. Each read circuit in the read circuit array can sample pixel signals iteratively from IPs in the IP column associated with the read circuit (for instance, by sampling pixel signals from successive IPs in order over multiple passes), or can sample pixel signals according to a pre-determined nonsequential order. In one embodiment, read circuits can sample multiple pixel signals simultaneously. Although not illustrated in the embodiments of Fig. 3 and Fig. 4, the read circuits can additionally include memories configured to store accumulated digital values prior to outputting the accumulated values as image data.

[0048] A conditional reset bus couples the IPs in each IP column in the IP array 127 to the read circuit associated with each IP column. After sampling a pixel signal from an IP in an IP column, the read circuit associated with the IP column produces a conditional reset signal if the sampled pixel signal exceeds a sampling threshold. For example, if an IP in an IP column outputs a pixel signal to a read circuit associated with the IP column via the pixel signal bus coupling the IP to the read circuit, and if the read circuit determines that the pixel signal exceeds a sampling threshold, the read circuit outputs a conditional reset signal to the IP via the conditional reset bus coupling the read circuit to the IP and the IP resets the charge stored at the IP. As described above, the pixel signal bus and the conditional reset bus can be implemented in a shared bus with Cntrl[X] enabling pixel signals to be output from row X to the shared bus and Reset[X] enabling conditional reset for pixels in row X from the shared bus, though such embodiments are not described further herein for the purposes of simplicity.

[0049] The control logic 132 produces read control signals for the read circuits in the read circuit array 130. The read control signals can control the sampling of pixel signals from the IPs in the IP array 127 by the read circuits, the conversion of sampled pixel signals into digital values, the accumulation of the digital values, the outputting of the accumulated digital values, and the resetting of the adders. The read control signals can include a threshold signal, a sample signal, a compare signal, a residue signal, a readout signal, and a reset/add signal for each read circuit in the read circuit array as described in Fig. 3.

[0050] The control logic 132 is configured to produce read control signals for the read circuit array 130 to enable the capture of an image over an image capture period. Prior to the image capture period or at the first use of a particular IP memory location for an image capture period, the control logic can produce a reset to cause the accumulator of each read circuit 110 to reset the IP memory location. At the beginning of the image capture period, the control logic can produce a threshold signal for each of the read circuits; as discussed above, the threshold signal is used by each read circuit to determine a threshold to which pixel signals are compared for the purposes of conditionally resetting IPs associated with the pixel signals and accumulating digital values associated with the pixel signals. During the image capture period, the control logic can produce a series of sample signals configured to enable the read circuits to sample pixel signals from IPs associated with the read circuits. In one embodiment, the control logic produces sample signals according to one or more sampling policies. Sampling policies are described in greater detail below. At the end of the image capture period, the controlled logic produces a residue signal configured to enable each read circuit to accumulate a digital value representative of a pixel signal regardless of whether the pixel signal exceeds a sampling threshold. After the image capture period, the control logic produces a readout signal configured to enable each read circuit to output the accumulated digital values representative of sampled pixel signals that exceed an associated sampling threshold as image data. The control logic may also produce a reset signal after each image capture period to reset the accumulated digital values within each read circuit.

[0051] The control logic may also be configured to produce pause and resume signals configured to cause the IPs and the read circuits to pause and resume an image capture, and to produce any other signal necessary to control the functionality of the IPs and read circuits in the read circuit array. For each read circuit, the image data output by the read circuit is a digital representation of the light captured by each IP in an IP column associated with the read circuit. The image data is received by the physical signaling interface for subsequent output to a host IC.

[0052] Fig. 5 illustrates an example image sensor system architecture with read circuit arrays located peripherally to an IP array, according to one embodiment. In the architecture of Fig. 5, six read circuit arrays (140a, 140b, 140c, 140d, 140e, and 140f) are located around an image sensor region 145 including an IP array. Unlike the embodiment of Fig. 4, in which one read circuit array 130 is located to one side of the image sensor region 125, the read circuit arrays 140 of Fig. 5 are located on all sides of the image sensor region 145. The read circuit arrays can be located within an IC also containing the image sensor region, or can be located on one or more separate ICs. For example, each read circuit array could be located on the periphery of an image sensor IC, or could be located in dedicated read circuit array ICs located adjacent to the image sensor IC.

[0053] In the previous embodiment of Fig. 4, each read circuit in the read circuit array 130 is coupled to an IP column in the IP array 127. In the embodiment of Fig. 5, each read circuit array 140x is coupled to a set of six IPs from partial rows and partial columns of the image sensor region 145. For example, read circuit array 140a is coupled to IP1, IP2, IP3, IP7, IP8, and IP9. Each read circuit array 140x includes one or more read circuits. In one embodiment, each read circuit array includes 6 read circuits, with each read circuit in a read circuit array coupled to one IP. In such an embodiment, each read circuit samples only the IP to which it is coupled. More typically, each read circuit will be shared by a block of IPs comprising a large number of rows and one or more columns. Although control logic is not illustrated in the embodiment of Fig. 5, each read circuit array can be coupled to universal control logic, or each may be coupled to dedicated control logic. Further, although a physical signaling interface is not illustrated in the embodiment of Fig. 5, each read circuit array may output image data via a common bus to a common physical signaling interface, or may output image data via a dedicated bus to a dedicated physical signaling interface coupled to each read circuit array.

[0054] Fig. 6a illustrates a top view of a pixel array IC in an example two-layer image sensor system architecture, according to one embodiment. The pixel array IC of Fig. 6a includes peripheral circuitry 162 surrounding an IP array. The IP array includes row control circuitry 164 and four row groups of IPs (IP Row Groups 0 through 3). Each IP row group is the width of the array and includes one-fourth of the rows in the array, and the row control circuitry provides control and reset signals needed for operation of the IPs (for instance, signals configured to cause the IPs to be enabled for reset and selected for readout, and any other signals discussed herein).

[0055] Fig. 6b illustrates a top view of a preprocessor IC in an example two-layer image sensor system architecture, according to one embodiment. The preprocessor IC of Fig. 6b includes peripheral circuitry 172 surrounding a read circuit array. The read circuit array includes a physical signaling interface 175 (which may alternately be on pixel array IC 160), read control circuitry 176, four read circuit arrays (read circuit array 0 through 3), and accompanying memory groups 0A/B, 1A/B, 2A/B, and 3A/B. Each read circuit array includes one or more read circuits (including an ADC, adder, and reset logic for each IP column) connected to corresponding rows in an associated memory group. When a particular IP row is selected in an IP row group of the pixel array IC, a corresponding row in the corresponding memory group is selected on the preprocessor IC.

[0056] Fig. 6c illustrates a cross section of the pixel array IC of Fig. 6a and the preprocessor IC of Fig. 6b in an example two-layer image sensor system architecture, according to one embodiment. In the embodiment of Fig. 6c, the pixel array IC 160 is located above the preprocessor IC 170 such that the bottom surface of the pixel array IC is coupled to the top surface of the preprocessor IC. A microlens array 180 and a color filter array 182 are located above the pixel array IC. The pixel array IC and the processor IC are coupled via pixel array IC wiring 184 and preprocessor IC wiring 186. By locating the pixel array IC above the preprocessor IC, the amount of surface area in the image sensor system capable of capturing light is increased. For instance, in a single-layer IC architecture including an IP array and one or more read circuit arrays, the portion of the single-layer IC including the one or more read circuit arrays are incapable of capturing light; such an embodiment reduces the amount of light incident upon the single-layer IC that is captured for a given circuit size, or for the same light capture requires a larger chip to allow the read circuits and memory to be arranged in the periphery. The top-layer of the embodiment of Fig. 6c, in contrast, does not include read circuit arrays, increasing the amount of the top-layer including the IP array, and accordingly increasing the amount of light incident upon the top layer that is captured. Light incident upon the top-layer passes through the microlens array and the color filter array, is captured by the IPs in the IP array, and signals representative of the captured light are sampled by the read circuit arrays via the pixel array IC wiring and the preprocessor IC wiring.

[0057] Fig. 7 illustrates the operation of an image sensor read circuit, such as the read circuit of Fig. 3, according to one embodiment. In the example embodiment of Fig. 7, an image is captured over the course of 16 sampling intervals. The ADC of the example embodiment of Fig. 7 converts pixel signals to 5-bit digital values, and the accumulator accumulates 5 -bit digital values into a 9-bit digital value during the image capture period. Further, in the embodiment of Fig. 7, the ADC converts received pixel signals into digital values representing the pixel signals such that each additional photon detected by an IP results in an increase in the digital value by one. For example, if an IP detects 5 photons after being reset, the pixel signal produced by the IP will be converted by the ADC into the value "00101". It should be emphasized that in other embodiments, the ADC converts received pixel signals into digital values representing the pixel signals such that multiple additional photons detected by an IP results in an increase in the digital value by one. In the

embodiment of Fig. 7, pixel signals are analog voltages, and thus aren't shown in Fig. 7 for the purposes of simplicity.

[0058] At the beginning of the image capture period (sampling interval 0), a control signal is received configured to configure an IP of the read circuit to be reset and begin exposure. In the embodiment of Fig. 7, the "begin exposure" control signal also resets the value stored at the memory element corresponding to the IP to zero. In addition, a threshold signal is received to set the sampling threshold for the read circuit at a pixel signal equivalent to 20 photons.

[0059] During the first sampling interval, 4 photons are detected by the IP. The IP then produces a pixel signal representing the charge collected by a photosensitive element within the IP equivalent in response to detecting the 4 photons, and the ADC converts this pixel signal to the digital value "00100". Since the 4 detected photons do not trigger the sampling interval of 20 photons ("10100"), the accumulator does not accumulate the digital value "00100", and the charge stored by the IP is not dissipated (the IP is not reset). Note that the column "Photons (det. - accum.)" indicates first the number of photons detected by the IP during a particular sampling interval and second the number of accumulated photons since the last conditional reset of the IP.

[0060] During sampling interval 2, 7 additional photons are detected by the IP. The charge stored by the IP increases from the charge produced in response to detecting 4 photons during sampling interval 1 to a charge produced in response to detecting 11 accumulated photons (4 photons during sampling interval 1 and 7 photons during sampling interval 2). The pixel signal produced by the IP in response to the stored charge is converted to the digital value "01011". Since the total 11 photons do not trigger the sampling threshold of 20 photons, the accumulator does not accumulate the digital value "01011", and the IP is not reset. Similarly, during sampling interval 3, 2 additional photons are detected by the IP, and the charge stored by the IP increases to a charge produced in response to detecting 13 accumulated photons (4 photons during sampling interval 1, 7 during sampling interval 2, and 2 during sampling interval 3). The pixel signal produced by the IP in response to this increased stored charge is converted to the digital value "01101". Since the accumulated 13 photons do not trigger the sampling threshold of 20 photons, the accumulator does not accumulate the digital value "01101", and the IP is not reset.

[0061] During sampling interval 4, 11 additional photons are detected by the IP. The charge stored by the IP increases to a charge equivalent to detecting 24 accumulated photons (4 during sampling interval 1, 7 during sampling interval 2, 2 during sampling interval 3, and 11 during sampling interval 4). The pixel signal produced by the IP in response to the stored charge is converted to the digital value "1 1000". Since the accumulated 24 photons exceeds the sampling threshold of 20 photons, the adder accumulates the digital value "11000" into the memory element for the IP, and the IP is reset.

[0062] The 14 photons detected during sampling interval 5 do not exceed the sampling interval of 20, the digital value produced by the ADC, "01110" is not accumulated and the IP is not reset. The 8 photons detected during sampling interval 6 results in an accumulated detection of 22 photons by the IP (14 photons during sampling interval 5, and 8 during sampling interval 6), and the adder accumulates the digital value "10110" (resulting in a total accumulated value of "000101110" into the memory element), and the IP is reset.

[0063] This process is repeated for each of the 16 sampling intervals. The digital values produced by the ADC during sampling intervals 10, 14, and 15 are all accumulated in response to the sampling threshold of 20 photons being exceeded by the number of accumulated photons detected by the IP. Accordingly, the IPs are reset for the sampling intervals following these intervals (sampling interval 11, 15, and 16). During sampling interval 16, 19 photons are detected by the IP, which does not exceed the sampling threshold of 20 photons. In addition, during sampling interval 16, a residue signal is received configured to instruct the accumulator to accumulate the digital value produced by the ADC (the residue value 190, "1001 1"). Accordingly, the adder accumulates the value "10011" to the maintained accumulation value "001111011" in the memory element to produce the image data 195, "010001110". Finally, a reset signal is received during sampling interval 16, which enables the read circuit to output the image data and which resets the values output by the ADC and stored at the accumulator to zero subsequent to outputting the image data.

[0064] Fig. 8 illustrates pixel information flow in an image capture system, according to one embodiment. During the course of an image capture period, an IP 200 detects photons and outputs pixel signals 202 to the read circuit. In response, the read circuit 204 converts the received pixel signals to digital values representative of the receive pixel signals, and for each digital value associated with a pixel signal that exceeds a sampling threshold, accumulates the digital value and resets the IP. After the image capture period, the accumulated digital values are output as image data 206.

[0065] A post processing module 208 receives the image data 206 and performs one or more processing operations on the image data to produce the processed data 210. In one embodiment, a response function can be used to transform the image data 206 according to a desired response. For example, the image data can be transformed with a linear function or a logarithmic function based on the intensity of the light detected by the IP. The processed data is then stored in memory 212 for subsequent retrieval and processing. The IP 200, the read circuit 204, the post processing module, and the memory can be located within an IC, or can be located within separate coupled ICs.

[0066] Fig. 9 illustrates various temporal sampling policies for use by an image sensor read circuit, such as the read circuit of Fig. 3, according to one embodiment. In the embodiment of Fig. 9, an image is captured over an image capture period 220 equivalent to 16 time units. For each of the three illustrated sampling policies, an "x" indicates the sampling of a given IP by a read circuit.

[0067] In sampling policy 1, the read circuit samples the IP after each of the 16 time units. In sampling policy 2, the read circuit samples the IP after every 4 time units. As the read circuit in sampling policy 2 samples the IP less frequently than the read circuit in sampling policy 1 , the IP in sampling policy 2 is more likely to saturate than the IP in sampling policy 1. However, the resources (processing, bandwidth, and power) required to implement sampling policy 2 (4 total samples) may be lower than the resources required to implement sampling policy 1 (16 total samples), since the read circuit in sampling policy 2 samples the IP only 25% as often as the read circuit in sampling policy 1.

[0068] In sampling policy 3, the read circuit samples the IP after time units 1, 2, 4, 8, and 16. The exponential spacing of the samplings of sampling policy 3 provide short sample intervals (for instance, the sample interval between time unit 0 and time unit 1) and long sample intervals (for instance, the sample interval between time unit 8 and time unit 16). Allowing for both short and long sampling intervals preserves the dynamic range of sampling policy 1 with nearly as few samplings as sampling policy 2 (5 samplings for sampling policy 3 vs. 4 samplings for sampling policy 2). Other sampling policies not illustrated in Fig. 9 may also be implemented by read circuits in the image sensor systems described herein.

Depending on the overall length of an exposure interval or other scene- or user-dependent factors, different sampling policies can be selected to meet desired power, SNR, dynamic range, or other performance parameters.

Additional Considerations

[0069] It should be noted that the various circuits disclosed herein can be described using computer aided design tools and expressed (or represented), as data and/or instructions embodied in various computer-readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Formats of files and other objects in which such circuit expressions can be implemented include, but are not limited to, formats supporting behavioral languages such as C, Verilog, and VHDL, formats supporting register level description languages like RTL, and formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES and any other suitable formats and languages. Computer-readable media in which such formatted data and/or instructions can be embodied include, but are not limited to, computer storage media in various forms (e.g., optical, magnetic or semiconductor storage media, whether

independently distributed in that manner, or stored "in situ" in an operating system).

[0070] When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits can be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image can thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.

[0071] In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the disclosed embodiments. In some instances, the terminology and symbols may imply specific details that are not required to practice those embodiments. For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, component circuits or devices and the like can be different from those described above in alternative embodiments. Additionally, links or other interconnection between integrated circuit devices or internal circuit elements or blocks may be shown as buses or as single signal lines. Each of the buses can alternatively be a single signal line, and each of the single signal lines can alternatively be buses. Signals and signaling links, however shown or described, can be single-ended or differential. A signal driving circuit is said to "output" a signal to a signal receiving circuit when the signal driving circuit asserts (or de-asserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. The term "coupled" is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. Integrated circuit device "programming" can include, for example and without limitation, loading a control value into a register or other storage circuit within the integrated circuit device in response to a host instruction (and thus controlling an operational aspect of the device and/or establishing a device configuration) or through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and/or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device. The term "light" as used to apply to radiation is not limited to visible light, and when used to describe sensor function is intended to apply to the wavelength band or bands to which a particular pixel construction (including any corresponding filters) is sensitive. The terms "exemplary" and "embodiment" are used to express an example, not a preference or requirement. Also, the terms "may" and "can" are used interchangeably to denote optional (permissible) subject matter. The absence of either term should not be construed as meaning that a given feature or technique is required. [0072] The section headings in the above detailed description have been provided for convenience of reference only and in no way define, limit, construe or describe the scope or extent of the corresponding sections or any of the embodiments presented herein. Also, various modifications and changes can be made to the embodiments presented herein without departing from the broader spirit and scope of the disclosure. For example, features or aspects of any of the embodiments can be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof.

Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.