FIELD OF THE INVENTION

The following generally relates to a computed tomography (CT) imaging system radiation sensitive detector with improved spatial accuracy.

BACKGROUND OF THE INVENTION

A CT scanner includes an x-ray tube mounted on a rotatable gantry that rotates around an examination region about a longitudinal or z-axis. A detector array subtends an angular arc opposite the examination region from the x-ray tube. The detector array detects radiation that traverses the examination region and a subject or object therein and generates a signal indicative thereof. The detector array generally includes a scintillator array optically coupled to a photosensor array, which is electrically coupled to processing electronics. The scintillator array generates light indicative of radiation impinging thereon, the photosensor array generates an electrical signal indicative of the light, and the processing electronics includes an analog-to-digital (AID) converter that generates digital data indicative of the detected radiation based on the electrical signal. The digital data is processed to generate a signal, which is reconstructed to generate volumetric image data and one or more images therefrom.

A CT scanner has utilized a current to frequency (I/F) converter as the AID converter. However, this converter is limited in spatial accuracy in low signal, low-dose imaging procedures. By way of example, FIGURE 8 shows a diagram illustrating output pulses ("OP") of the I/F converter as a function of integration period ("IP"). In this diagram, Ti represents the beginning of an integration period. First, second, . . . , L pulses are generated at T ₂ , T ₃ , . . . T _L . T _M represents the end of the integration period and the beginning of a next integration period. In this example, a next pulse is generated at T _N , which occurs in the next integration period. The region 802 represents charge of the first integration period that overlaps the next integration period. The data has been re-aligned to compensate for this, which improves signal to noise, but it also creates skewing of the data in time, which reduces spatial accuracy. Unfortunately, approaches to overcome the spatial skewing have required an increase in circuitry area, cost and power requirements. SUMMARY OF THE INVENTION

Aspects of the present application address the above-referenced matters and others.

According to one aspect, a detector array of an imaging system includes a radiation sensitive detector configured to detect radiation and generates a signal indicative thereof and electronics in electrical communication with the radiation sensitive detector. The electronics include a current-to-frequency converter configured to convert the signal into a pulse train having a frequency indicative of a charge collected during an integration period. The electronics further include a residual charge collection circuit electrically coupled to current-to-frequency converter. The residual charge collection circuit is configured to store charge collected by the integrator for an end portion of the integration period that does not result in a pulse of the pulse train.

In another aspect, a method receiving a first signal indicating an integration period started and generating, with a current to frequency converter, a pulse train with a pulse frequency indicative of input charge during the integration period. The method further includes receiving a second signal indicating the integration period ended. The method further includes storing, for the integration period, a residual charge from a last pulse of the pulse train to an end of the integration period.

In another aspect, an imaging system includes a radiation source configured to emit radiation and a detector array configured to detect emitted radiation and generate a signal indicative thereof. The detector array includes a current-to-frequency converter configured to convert the signal into a pulse train having a frequency indicative of a charge collected during an integration period. The detector array further includes a residual charge collection circuit electrically coupled to current-to-frequency converter. The residual charge collection circuit is configured to store charge collected by the current-to- frequency converter for the integration period from a last pulse generated by the current-to- frequency converter to an end of the integration period.

Still further aspects of the present invention will be appreciated to those of ordinary skill in the art upon reading and understand the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

The invention may take form in various components and arrangements of components, and in various steps and arrangements of steps. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.

FIGURE 1 schematically illustrates an example imaging system with a detector array with a plurality of detector modules, each detector module including a plurality of detector tiles.

FIGURE 2 schematically illustrates an example of a detector tile having an x-ray photon detection portion and processing electronics.

FIGURE 3 schematically illustrates an example of the electronics, including an VF converter and a residual charge collection circuit.

FIGURE 4 schematically illustrates an example bank of capacitors configured to provide an integrating capacitor, a reset capacitor and a residual charge capacitor.

FIGURE 5 schematically illustrates another example of the bank of capacitors configured to provide the integrating capacitor, the reset capacitor and the residual charge capacitor.

FIGURE 6 schematically illustrates an example approach for connecting capacitors of the banks of FIGURES 4 and 5 to provide the integrating capacitor, the reset capacitor and the residual charge capacitor.

FIGURE 7 illustrates an example method in accordance with an embodiment described herein.

FIGURE 8 illustrates an example diagram showing pulse output of a current to frequency converter as a function of integration period.

DETAILED DESCRIPTION OF EMBODIMENTS FIGURE 1 illustrates an imaging system 100 such as a computed tomography (CT) scanner. The imaging system 100 includes a generally stationary gantry 102 and a rotating gantry 104. The rotating gantry 104 is rotatably supported by the stationary gantry 102 and rotates around an examination region 106 about a longitudinal or z-axis. A radiation source 108 such as an x-ray tube is supported by the rotating gantry 104 and emits radiation that traverses the examination region 106.

A radiation sensitive detector array 112 subtends an angular arc opposite the radiation sources 108 across the examination region 106 and detects radiation traversing the examination region 106. In the illustrated embodiment, the radiation sensitive detector array 112 includes a plurality of detector modules 114, each extending along the z-axis direction. In one instance, the detector array 112 is substantially similar to and/or is based on the detector array described in US patent 6,510, 195B1, filed July 18, 2001, and entitled "Solid State X-Radiation Detector Modules and Mosaics thereof, and an Imaging Method and Apparatus Employing the Same," which is incorporated herein by reference in its entirety. Other arrangements are also contemplated herein.

A detector module 114 includes a plurality of detector tiles 116 extending along the z-axis direction. Briefly turning to FIGURE 2, a cross-sectional view of a detector tile 116 along line A-A of FIGURE 1 is illustrated. The tile 116 includes a scintillator array 202 optically coupled to an array 204 of pixels 206, which is electrically coupled to electronics 208 through a substrate 210. Electrical conductors 212 (e.g., pins, etc.) are for power, I/O, etc. In a variation, the substrate 210 is omitted. Examples are described in "A New 2D-Tiled Detector for Multislice CT," Luhta et al., Medical Imaging 2006: Physics of Medical Imaging, Vol. 6142, pp. 275-286 (2006), and US 8,710,448 B2, filed on March 8, 2007, and entitled "Radiation Detector Array," which is incorporated in its entirety by reference herein.

As described in further detail below, existing components of the electronics 208 are re-configured through additional switches to implement a self-contained residual charge switched-capacitor based converter that provides an accurate measurement of residual charge 802 (FIGURE 8), which can be added to the charge indicated by the output of the I/F converter to determine a total charge for an integration period. This approach mitigates an increase in the area, cost and power requirements of the electronics 208, while allowing data collection to end coincident with the end of each integration period, eliminating spatial skewing associated with re-aligning pulses overlapping subsequent integration periods. This approach is well suited for x-ray tubes with fast KV (grid switching) and/or other attributes that magnify such spatial skewing. Returning to FIGURE 1, a reconstructor 1 18 reconstructs the signal from the detector array 1 12 and generates volumetric image data indicative thereof. The volumetric image data can be further processed to generate one or more images of the scanned portion of the subject or object. A computing system serves as an operator console 120. Software resident on the console 120 allows the operator to control the operation of the system 100. A patient support 122, such as a couch, supports an object or subject such as a human patient in the examination region 106.

FIGURE 3 schematically illustrates an example of at least a sub-portion the electronics 208 for the pixel 206. An analog-to-digital (AID) converter 300 includes an integrator 302 (an amplifier 304 and an integrating capacitor (Ci _nt ) 306) and a comparator 310. The integrator 302 is configured to integrate charge (Ioio _d e _j n) from the pixel 206 (and a bias current, if employed) during each integration period. The comparator 310 compares an output of the amplifier 304 with a predetermined threshold value (V _th ) and generates a signal indicative thereof such as a pulse when the output rises above V _th .

A data collection switch 312 disconnects the AID converter 300 to and from the pixel 206 during the reset of the integrating capacitor (Ci _nt ) 306. A reset circuit 314 (a reset capacitor (C _rst ) 316 and reset switches 318 and 320) is configured to reset the integrator 302 during each integration period in response to the generation of a pulse by the comparator 310. A residual charge collection circuit 322 (a residual charge capacitor (C _res ) 324 and residual charge switches 334) is configured to store charge collected by the integrating capacitor 306 from a last pulse generated in an integration period to the end of the integration period. Switches 334 are briefly closed and once a ratio of the residual charge is transferred to the residual charge capacitor (C _res ) 324, the switches 334 are opened and then the integrator capacitor (Cin _t ) 306 is reset by connecting it to the reset Capacitor (C _rst ) 316 via operation of reset switches 318 and 320 and input disconnect switch 312, to begin a next integration period.

In the illustrated example, the AID converter 300 is implemented as a current-to-frequency (I/F) converter in that it generates a pulse train with a pulse frequency indicative of the input charge (Ioio _d e _j n). An example of an I/F converter is further described in US patent 6,671,345 B2, filed November 7, 2001, and entitled "Data

Acquisition for Computed Tomography," which is incorporated herein by reference in its entirety. Other suitable electronics are described in US patent 4,052,620, filed November 28, 1975, and entitled "Data Acquisition for Computed Tomography," which is incorporated herein by reference in its entirety.

Logic 330 controls the data collection switch 312 and the reset switches 318 and 320 based on the output of the comparator 310, a clock ("CLK") and the output of a timing circuit 332, which determines timing base on an encoder pulse indicating the end/beginning of an integration period. In general, the clocking of the switched capacitor converter 338 at a higher rate than the channel samples allows for converting the residual charge balance quickly at the end of an integration period such that residual charge conversion ends within the spatial sampling period

The charge value transferred to the residual capacitor (C _res ) 324 is connected to a switched capacitor converter 338 via switches 336 and converted at a very high conversion clock rate. The switched capacitor converter 338 can be implemented with its own comparator and bank of capacitors (as shown) or can be clocked fast enough (e.g., 10- 30 times higher) to utilize existing circuitry in the channel like the comparator 310 for its function. If so used, additional switches would configure the comparator 310 to perform conversion under the control of the logic 330, which would be completed during the same time of a reset pulse in normal operation. It can also be appreciated the residual capacitor (Cres) 324 can be eliminated and residual charge on the integrating capacitor (Cint) 306 can be measured directly using the existing comparator 310 if the amount of charge lost from the input being disconnected is small due to clocking the comparator 310 very quickly.

In this example, the logic 330 is also configured to count the number of pulses from the comparator 310 during an integration period and determines a time from a first pulse of the integration period to the last pulse of the integration period. From this data, the logic 330 generates a frequency signal by dividing the number of pulses by the time between the pulses, which is indicative of collected charge. This frequency data is combined with the residual charge value stored by the residual charge collection circuit 322. The logic 330 also issues a reset signal coincident with the end of the integration period to ensure the charge on the integration capacitor Cint 306 is reset to the same value as if a complete pulse had been measured. Since the voltage on the reset capacitor C _rst 316 is selectable from an existing settable voltage reference, the threshold voltage of the switched capacitor converter 338 is likewise settable without additional circuitry. The logic 330 processes the result to determine an attenuation value, which is output in a signal, e.g., in a 16-bit word.

FIGURES 4 and 5 schematically illustrate a bank 402 of capacitors 404 configured to provide C _in t 306 and C _rst 316 and C _res 324. In FIGURE 4, different sub-sets of different capacitors 404 are electrically connected in parallel to respectively provide Ci _nt 306, C _rst 316 and C _res 324. In FIGURE 4, all of the capacitors 404 of the bank 402 are used. FIGURE 5 shows a variation in which not all of the capacitors 404 of the bank 402 are needed to provide Cint 306 and C _rst 316 and C _res 324. Other combinations of capacitors 404 for providing C _int 306 and C _rst 316 and C _res 324 are also contemplated herein.

FIGURE 6 schematically shows how capacitors 404 can be connected together. In FIGURE 6, each of the capacitors 404 of the bank is associated with at least one switch 602. The switches 602 in the illustrated example are used to connect capacitors 404 of the bank 402 electrically in parallel to create Cint 306 and C _rst 316 and C _res 324 with particular capacitance values for Cint 306 and C _rst 316 and C _res 324. The switches 602 can be configured to select any connection to any bank of capacitance Ci _nt 306, C _rst 316 and

Where the bank 402 for C _in t 306 and C _rst 316 already includes enough unused capacitors 404 for also implementing C _res 324, only the switches 334, the timing circuit 332, control by the logic 330, and processing of the residual charge by the logic 330 are added to implement C _res 324. In another instance, where the bank 402 includes enough capacitors 404 for C _in t 306 and C _rst 316 but not for C _res 324, one or more capacitors are added to the bank 402 to implement also implement C _res 324.

The electronics 208 described herein can be implemented via CMOS and/or other fabrication process by adding the switches 334, re-configuring the capacitor bank 402, and adding the timing circuit 332.

FIGURE 7 illustrates an example method in accordance with an embodiment described herein.

At 702, a first signal indicating start of a first integration period is received.

At 704, a pulse train with a pulse frequency indicative of the input charge is generated by the current to frequency converter 300 for the integration period.

At 706, a second signal indicating end of the integration period is received. At 708, a residual charge collected by the current to frequency converter 300 for the end of the integration period is stored.

At 710, the pulse train and the residual charge are used to determine a total charge for the integration period.

At 712, the total charge is processed to determine an attenuation value.

At 714, the attenuation value is conveyed to the reconstructor 118.

At 716, attenuation values for multiple integration periods are reconstructed to generate volumetric image data.

The invention has been described herein with reference to the various embodiments. Modifications and alterations may occur to others upon reading the description herein. It is intended that the invention be construed as including all such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.