IMPEDANCE ADJUSTMENT METHOD AND SEMICONDUCTOR DEVICE - SONY SEMICONDUCTOR SOLUTIONS CORP

Title:

IMPEDANCE ADJUSTMENT METHOD AND SEMICONDUCTOR DEVICE

Document Type and Number:

WIPO Patent Application WO/2019/198434

Kind Code:

A1

Abstract:

A semiconductor device pertaining to an embodiment of the present disclosure is provided with: an output driver including a first variable resistance element; replica circuits, each including a second variable resistance element and having the same configuration as that of the output driver; first wiring connected to output ends of the replica circuits; second wiring electrically connected to a first external terminal; and a comparator for comparing the voltage of the first wiring with the voltage of the second wiring.

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Inventors:

HACHIYA SHOGO (JP)
MARUKO KENICHI (JP)
UCHINO KOKI (JP)
IMAMURA MAKOTO (JP)
IWAKI TAKAMICHI (JP)
ASAI NOBUYUKI (JP)

Application Number:

PCT/JP2019/011129

Publication Date:

October 17, 2019

Filing Date:

March 18, 2019

Export Citation:

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Assignee:

SONY SEMICONDUCTOR SOLUTIONS CORP (JP)

International Classes:

H03K19/0175; H03H7/38

Foreign References:

JP2009164718A

2009-07-23

Attorney, Agent or Firm:

TSUBASA PATENT PROFESSIONAL CORPORATION (JP)

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