DESCRIPTION Technical Field

The present invention relates generally to impedance reduction and/or impedance buffering within electrical circuits. More particularly, this invention relates to impedance reduction and/or buffering circuits for use within miniature hearing aid devices that are designed for high performance, low noise, and reduced size. Background Prior Art The general construction of hearing aids usually includes a microphone portion, an amplifica¬ tion portion, and a receiver portion. The micro¬ phone portion picks up sound waves in audible frequencies and creates an electronic signal repre- sentative of these sound waves. The amplification portion takes the electronic signal and amplifies the signal, and then sends the amplified signal to the receiver, portion. The receiver portion produces enhanced original sound waves that are easier to hear than the original sound waves. Thus, a hearing aid user benefits from the enhanced sound waves.

Although hearing aid users benefit from the increased ability to hear sounds that surround them, prior art hearing aids were problematic in that they were fairly large. In particular, when a hearing aid was worn by a user, either in front or behind the ear, the hearing aid was visible by an observer. Furthermore, even when the hearing aid was recessed and a tube extended from the hearing aid into a user's ear, the tube was still visible by an observ- er. Thus, a hearing aid user often would not want to wear a hearing aid at all, when the hearing aid or tube extending into the user's ear was visible by an observer.

Thus, there has been a goal in the industry to create a smaller and smaller hearing aid which would fit into an ear canal, yet perform at the same or higher levels of performance than the larger hearing aid devices. Smaller hearing aids require smaller transducers which, in the case of microphones, means less source capacitance. As a result, the front ends of the amplifier portion 3, must have very high resistances and very low input capacitances in order to match or buffer to the source impedance. It is well known that Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technology offers higher gain and lower capacitance per unit area than Junc¬ tion Field Effect Transistor (JFET) technology. Hearing aid microphones have traditionally used JFET front ends to achieve low noise. However, the push to smaller sizes makes the use of MOSFETs attrac¬ tive. Specifically, the prior art used enhancement mode MOSFETs, Complimentary MOS transistors (CMOS) , and/or other types of enhancement mode devices at the front end of the amplifier portion or after the microphone portion of these hearing aids. (For example, see Murphy et al . U.S. Patent No. 4,764,69- 0) . At the very least, this is done to reduce the overall size of the hearing aid device and to

additionally reduce power consumption when CMOS technology is used.

However, problems arise when enhancement mode devices are used at the front end of the amplifier portion of a hearing aid device. Specifically, when a voltage is applied to turn on (or enhance) an enhancement mode device, carriers from the source to the drain of the device are conducted along the surface wherein the surface is the physical separa- tion between the two dissimilar materials of silicon and silicon dioxide. As the carriers are conducted along the surface, trapping and releasing of carri¬ ers occur based on the vertical field between the gate and the channel, as is commonly known in the art. Therefore, there is always some component of electrical field pulling the carriers toward the surface, causing trapping and releasing at the surface. This trapping and releasing results in an approximately l/f noise; f being the frequency of the noise.

At higher frequencies, one gets lower relative noise. However, at lower frequencies, frequencies commonly requiring the assistance of a hearing aid device, a relatively large amount of noise is produced from the trapping and releasing due to the conduction of carriers in the conduction channel of the enhancement mode transistor. The commonly known method of reducing the previously mentioned noise incorporates making the size of the enhancement mode devices very large so that the noise is integrated out by the increased area of the transistors. However, making large devices within the circuitry is contrary to the basic goal of creating smaller hearing aid devices. Hence, when a signal is produced by a micro¬ phone, the impedance of the microphone must be matched or buffered to the transmission medium which receives the signal. Generally, as previously

mentioned, in the case of a hearing aid, the micro¬ phone portion impedance must be appropriately buffered to the amplifier portion impedance in order for efficient amplification to occur. Thus, it is an object of the present invention to provide a circuit to match the impedance of the microphone portion and the amplifier portion of a hearing aid. This object is accomplished while, at the same time, solving the noise, size, and other problems of the prior art. This invention, while solving these problems of the prior art, also main¬ tains the same or higher level of performance as the prior art . Summary of the Invention The present invention is an impedance matching, reduction, or buffer circuit that permits smooth signal flow from a first transmission medium to a second transmission medium. The impedance circuit includes a first node that is adapted for coupling to the first transmission medium. The first node receives a signal from the first transmission medium. The impedance circuit also includes a buried channel transistor that is coupled to the first node and is used for transforming the imped- ance imposed on the signal. The impedance circuit further includes a second node that is coupled to the buried channel transistor and is adapted for coupling to the second transmission medium. The second node is the point at which the signal is conveyed to the second transmission medium.

In one embodiment of the invention, the imped¬ ance circuit further includes a biasing portion that is coupled to the buried channel transistor, the first node, and the second node. The biasing portion comprises a configuration that is responsive to the buried channel transistor, and is responsive to the signal when the signal is in a transient state. The impedance circuit further includes a

resistor that is coupled to the biasing portion, and is coupled to the buried channel transistor. The resistor is used for creating a bias current for the buried channel transistor. In operation, when a voltage source is applied, to the buried channel transistor, instead of trap¬ ping and releasing occurring along the surface of the transistor, the conduction occurs beneath the surface. Since the conduction occurs beneath the surface, a significantly less amount of noise is created, and impedance matching can take place without noise significantly affecting the signal. In further operation, the buried channel transistor creates a high impedance at the first node, and creates a low impedance at the second node based on the buried channel transistor's inherent structure. Thus, the impedance is reduced and excessive noise is not produced while the other standards of perfor¬ mance are kept at a high level. For a better understanding of the invention, reference may be had to the following specification taken in conjunction with the following drawing. Furthermore, other features and advantages of the invention will be apparent from the following specification taken in conjunction with the follow¬ ing drawing. Brief Description of Drawings

FIG. 1 is a schematic drawing of one embodiment of the impedance circuit of the present invention; and,

FIG. 2 is a schematic diagram of another embodiment of the impedance circuit of the present invention. Detailed Description While this invention is susceptible of embodi¬ ments in many different forms, there is shown in the drawings and will herein be described in detail, a preferred embodiment of the invention with the

understanding that the present disclosure is to be considered as an exemplification of the principles of the invention and is not intended to limit the broad aspects of the invention to the embodiment illustrated.

FIG. 1 shows an impedance circuit for reduc¬ ing/buffering the impedance between a first trans¬ mission medium and a second medium. In a hearing aid, the first transmission medium can, at least, represent a microphone portion (not shown) and/or the medium of transmission which the microphone portion creates in operation. Further in a hearing aid, the second transmission medium can, at least, represent the amplifier portion (not shown) and/or the medium of transmission which the amplifier portion requires for satisfactory operation. When the impedance circuit is in use, VIN is the signal that is received from the first transmission medium of the hearing aid, and VOUT is the signal that is conveyed along to the second transmission medium.

FIG. 1 further shows a first transistor 20 that is used in conjunction with a second transistor 30 for biasing a third transistor 40. The first and second transistors 20, 30 together, generally, make up what can be referenced as a biasing portion 70. The biasing portion 70 can alternatively comprise devices that are used to bias transistors generally, as is well known. Such biasing devices can include very large resistors, typically in the giga-ohm range, or diodes. However, FIG. 1 includes one embodiment in which the first and second transistors 20, 30 are Bi-Polar-Junction Transistors (BJTs) . Although BJTs are used in FIG. 1, MOSFETs or other types of transistors can also be used to bias the third transistor 40, as is shown in FIG. 2 and described later within this specification. In summary, the requirement is to establish a DC bias point while maintaining very high input impedance.

Within the impedance circuit generally dis¬ closed in FIG. 1, the first transistor 20 includes one emitter terminal 22, one base terminal 26, and one collector terminal 24. In addition, the second transistor 30 includes one emitter terminal 32, one base terminal 36, and one collector terminal 34.

The third transistor or buried channel transis¬ tor 40 in FIG. 1 is a conventional device, such as a depletion mode n-channel transistor, which is fabricated so that a depletion region exists above the channel as can be achieved by one of ordinary skill in the art. This type of fabrication minimiz¬ es trapping and releasing at the surface. Thus, noise created through trapping and releasing does not occur at the surface when the third transistor is in operation.

The third transistor 40 can be an n-type deple¬ tion mode MOSFET. The third transistor 40 has a width equal to one hundred 100 microns and a length equal to three 3 microns. In one form of the impedance circuit in FIG. 1, the third transistor 40 includes at least one drain terminal 44, at least one backside terminal 48, at least one source termi¬ nal 42, and at least one gate terminal 46. The drain terminal 44 of the third transistor 40 is cou¬ pled to a voltage source 60. A first node (A) cou¬ ples the emitter terminal 22 of the first transistor 20 to the gate terminal 46 of the third transistor 40. The first node (A) also couples the emitter terminal 22 of the first transistor 20 and the gate terminal 46 of the third transistor to the first transmission medium. The first node (A) further couples the base terminal 36 to the emitter 22 of the first transistor 20 and the gate 46 of the third transistor 40.

In the embodiment in FIG. 1, a second node (B) couples the collector terminal 24 of the first tran¬ sistor 20 to the collector terminal 34 of the second

transistor 30. The second node (B) also couples the source terminal 42 and the backside terminal 48 of the third transistor 40 together. The second node (B) additionally couples the two respective collec- tor terminals 24, 34 of the first and second tran¬ sistors 20, 30 to the source and backside terminals 42, 48 of the third transistor 40. Furthermore, the second node (B) couples the two collector terminals 24, 34 of the first and second transistors 20, 30, and the source and backside terminals 42, 48 of the third transistor 40 to the second transmission medium.

The impedance circuit in FIG. 1 further in¬ cludes a resistor 50 which, in conjunction with the first and second transistors 20, 30, creates an appropriate bias current for the third transistor 40. The second node (B) couples a first end 52 of the resistor 50 to the respective second node (B) coupled terminals 24, 34, 42, and 48, and to the second transmission medium. The second end 54 of the resistor 50 is coupled to ground 14. The value of the resistor 50 can be 22K ohms in one embodiment of the invention.

As an alternative, resistor 50 can be replaced by a current source. Further, in the impedance circuit in FIG. 1, the base terminal 26 of the first transistor 20 is coupled to ground 14. In addition, first and second transistors 20 and 30 function as diodes to establish the DC bias of node A. It should be appreciated that each of the transistors may have more than one terminal of the same type.

Turning to FIG. 2, an additional embodiment of the impedance circuit is disclosed for reduc¬ ing/buffering the impedance between a first trans- mission medium and a second medium. All common elements between FIG. 1 and FIG. 2, which are num¬ bered, will be listed with a prime (') in FIG. 2. Again, in a hearing aid, the first transmission

medium can, at least, represent a microphone portion (not shown) and/or the medium of transmission which the microphone portion creates in operation. Further in a hearing aid, the second transmission medium can, at least, represent the amplifier portion (not shown) and/or the medium of transmis¬ sion which the amplifier portion requires for sat¬ isfactory operation. When the impedance circuit is in use, VIN' of FIG. 2 is the signal that is re- ceived from the first transmission medium of the hearing aid, and VOUT' of FIG. 2 is the signal that is conveyed along to the second transmission medium.

FIG. 2 further shows a first transistor 80 that is used in conjunction with a second transistor 90 for biasing a third transistor 40' . The first and second transistors 80, 90 together, generally, make up what can be referenced as a biasing portion 70' . The biasing portion 70' can alternatively comprise other devices for biasing the third transistor 40', as is well known. Such biasing devices can include very large resistors, typically in the giga-ohm range, or diodes. However, FIG. 2 includes one embodiment in which the first and second transistors 80, 90 are enhancement mode p-channel (PMOS) MO- SFETs. Although enhancement mode PMOS MOSFETs are used in FIG. 2, other types of MOSFETs, including enhancement mode n-channel (NMOS) MOSFETs, and depletion mode NMOS and PMOS MOSFETs, or other types of transistors, can also be used to bias the third transistor 40' . In summary, as explained above, the requirement is to establish a DC bias point while maintaining very high input impedance.

Within the impedance circuit generally dis¬ closed in FIG. 2, the first transistor 80 includes a source terminal 82, a drain terminal 84, a gate terminal 86, and a backside terminal 88. In addi¬ tion, the second transistor 90 includes a source

terminal 92, a drain terminal 94, a gate terminal 96, and a backside terminal 98.

The third transistor or buried channel transis¬ tor 40' in FIG. 2 is a conventional device, such as a depletion mode n-channel (NMOS) transistor, which is fabricated so that a depletion region exists above the channel as can be achieved by one of ordi¬ nary skill in the art. Again, this type of fabrica¬ tion minimizes trapping and releasing at the sur- face. Thus, noise created through trapping and re¬ leasing does not occur at the surface when the third transistor 40' is in operation.

The third transistor 40' in FIG. 2 can be an n- type depletion mode MOSFET. The third transistor 40' in FIG. 2 has a width equal to one hundred (100) microns and a length equal to 3.6 microns. In one form of the impedance circuit in FIG. 2, the third transistor 40' includes a source terminal 42', a drain terminal 44', a gate terminal 46', and a backside terminal 48' . The drain terminal 44' of the third transistor 40' is coupled to a voltage source 60' . A first node (A') couples the drain terminal 84 of the first transistor 80 to the gate terminal 46' of the third transistor 40' . The first node (A' ) also couples the drain terminal 84 of the first transistor 80 and the gate terminal 46' of the third transistor 40' to the first transmission medium. The first node (A') further couples the source terminal 92 of the second transistor 90 to the gate terminal 86 and drain terminal 84 of the first transistor 80 and the gate 46' of the third transistor 40' .

Additionally, in the embodiment in FIG. 2, a second node (B') couples the backside terminal 88 of the first transistor 80 to the backside terminal 98 of the second transistor 90. The second node (B' ) also couples the source terminal 42' and the back¬ side terminal 48' of the third transistor 40'

together. The second node (B' ) additionally couples the two respective backside terminals 88, 98 of the first and second transistors 80, 90 to the source and backside terminals 42', 48' of the third tran- sistor 40' . Furthermore, the second node (B' ) cou¬ ples the two backside terminals 88, 98 of the first and second transistors 80, 90, and the source and backside terminals 42', 48' of the third transistor 40' to the second transmission medium. Addition- ally, the gate terminal 96 and the drain terminal 94 of the second transistor 90 are connected to ground 14' . In a preferred form of the embodiment of FIG. 2, the first and second transistors 80, 90 preferably each have a width of four (4) microns and a length of three (3) microns.

The impedance circuit in FIG. 2 further in¬ cludes a resistor 50' which, in conjunction with the first and second transistors 80, 90, creates an appropriate bias current for the third transistor 40' . The second node (B' ) couples a first end 52' of the resistor 50' to the respective second node (B') coupled terminals 88, 98, 42', and 48', and to the second transmission medium. The second end 54' of the resistor 50' is coupled to ground 14. The value of the resistor 50' can be 22K ohms in this embodiment of the invention.

As an alternative, resistor 50' can be replaced by a current source. Furthermore, in the impedance circuit in FIG. 2, the source terminal 82 of the first transistor 80 is coupled to ground 14' . It should be appreciated that each of the transistors may have more than one terminal of the same type.

The embodiment in FIG. 2 is generally prefera¬ ble to the embodiment in FIG. 1 in the following re- spects. As described above, the biasing MOSFETs 80, 90 can be used to replace the NPN BJTs 20, 30, used to bias the gate 46' of the third transistor 40' . These biasing MOSFETs are also known as the biasing

portion 70', and are PMOS devices in the FIG. 2 em¬ bodiment .

When PMOS devices are used as the biasing portion 70' (MOSFETs) to replace the biasing portion 70 from FIG. 1 (BJTs) , the PMOS devices have been found to exhibit about 1/4th as much (i.e. 75% less) loading capacitance than the BJTs at the input terminal 10' of the impedance circuit, while main¬ taining the same loading resistance as the BJTs in biasing portion 70 from FIG.l. When used in the biasing portion 70, 70', both NPN (BJTs) and PMOS (MOSFETs) devices must have minimum physical size, in order to minimize their loading capacitance effects. The reduction in capacitance by use of PMOS devices comes directly from recognizing that, for the same device size, the loading capacitance of a device having a Silicon Dioxide dielectric (such as for a PMOS device) is l/4th the loading capaci¬ tance of a device having Silicon as its dielectric (such as for an NPN bipolar device) .

The reduced loading capacitance of the PMOS devices results in improved performance for this impedance circuit via higher buffer gain (due to reduced loading capacitance at the input) . It also results in a lower input referred noise while main¬ taining equal performance in all other areas. In general, these performance improvements can be ob¬ tained from using any MOS device including enhance¬ ment mode NMOS devices, depletion mode NMOS devices, enhancement mode PMOS devices, or depletion mode PMOS devices. The same types of devices or a combination of these devices could be used, so long as the devices used are biased properly. Nonethe¬ less, as shown in FIG. 2, the enhancement mode devices are preferred within the biasing portion 70', since no additional circuitry is needed to achieve the bias requirements, but depletion mode devices could be used if additional circuitry

(typically known as a charge pumps) were included to meet the bias requirements.

Both the embodiments from FIG. 1 and FIG. 2 are formed within a single substrate. In other words, the circuit elements and connections are fabricated into and onto a single substrate of semi-conductor material using well known fabrication concepts. There are numerous advantages of using a common or single substrate in the fabrication process, such as the ultimate smaller size of the circuit embodiment. Thus, it is usually most advantageous to use a single substrate to achieve the smallest feasible circuit, and the smallest feasible hearing aide.

It will be understood that the invention may be embodied in other specific forms without departing from the spirit or central characteristics thereof. Specificly, a single transistor can be used in combination with a diode or other circuit element (biasing elements) to make up the biasing portion 70, 70' . The present examples and embodiments, therefore, are to be considered in all respects as illustrative and not restrictive, and the invention is not to be limited to the details given herein.