Title:
IMPLEMENTATION OF AN INHIBIT DURING SOFT PROGRAMMING TO TIGHTEN AN ERASE VOLTAGE DISTRIBUTION
Document Type and Number:
WIPO Patent Application WO2003067597
Kind Code:
A3
Abstract:
Methods and apparatus for tightening an erased bit threshold voltage distribution are disclosed. According to one aspect of the present invention, a method for processing erased bits associated with an erased bit distribution which includes an over-erased bit which has a first value that is less than a first threshold voltage value and a bit that has a second value that substantially exceeds a second threshold voltage value includes inhibiting the fast bit. The method also includes applying a soft program pulse to the erased bits such that inhibiting the fast bit substantially prevents the second value from changing and applying the soft program pulse to the over-erased bit substantially causes the first value to increase. In one embodiment, applying the soft program pulse to the over-erased bit substantially causes the first value to increase to a value that is greater than or equal to the first threshold voltage value.
Inventors:
PAN FENG (US)
YU TAT-KWAN EDGAR (US)
YU TAT-KWAN EDGAR (US)
Application Number:
PCT/US2003/003710
Publication Date:
November 13, 2003
Filing Date:
February 06, 2003
Export Citation:
Assignee:
SANDISK CORP (US)
PAN FENG (US)
YU TAT-KWAN EDGAR (US)
PAN FENG (US)
YU TAT-KWAN EDGAR (US)
International Classes:
G11C16/34; (IPC1-7): G11C16/34
Foreign References:
| US5901090A | 1999-05-04 | |||
| US6483752B2 | 2002-11-19 | |||
| US6438037B1 | 2002-08-20 | |||
| US6252803B1 | 2001-06-26 | |||
| US6172909B1 | 2001-01-09 | |||
| US6122198A | 2000-09-19 |
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