| WO/2008/132401 | DEVICE FOR BALANCING THE POWER SUPPLIED BY POWER GENERATORS |
| JP3655277 | ELECTRIC MOTOR POWER SUPPLY MANAGEMENT SYSTEM |
| JP07213059 | SWITCHING REGULATOR |
WEISPFENNIG, Daryl (6920 Chaparral Lane, Chanhassen, MN, 55317, US)
FREDERICK, Bruce, A. (5635 Quinwood Lane, NorthPlymounth, MN, 55442, US)
WEISPFENNIG, Daryl (6920 Chaparral Lane, Chanhassen, MN, 55317, US)
CLAIMS
We claim:
1. An ORing element for use in a power supply, the ORing element comprising: a field effect transitor (FET) for electrical connection between an output of the power supply and a bus; a first bi-polar transistor, wherein an emitter of the first bi -polar transistor is electrically connected to a source of the FET, and wherein a collector of the first bi-polar transistor is electrically connected to a bias voltage and a gate of the FET; and a second bi-polar transistor, wherein an emitter of the second bi-polar transistor is electrically connected to a base of the second bi-polar transistor and a base of the first bi- polar transistor, and wherein a collector of the second bi-polar transistor is electrically connected to a drain of the FET.
2. The ORing element of claim 1 , wherein the emitter of the second bi-polar transistor is electrically connected to the bias voltage.
3. The ORing element of claim 1 , wherein at least one resistor is electrically connected between the collector of the first bi-polar transistor and the bias voltage.
4. The ORing element of claim 1 , wherein the first bi-polar transistor and the second bi-polar transistor are contained in a single package.
5. The ORing element of claim 4, wherein the single package is a 6-pin SOT-23 package.
6. A power supply comprising: a first power supply module; a common output bus; and an ORing element connected between the first power supply module and the common output bus, wherein the ORing element comprises: a field effect transistor (FET) electrically connected between the first power supply module and the common output bus; a first bi-polar transistor, wherein an emitter of the first bi-polar transistor is electrically connected to a source of the FET, and wherein a collector of the first bi-polar transistor is electrically connected to a bias voltage and a gate of the FET; and a second bi-polar transistor, wherein a emitter of the second bi-polar transistor is electrically connected to a base of the second bi-polar transistor and a base of the first bipolar transistor, and wherein a collector of the second bi-polar transistor is electrically connected to a drain of the FET.
7. The power supply of claim 6, wherein the emitter of the second bi-polar transistor is electrically connected to the bias voltage.
8. The power supply of claim 6, wherein the first bi-polar transistor and the second bi-polar transistor are contained in a single package.
9. The power supply of claim 8, wherein the single package is a 6-pin SOT-23 package.
10. The power supply of claim 6, further comprising a second power supply module; and a second ORing element connected between the second power supply module and the common output bus. |
IMPROVED CONTROLLER FOR ORING FIELD EFFECT TRANSISTOR
BACKGROUND Many electrical power supplies include multiple power supply modules joined in parallel by a common output bus. ORing circuit elements are often included between the power supply modules and the common output bus to prevent a failure of one power supply module from drawing down the common output bus and leading to a complete failure of the power supply. There are several common ORing element designs, each having certain disadvantages.
One common ORing element design involves placing a diode in series between a power supply module and the common output bus. When the output voltage of the power supply module is sufficiently greater than the voltage at the common output bus, the diode is forward-biased, allowing a forward current between the power supply module and the common output bus. If, however, the output of the power supply module drops below the output of the common output bus, then the diode will be reverse biased. When the diode is reverse biased, the power supply module is essentially prevented from drawing reverse current from the common output bus, thereby preventing a potential failure of the power supply. This and other diode-based ORing element, designs, however, suffer from several defects. Placing power-dissipating diodes between power supply modules and the common
output bus reduces the efficiency of the power supply, and generates excess heat. Also, the diodes must be chosen with a suitably fast recovery time to prevent reverse current.
Another known ORing element design involves placing a field effect transistor (FET) in series between the power supply module and the common output bus. A comparator circuit senses the difference between the output voltage of the power supply module and the voltage at the common bus, and turns the FET on or off accordingly. That is, when the voltage difference between the power supply module and the common output bus is greater than a threshold voltage, the FET is biased on, allowing a current between the power supply module and the common output bus. When the voltage difference is less than the threshold voltage, the FET is biased off, essentially preventing current between the power supply module and the common output bus.
Like diode-based ORing element designs, current FET-based ORing circuit element designs also present significant disadvantages. For example, the body diode of the FET may be forward biased by even relatively small positive voltages, allowing undesirable forward current. For this reason, many FET-based Oring circuits are designed with a negative threshold voltage. This causes its own problems, however. For example, ORing elements with a negative threshold voltage allow the FET to be turned on when the voltage at the power supply module is less than the voltage at the common output bus, which can result in potentially large and undesirable reverse currents.
BRIEF SUMMARY OF THE INVENTION
In one general aspect, the present invention is directed to an ORing element for use in a power supply. The ORing element may include a field effect transistor (FET), a first bi-
polar transistor and a second bi-polar transistor. The FET may be electrically connected between an output of the power supply module and a common output bus. The first bipolar transistor may have an emitter electrically connected to the source of the FET and a collector electrically connected to a gate of the FET as well as a bias voltage. The second bi-polar transistor may be diode connected, with its emitter electrically connected to its base. The emitter of the second bi-polar transistor may also be electrically connected to the base of the first bi-polar transistor. The collector of the second bi-polar transistor may be electrically connected to the drain of the FET. hi this way, the ORing circuit may selectively connect and isolate the power supply module from the common output bus. hi addition, multiple power supply modules and ORing elements may be combined to form a single power supply. BRIEF DESCRIPTION OF THE FIGURES
Embodiments of the present invention are described herein, by way of example, in conjunction with the following figures, wherein:
Figure 1 shows a schematic diagram of an ORing element according to various embodiments; and Figure 2 shows a block diagram of a power supply according to various embodiments.
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention are directed in general to ORing circuit elements and power supplies implementing the same. Figure 1 shows a schematic diagram of an exemplary ORing circuit element 100 according to various embodiments of the present invention. The circuit element 100 has an input node 108 for receiving a voltage provided by
a power supply module (not shown in Figure 1) and an output node 110 for providing a voltage to a common output bus (not shown in Figure 1). The circuit element 100 may also have a bias node 112 that receives a bias voltage. The circuit element 100 includes a field effect transistor (FET) 102, which may be electrically connected between the input node 108 and the output node 110. For example, as shown in Figure 1, the source terminal 152 of the FET 102 may be coupled to the input node 108 and the drain terminal 154 may be coupled to the output node 110. In this way, the current between the input node 108 and the output node 110 may be controlled by changing the state of the FET 102. For example, when the FET 102 is biased to an on condition, current may flow from the input node 108 to the output node 110. When the FET 102 is not biased to an on condition, the current may be limited and/or prevented altogether.
The ORing circuit element 100 may also include various components for selectively biasing the FET 102 including, for example, bi-polar transistors 104 and 106. The transistor 104 maybe connected such that its collector terminal 158 is coupled to the gate terminal 156 of the FET 102. The emitter 160 of transistor 104 is coupled to the source terminal 152 of the FET 102. The collector 158 of transistor 104 may also be coupled to the bias input 112 (e.g., via resistors 116 and 114). The transistor 106 may be connected such that its emitter 164 is shorted to its base 166. In this way, the transistor 106 may act as a two terminal device having characteristics similar to a diode (e.g., "diode connected")- The emitter 164 and base 166 of the transistor 106 may be coupled to the bias input 112 through resistor 118 and resistor 114. The emitter 164 and base 166 may also be coupled to the base 162 of the transistor 104. The collector 168 of the transistor 106 may be coupled to the drain 154 of the FET 102. In various embodiments, a zener or other suitable diode 120 may be electrically
connected between the bias node 112 and input 108 as shown. The diode 120 may safeguard the various transistors 102, 104, 106 of the circuit element 100 by preventing the voltage drop between the bias 112 and the input 108 from becoming too large.
In operation, the FET 102 is selectively biased based on the difference between the input voltage 108 and the output voltage 110. When the output 110 is higher than the input 108, then the FET 102 is held in its off state, isolating the output 110 from any power supply modules and/or other components electrically connected to the input 108. This may be desirable, as a fall in the input voltage 108 relative to the output voltage 110 may indicate a failure of the power supply module or other component electrically connected to the input 108. When the output 110 is lower than the input 108, then the FET 102 may be biased to an active or saturation mode, allowing current to flow between the input 108 and the output 110.
When the output 110 is sufficiently higher than the input 108, the body diode of the FET 102 will be reverse biased. The diode-connected transistor 106 may also be reverse biased due to the relatively high voltage at 110. The transistor 104 may be in its saturation mode, with its collector/base and emitter/base junctions both forward biased. This results in a relatively high collector current and relatively low collector voltage for the transistor 104, which keeps the voltage at the gate 156 of the FET 102 at a relatively low level, maintaining the FET 102 in an off state.
When the input 108 begins to rise relative to the output 110, the body diode of the FET 102 may become slightly forward biased. The diode-connected transistor 106 may also become forward-biased and may begin to draw base current from the transistor 104. This, in turn, may draw the transistor 104 out of saturation, reducing its collector current and increasing the collector voltage. As the collector voltage increases at the collector 158 of the
transistor 104, the voltage at the gate 156 of the FET 102 begins to rise, transitioning the FET 102 into an active mode when the gate threshold voltage is reached. In various embodiments, the gate threshold voltage is reached while the current at the output 110 is relatively low (e.g. , less than 100 mA) and low body diode bias voltages (e.g., less than 10 mV). As the current at output 110 increases further, the on resistance of the FET 102 may become dominant, causing the voltage drop across the FET 102 as well as the gate 156 voltage of the FET 102 to increase more quickly. Accordingly, the FET 102 may eventually transition to a saturation state.
The voltage drop between input 108 and output 110 (e.g., the voltage drop across the FET 102) at which the FET 102 is biased on may be referred to as the "threshold voltage" of the circuit 100. It will be appreciated that because the junctions of the transistors 104 and 106 are more closely matched than the junctions of a transistor and a diode, the circuit 100 may achieve more repeatable and lower threshold voltages. To potentially further enhance the repeatability of the circuit element 100, the transistors 104 and 106 may be contained in a single package, for example, a 6-pin SOT-23 package such as part number ZXTD09N50DE6 available from ZETEX. In this way, the transistors 104 and 106 may thermally track each other, further causing them to behave similarly.
It will be appreciated that when the current at the output 110 is relatively low, then the FET 102 will operate in its active state. In that state, the FET 102 behaves in a non-Ohmic manner (e.g., its effective impedance is higher than Ohm's law would suggest). As a result, small changes in current at the output 110 may tend to cause large changes in the voltage drop across the FET 102. Accordingly, even if the components of the ORing circuit element 100 would ordinarily result in a negative threshold voltage, reverse current is still limited.
Because small changes in output current bring about large changes in the voltage drop across the FET 102, if the current at the output 110 begins to turn negative, it will bring about a large change in the voltage drop across the FET. This may cause the transistors 104, 106 to draw the gate 156 of the FET 102 low and prevent substantial negative output current.
Figure 2 shows a block diagram according to various embodiments of an exemplary power supply 200. The power supply includes multiple power supply modules 202. Each power supply module 202 is electrically connected to a common output bus 204 via ORing elements 100 that may be similar or identical to the ORing elements 100 described above. The inputs 108 of the ORing elements 100 are connected to their respective power supply modules 202, while the outputs 110 of the ORing elements 100 are connected to the common output bus 204. In this way, the ORing elements may provide a buffer between the respective power supply modules 202 and the common output bus 204 as described above. It will be appreciated that the number of power supply modules 202 and ORing elements 100 may vary depending on the particular application.
In operation, when the various power supply modules 202 are operating properly, they may provide a voltage at input 108 that is, at least slightly, higher than the voltage at output 110 and the common output bus 204. Accordingly, the FET 's 102 (not shown in Figure 2) of the respective ORing elements 100 are in an active or saturation state, allowing forward current between the power supply modules 202 and the common output bus 204. If a power supply module 202 fails, then it may draw the input 108 of its corresponding ORing element 100 low. As a result, the FET 102 of the ORing element will be transisioned to an off state, preventing the failed power supply module 202 from drawing down the voltage at the common output bus 204.
It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for purposes of clarity, other elements, such as, for example, some specific terms of the instruments described above, etc. Those of ordinary skill in the art will recognize that these and other elements may be desirable. However, because such elements are well known in the art and because they do not facilitate a better understanding of the present invention, a discussion of such elements is not provided herein.
While several embodiments of the invention have been described, it should be apparent that various modifications, alterations and adaptations to those embodiments may occur to persons skilled in the art with the attainment of some or all of the advantages of the present invention. For example, the values of various components may be varied. Also various components (e.g. , resistors, filtering capacitors, etc.) may be added or removed to the circuits. The present description is therefore intended to cover all such modifications, alterations and adaptations without departing from the scope and spirit of the present invention as defined by the appended claims.
Next Patent: DRILL FOR MACHINING FIBER REINFORCED COMPOSITE MATERIAL