TECHNICAL FIELD

The present disclosure generally relates to wireless systems in which a central processing unit for a base station is coupled to a series of spatially separated transmitting and receiving antenna points via serial interfaces. The present disclosure relates more particularly to an improved serial interface in such a system.

BACKGROUND

The term “cell-free massive MIMO” has been used to refer to a massive Multiple-Input Multiple-Output (MIMO) system where some or all of the transmitting and receiving antennas for a base station are geographically distributed, apart from the base station. Each of the transmitting and receiving points may be referred to as an “antenna point,” “antenna processing node,” or “antenna processing unit.” These terms may be understood to be interchangeable for the purposes of the present disclosure, with the abbreviation “APU” being used herein. These APUs are communicatively coupled to and controlled by a controlling node, which is spatially separate from some or all of the APUs, may be referred to interchangeably as a “central processing node” or “central processing unit” - the abbreviation “CPU” is used herein. The interconnections between the APUs and the CPU may be referred to as a “fronthaul” network, while the CPU’s connection to a broader network may be regarded as the “backhaul.”

Figure 1 provides a conceptual view of a cell-free massive MIMO deployment, comprising a CPU 20 connected to several APUs 22, via serial links 10. As seen in the figure, each of several user equipments (UEs) 115 may be surrounded by one or several serving APUs 22, all of which may be attached to the same CPU 20, which is responsible for processing the data received from and transmitted by each APU. Each UE 115 may thus move around within this system without experiencing cell boundaries.

Systems described herein include at least CPU and two or more APUs spatially separated from each other and from the CPU. These systems, which may be considered examples of cell-free massive MIMO deployments, will be called distributed wireless systems herein. Figures 2 and 3 provide other views of example deployments of distributed wireless systems. In this scenario shown in Figure 2, multiple APUs 22 are deployed around the perimeter of a room, which might be a manufacturing floor or a conference room, for example. Each APU 22 is connected to the CPU 20 via a “strip,” or “stripe.” These might also be referred to as “chains” or “branches.” More particularly, the CPU 20 in this example deployment is connected to two such stripes, each stripe comprising a serial concatenation of several (10, in the illustrated example) APUs 22. Figure 3 shows an two-dimensional model of a factory floor with densely populated APUs 22 connected to the CPU 20 via several such “stripes.” As a general matter, the CPU 20 can target a UE anywhere in the room by controlling one or several APUs 22 that are closest to the UE to transmit signals to and receive signals from the UE.

In this example deployment, the APUs are spaced at 10 meters, in both x- and y- directions, which means that a UE is never more than about 7 meters away from one (or several) APUs, in the horizontal dimension.

It will be appreciated that the distribution of base station antennas into APUs as shown in Figures 1-3 can provide for shorter distances between the base station antennas and the antenna(s) for any given UE served by the base station, in many scenarios. This will be an enabler for the use of higher carrier frequencies, and thereby higher modulation/information bandwidths, both of which are key expectations for fifth generation (5G) wireless networks.

Another requirement of 5G networks is that they support a high quality-of-service (QoS). To achieve this, it is necessary that the radio link between the mobile/device/machine (UE) and the base station be highly reliable and support low-latency communications. This is especially the case for industrial scenarios, for example, where mission-critical real-time communication is needed for communications with or between machines equipped with devices. These communications and the supporting technologies are referred to as ultra-reliable low-latency communications (URLLC). It will be appreciated that distributed wireless systems like those shown in Figures 1-3 and described above are good candidates for ultra-reliable networking, since these deployments provide for multiple possible radio links between a given UE and the infrastructure network.

SUMMARY

Because the APUs in the distributed wireless systems shown in Figures 2 and 3 are connected to each other and to the CPU through a series of serial links, the serial interfaces in all of the APUs must generally be operating, even if only one or a few APUs are actively transmitting and/or receiving at a given time. Assuming the interface is Ethernet and POE (power over ethemet), inactive APUs will limit the system’s power budget even when not involved in the active transmission. This will tend to limit the maximum number of APUs that may be connected. Also, the maximum number of simultaneously active APUs than can be supported will be limited. Another potential problem with series-connected APUs as shown in Figures 2 and 3 is that the system may be vulnerable to single points of failure. If one APU breaks, the link to all subsequent APUs is also lost. Embodiments of the techniques described herein address these problems by providing a modified version of the well- known Ethemet serial interface.

A distributed wireless system according to several of the presently disclosed embodiments comprises a controlling node and two or more antenna processing nodes communicatively coupled to the controlling node but spatially separated from each other and from the controlling node. The controlling node sends commands to and exchanges data with a first subset of the antenna processing nodes, using a first twisted-pair lane of a physical layer interface having four twisted-pair lanes, and sends commands to and exchanging data with a second subset of the antenna processing nodes, using a second twisted-pair lane. In some embodiments, the controlling node also uses a third twisted-pair lane for communicating with the first subset, while using the fourth twisted-pair lane for communicating with the second subset. Corresponding antenna processing nodes terminate one or two twisted-pair lanes in a direction towards the controlling node, while terminating one or two twisted- pair lanes towards one or more antenna processing nodes further from the controlling node.

An example method according to some of the embodiments detailed below is carried out in a controlling node of a distributed wireless system that comprises the controlling node and two or more antenna processing nodes communicatively coupled to the controlling node but spatially separated from each other and from the controlling node. This example method comprises sending commands to and exchanging data with a first subset of the antenna processing nodes, using a first twisted-pair lane of a physical layer interface having four twisted-pair lanes. This example method further comprises sending commands to and exchanging data with a second subset of the antenna processing nodes, using a second twisted-pair lane of the physical layer interface.

In some embodiments, the method further comprises sending commands to and exchanging data with a third subset of the antenna processing nodes, using a third twisted-pair lane of the physical layer interface, and sending commands to and exchanging data with a fourth subset of the antenna processing nodes, using a fourth twisted-pair lane of the physical layer interface. In these embodiments, then, each subset of antenna processing nodes is served using only a single twisted-pair lane. In other embodiments, the sending commands to and exchanging data with the first subset of the antenna processing nodes comprises using the first twisted-pair lane as well as a third twisted-pair lane of the physical layer interface, and the sending commands to and exchanging data with the second subset of the antenna processing nodes comprises using the second twisted-pair lane as well as a fourth twisted-pair lane of the physical layer interface. In these embodiments, each subset of antenna processing nodes is served using two of the twisted-pair lanes.

Another example method according to some of the embodiments detailed below is carried out in a first antenna processing node of a distributed wireless system comprises a controlling node, the first antenna processing node, and one or more additional antenna processing nodes, each of the antenna processing nodes being communicatively coupled to the controlling node but spatially separated from each other and from the controlling node. This example method comprises receiving commands from and exchanging data with the controlling node, using a first twisted-pair lane of a physical layer interface having four twisted-pair lanes, and forwarding commands and data to and receiving data from one or more other ones of the antenna processing nodes, using a second twisted pair lane of the physical layer interface. In some embodiments, the method further comprises receiving commands from and exchanging data with the controlling node using a third twisted-pair lane of the physical layer interface as well as the first twisted-pair lane, and further comprises forwarding commands and data to and receiving data from one or more other ones of the antenna processing nodes using a fourth twisted-pair lane of the physical layer interface as well as the second twisted-pair lane.

Details and variants of the methods and apparatuses summarized above are described in the detailed description below, and illustrated in the attached figures.

BRIEF DESCRIPTION OF THE FIGURES

Figure 1 is an illustration of an example cell-free massive MIMO system.

Figure 2 illustrates an example deployment of a distributed wireless system.

Figure 3 illustrates another example deployment of a distributed wireless system.

Figure 4 is a block diagram of an example antenna processing node, according to some embodiments.

Figure 5 illustrates an example deployment of a distributed wireless system modified according to some of the techniques described herein.

Figure 6 illustrates the physical layer (PHY) according to the Ethernet standard.

Figure 7 illustrates bit mapping to four lanes, according to the Ethernet standard.

Figure 8 illustrates a modified mapping, according to some embodiments.

Figure 9 is a process flow diagram of an example method carried out by a controlling node, according to some embodiments.

Figure 10 is a process flow diagram illustrating an example method carried out by an antenna processing node, according to some embodiments.

Figure 11 is a block diagram of an example controlling node, according to some embodiments.

DETAILED DESCRIPTION

There are several possible approaches for implementing the interconnections between the CPU in a distributed wireless system and the APUs that it controls. One approach is to implement the interconnections between the CPUs and the APUs as a high-speed digital interface, e.g., such as a high-speed Ethernet connection, which might be a power-over-Ethemet (POE) connection. With this approach, information to be transmitted by a given APUs is sent from the CPU to the APU as digital baseband information. This digital baseband information is then up-converted to a radiofrequency (RF) signal in the APU, for transmission over the air. In the other direction, RF signals received from a UE are down converted in the APU and converted to digital form before being sent over the digital link to the CPU, for further processing.

The techniques described herein are focused the approach described above, i.e., on systems where a CPU is connected to multiple APUs via a series of serial links. In such a system, communications along these serial links may be described as “upstream” and “downstream” communications, where upstream communications are communications in the direction towards the CPU while downstream communications are in the opposite direction, i.e., away from the CPU. In the upstream direction, each APU thus sends its own data towards the CPU, via an upstream serial interface, along with any data that it receives from one or more APUs that are further downstream, via a downstream serial interface. This is seen in Figure 4, which is a block diagram illustrating components of an example APU, here illustrated as antenna processing node 400. As seen in the figure, the antenna processing unit 400 also receives communications for itself and for downstream APUs from the CPU, via the upstream serial interface 432, and forwards those communications intended for downstream APUs towards those APUs, via the downstream serial interface 434. Uikewise, the antenna process unit 400 sends data that it receives from one or more UEs to the CPU via the upstream serial interface 432, while also receiving similar data from other APUs via the downstream serial interface 434, which it then forwards to the CPU via the upstream serial interface 432.

The required capacity of the fronthaul network formed by these serial links is proportional to the number of simultaneous data streams that the APUs in the series can spatially multiplex, at maximum network load. The required capacity of the backhaul of the CPU (i.e., the CPUs connection towards the core network) is the sum of the data streams that the serial links connecting the APUs to the CPUs will transmit and receive at maximum network node. The most straightforward way to limit these capacity requirements is to constrain the number the number of UEs that can be served per APU and CPU. Put another way, the capacity of the distributed wireless system to serve UEs may be limited by the maximum capacities of the serial links between the APUs to the CPUs.

The use of serial interfaces as described above is generally a good match for downlink (DL) communications, i.e., communications from a base station to one or more UEs. Note that the terms “wireless device,” “user equipment,” and “UEs” are used herein to refer to any wireless devices served by the distributed wireless systems described here, including wireless devices that do not have a “user” as such but that are connected to machines. The serial interfaces described here work well for downlink communications because the same information may be sent to all of the APUs involved in any given transmission to a wireless device. This downlink information may be the bits or data blocks that must be transmitted by the APUs, with each APU involved in the transmission separately performing its own coding, modulation, upconversion, and transmission. There are other possibilities, however, such as the CPU sending to the APUs a time-domain digital representation of a modulated in-phase/quadrature (I/Q) signal, for upconversion and transmission, or the CPU sending to the APUs a frequency-domain digital representation of I/Q symbols, for OFDMA modulation, upconversion, and transmission by the APUs. In any of these cases, when the CPU sends this downlink information to two or more APUs in the chain, it need only send one copy, with each APU forwarding the information further downstream, as necessary.

Because the APUs in the distributed wireless systems shown in Figures 2 and 3 are connected to each other and to the CPU through a series of serial links, the serial interfaces in all of the APUs must generally be operating, even if only one or a few APUs are actively transmitting and/or receiving at a given time. Assuming the interface is Ethernet and POE (power over ethemet), inactive APUs will limit the system’s power budget even when not involved in the active transmission. This will tend to limit the maximum number of APUs that may be connected. Also, the maximum number of simultaneously active APUs than can be supported will be limited. Another potential problem with series-connected APUs as shown in Figures 2 and 3 is that the system may be vulnerable to single points of failure. If one APU breaks, the link to all subsequent APUs is also lost. Embodiments of the techniques described herein address these problems by providing a modified version of the well- known Ethemet serial interface.

High-speed Ethemet comprises Ethemet variants known as 1000BASE-T, 2.5GBASE-T, 5GBASE-T, 10GBASE-T, and 25GBASE-T, providing maximum raw data rates of 1, 2.5, 5, 10, and 25 Gbit/second, respectively. These variants are specific versions of what are known as Gigabit Ethemet, 2.5 Gigabit Ethemet, 5 Gigabit Ethemet, 10 Gigabit Ethemet, and 25 Gigabit Ethemet, respectively, typically utilize 8-conductor twisted-pair cabling, such as Cat 5e, Cat 6, Cat 6A, Cat 7, or Cat 8 cabling, which provide for four twisted-pair (TP) lanes. Each of these lanes carries one- fourth of the full duplex data carried by the cable. Details of Ethemet are defined in “IEEE Standard for Ethemet," in IEEE Std 802.3-2018 (Revision oflEEE Std 802.3-2015) , vok, no., pp.1-5600, 31 Aug. 2018; Clause 55, which defines the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA) sublayer, and baseband medium for type 10GBASE-T Ethemet is of particular relevance for 10 Gbit (and higher) data rate applications. This standard is referred to hereinafter as simply “the Ethemet Standard.”

In a distributed wireless system using a simple series configuration, e.g., as shown in Figures 2 and 3, each APU has two Ethemet connections, managed by respective Ethemet interface circuits, which may be referred to as Ethemet interfaces, or simply interfaces. These are shown in Figure 4 as upstream interface 432, which receives data from and transmits data towards the CPU, and downstream interface 434, which receives data from and transmits data towards APUs further away from the CPU. Each APU can be in either idle or active mode. In idle mode, an APU is only forwarding data to subsequent series connected devices and monitoring the Ethemet packages for requests (from the CPU) to change the APU’s state to active mode. In active mode, the APU is either transmitting or receiving data from the UE, with that data being received from or forwarded to the CPU, respectively.

The capacity of each connection/interface is dimensioned to handle the sum data traffic of all active APUs. Since the data rates to support 5G communications may be very high, the power consumption of the APUs in idle mode may be quite high, e.g., on the order of several Watts, with this idle-mode power consumption being dominated by the analog drivers connected to the Ethemet cables. An example Ethemet physical layer for a 10 Gbit Ethemet is described in J. R. Westra et a , "8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS," 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 146-147.

According to several of the embodiments described herein, rather than terminating all four lanes of the Ethernet cabling at each of the APU’s serial interfaces, each interface terminates only one or two of the four lanes. The other two or three lanes bypass the APU, for termination at a succeeding downstream APU, in the downstream direction, or at a succeeding upstream APU or the CPU, in the upstream direction. Figure 5 illustrates an example where two of the four Ethernet lanes are terminated at each interface, with each APU in the chain terminating the two lanes other that bypassed the preceding and/or succeeding APU. Thus, the first downstream APU in the illustrated system, labeled APU_0, terminates lanes 3 and 4 at its upstream serial interface, in this example, while lanes 1 and 2 bypass APU_0 and are terminated at APU_1. Likewise, lanes 3 and 4, which are terminated at the downstream interface of APU_0, bypass APU_1 and are terminated at the upstream interface of APU 2. This pattern is continued for APU 3 and any subsequent APUs in the chain. It will be appreciated that in an embodiment where only one lane is terminated at each of the downstream and upstream interfaces, every fourth APU will be connected to the same lane, and each lane will bypass three APUs between terminations.

A consequence of this, of course, is that the data rate supplied to a given APU is only one- half or one-fourth of the total capacity of the Ethernet cabling. At the same time, however, a given lane is serving only one-half or one-fourth of all the APUs in a chain, so both the aggregate data capacity and average per-APU capacities of the serial links are unchanged. If the aggregate data rate that can be sourced or terminated by the CPU is 10 Gbits/second, for example, then 5 Gbits/second can be supplied to or received from any of the APUs in the system shown in Figure 5, which will support high data transmission and reception rates by a single APU or by several APUs operating simultaneously.

A key benefit of the approach discussed above, as exemplified by the two-lane embodiment shown in Figure 5, is that each APU only needs to drive one-half or one-fourth of the TP lanes, compared to a scenario in which each APU interface terminated all four TP lanes supported by the Ethernet cable. This can reduce APU power consumption in idle mode by as much as 30-60%. Another benefit of the approach is that the overall system is more robust, in that single points of failure will cause degradation in system performance, but not total failure of large portions of the system. If one of the APUs in the system shown in Figure 4 fails, for example, then only one-half of the APUs further downstream from that APU are affected. The remainder will remain functional and available for communications. This improved system robustness also provides for enhanced upgradeability of the system. One-half or one-fourth of the APUs may be taken out of operation and upgraded, using the lane or lanes that connect them to the CPU, while the remaining APUs continue to operate normally. As discussed above, in the system illustrated in Figure 5, each APU is connected to only two TP lanes, in each direction (upstream and downstream). Physical connections to these upstream and downstream interfaces, which utilize only four wires each, can be made with a single 8-pin connector, e.g., a single RJ45 or 8P8C connector. Thus, for example, each APU may house only a single RJ45 or 8P8C jack, with four of the pins corresponding to the two lanes of the APU’s upstream serial interface and the remaining four pins corresponding to the two lanes of the APU’s downstream serial interface. In embodiments where only one lane is terminated at each APU interface, a single RJ45 or 8P8C connector might also be used, but in this case only four of the eight pins will be utilized.

The techniques described above may be applied to any of the Ethernet versions that utilize four TP lanes. As noted above, these include several standard versions, providing several rates and medium. For the distributed wireless systems described here, appropriate standard versions might include 2.5GBASE-T, 5GBASE-T and 10GBASE-T, although the techniques described herein are not limited to those specific versions. Each of these versions provides full duplex connections using copper-based TP-cables. The protocols for each are similar, with only the actual data/symbol rates differing. Actual data rates for these versions are 2.5, 5 and 10 Gbit/second, respectively.

Normally the data sent over the Ethernet cable when using these versions of the standard is spread evenly across all four lanes in the TP cable. To implement the techniques described above, a small deviation from the standards is necessary.

More particularly, Figure 6 shows the layer and signal flow inside the physical layer (PHY) in 10GBASE-T. This figure is reproduced from Figure 55-4 of the Ethernet standard. As seen in the figure, the Physical Medium Attachment (PMA) block is responsible for mapping the data onto the TP lanes. The details of the PCS and PMA block operation, as defined by the Ethernet standard, are shown in Figure 7, which is reproduced from Figure 55-6 of the Ethernet standard. As seen there, data blocks for transfer are encoded, scrambled, and aggregated, and a low-density parity-check (LDPC) code added, to form an LDPC frame. Bits from the LDPC frame are then transmitted down the four TP lanes using a double-square 128 (DSQ128) constellation. Here, pulse-amplitude modulation-16 (PAM- 16) signaling is used, two symbols at a time, with 7 bits (3 uncoded and 4 uncoded) mapped to these two symbols. The DSQ128 constellation is a constellation that uses only 128 of the possible 256 two-symbols, to increase the space between symbols.

As seen in Figure 7, the mapping of the symbols to the lanes in the 10GBASE-T Ethernet standard map successive PAM- 16 symbols to different lanes. Thus, PAM16i<0> is mapped to Pair A (lane 1), PAM16i<l> is mapped to Pair B (lane 2), PAM16i<2> is mapped to Pair C, and PAM16i<3> is mapped to Pair D. This is repeated for PAM16 ₂ <0>- PAM16 ₂ <3>, and so on. A consequence of this is that data in a given data block fed into the PCS block is spread across all four lanes. If only two lanes are terminated at a given APU, this means that half of the data in a given transport block would not reach that APU. This is addressed by redefining the mapping performed by the PMA block onto the TP lanes. Fig. 8 shows how this is done for a system like that shown in Figure 5, where each APU terminates two lanes. Here, PAM16i<0> is mapped to Pair A (lane 1) and PAM16i<l> is mapped to Pair B (lane 2), just as in the standard case. However, PAM16i<2> is mapped to Pair A, and PAM16i<3> is mapped to Pair B, which means that all the data from a given transport block is mapped to only two of the four lanes. Similar mapping can be performed separately for Pair C and Pair D, for data targeted to APUs targeting the other two lanes. Of course, in a system in which each APU terminates only a single lane, the PMA mapping is further modified so that data targeted to a given APU is mapped to a single TP lane. The PCS and PMA blocks are considered part of the physical (PHY) layer, which resides below the Ethernet data link so these modifications may be understood as modifying the existing standards for the existing Gigabit Ethernet PHY layer, 10 Gigabit Ethernet PHY later, etc., to obtain a modified Gigabit Ethernet PHY layer, while maintaining compatibility with an unmodified data link layer running at one-half or one-fourth its normal speed.

It will be appreciated that the techniques described above may be used to provide the advantages of reduced power consumption, for a given system data capacity, and improved system robustness. In specific embodiments utilizing the 10GBASE-T and similar variants of the Ethernet standard, these techniques may be implemented with minor changes to the physical (PHY) layer portion of the standard. The general techniques, whereby each APU in a distributed wireless system terminates only a subset of the lanes carried by a multi-lane data cable, are more generally applicable, of course.

Given the specific details and examples presented above, it will be appreciated that Figure 9 is a process flow diagram illustrating an example method according to some of the techniques described herein, as carried out by a controlling node or CPU. The controlling node performing this method is in a distributed wireless system that comprises the controlling node and two or more antenna processing nodes communicatively coupled to the controlling node but spatially separated from each other and from the controlling node, e.g., as shown in Figures 2 or 3.

As shown at block 910, the method comprises the step of sending commands to and exchanging data with a first subset of the antenna processing nodes, using a first twisted-pair lane of a physical layer interface having four twisted-pair lanes. As shown at block 920, the method further comprises sending commands to and exchanging data with a second subset of the antenna processing nodes, using a second twisted-pair lane of the physical layer interface. It will be appreciated that these steps may be performed at the same time, or in overlapping intervals, as the communications with the first and second subsets of antenna processing nodes may be independent, except for using parts of the same four TP -lane physical interface. Note that here and elsewhere in this document, the terms “first,” “second,” “third,” etc., are used nominally, i.e., merely to distinguish one instance of a thing from another, rather than ordinally, and thus should not be understood to imply a particular order unless the context demands otherwise. In some embodiments, as was discussed earlier, each of the antenna processing nodes may terminate only a single lane. In these embodiments, the method may then further comprise sending commands to and exchanging data with a third subset of the antenna processing nodes, using a third twisted-pair lane of the physical layer interface, and sending commands to and exchanging data with a fourth subset of the antenna processing nodes, using a fourth twisted-pair lane of the physical layer interface. These steps are shown in blocks 930 and 940, which are shown as the “one-lane variant” in Figure 9. In some of these embodiments sending commands to and exchanging data with the first subset of the antenna processing nodes comprises using a first Gigabit Ethernet or 10 Gigabit Ethernet data link layer and using a modified Gigabit Ethernet or 10 Gigabit Ethernet physical layer to map data processed by the first Gigabit Ethernet or 10 Gigabit Ethernet data link layer to and from only the first twisted-pair lane. Similarly, sending commands to and exchanging data with the second subset of the antenna processing nodes comprises using a second Gigabit Ethernet or 10 Gigabit Ethernet data link layer and using the modified Gigabit Ethernet or 10 Gigabit Ethernet physical layer to map data processed by the second Gigabit Ethernet or 10 Gigabit Ethernet data link layer to and from only the second twisted-pair lane. This can be extended to the third and fourth subsets, using the third and fourth twisted-pair lanes and third and fourth Gigabit data link layers.

In other embodiments, each of the antenna processing nodes may terminate only two of the four lanes. In these embodiments, sending commands to and exchanging data with the first subset of the antenna processing nodes may comprise using the first twisted-pair lane and a third twisted-pair lane of the physical layer interface, and sending commands to and exchanging data with the second subset of the antenna processing nodes comprises using the second twisted-pair lane and a fourth twisted-pair lane of the physical layer interface. The use of the third and fourth twisted-pair lanes in this variant is shown at blocks 950 and 960, which are shown as the “two-lane variant” in the Figure. In some embodiments of this two-lane variant, the first subset may comprise every second one of the antenna processing nodes, as ordered along cabling connecting the controlling node to the antenna processing nodes, while the second subset comprises the remaining ones of the antenna processing nodes.

In some embodiments of the two-lane variant, sending commands to and exchanging data with the first subset of the antenna processing nodes comprises using a first Gigabit Ethernet or 10 Gigabit Ethernet data link layer and using a first modified Gigabit Ethernet or 10 Gigabit Ethernet physical layer to map data processed by the first Gigabit Ethernet or 10 Gigabit Ethernet data link layer to and from only the first and third twisted-pair lanes. Similarly, sending commands to and exchanging data with the second subset of the antenna processing nodes may comprise using a second Gigabit Ethernet or 10 Gigabit Ethernet data link layer and using a second modified Gigabit Ethernet or 10 Gigabit Ethernet physical layer to map data processed by the second Gigabit Ethernet or 10 Gigabit Ethernet data link layer to and from only the third and fourth twisted-pair lanes. With either of the variants described above, sending commands to and exchanging data with the first subset of the antenna processing nodes and said sending commands to and exchanging data with the second subset of the antenna processing nodes may be performed via a single 8P8C or RJ45 connector interface, in some embodiments.

As was noted in the above discussion, one advantage of the techniques described herein is that robustness of the system with respect to antenna process node failures is improved. Thus, in some embodiments or instances of the method shown in Figure 9, the method carried out by the controlling node may comprise determining that communications with a first antenna processing node have failed, the first antenna processing node being in the first subset and having been used by the controlling node to communicate with a first user equipment. This is shown at block 970. The method may further comprise, in response to this determination, shifting communications with the first user equipment to at least a second antenna processing node, in the second subset. In other words, commands and/or data previously sent to the first antenna processing node, e.g., for communication with one or more UEs served by that antenna processing node, are now sent to another antenna processing node. Because one or more other antenna processing node in the first subset may now be unavailable, because of the failure of the antenna processing node in the first subset, these commands and/or data are now sent to an antenna processing node in the second subset. Because those antenna processing nodes in the second subset are connected to the controlling node through one or two TP lanes that are separate from those connecting the failed antenna processing node, all of the antenna processing nodes in the second subset should still be in operation.

Power over Ethernet (POE) was also mentioned above. This allows the DC electrical power for operating a device to be supplied over the Ethernet cable, eliminating the need for batteries or other power supplies at each of the antenna processing nodes. The POE concept may still be used in embodiments of the presently disclosed systems, but must be modified so that DC power is supplied separately to each of the subsets of antenna processing nodes, since they are connected to the controlling node through separate subsets of the TP lanes. Thus, in some embodiments of the method disclosed in Figure 9, the method further comprises supplying electrical power to the first subset of antenna processing nodes via at least one conductor of the first twisted-pair lane and supplying electrical power to the second subset of antenna processing nodes via at least one conductor of the second twisted-pair lane. This is shown at block 905. Note that in the one-lane variant, electrical power would in these embodiments also be sent to the third subset of antenna processing nodes via at least one conductor of the third twisted-pair lane and to the fourth set of antenna processing nodes via at least one conductor of the fourth twisted-pair lane.

Figure 10 illustrates an example method, according to some of the embodiments described herein, as might be implemented in a first antenna processing node of a distributed wireless system that comprises a controlling node, the first antenna processing node, and one or more additional antenna processing nodes, each of the antenna processing nodes being communicatively coupled to the controlling node but spatially separated from each other and from the controlling node. Again, the term “first” as used here does not imply any particular order or placement of the first antenna processing node within the system.

The method of Figure 10 includes the step of receiving commands from and exchanging data with the controlling node, using a first twisted-pair lane of a physical layer interface having four twisted-pair lanes, as shown at block 1010. The method also includes the step of forwarding commands and data to and receiving data from one or more other ones of the antenna processing nodes, using a second twisted-pair lane of the physical layer interface, as shown at block 1020. It will be appreciated that the first twisted-pair lane here carries communications between the first antenna processing node and the controlling node, i.e., in the upstream direction. However, depending on where this first antenna processing node is in a series of antenna processing nodes, this first twisted pair lane may be terminated at its other end by another antenna processing node between the first antenna processing and the controlling node, rather than at the controlling node directly. The second twisted-pair lane referred to here, on the other hand, carries communications to and from one or more antenna processing nodes further away from the controlling node, i.e., in the downstream direction.

As discussed above, in some embodiments an antenna processing node may terminate only one twisted-pair lane in each of the upstream and downstream directions. In these embodiments, then, the receiving commands from and exchanging data with the controlling node, as shown at block 1010, is performed using only the first twisted-pair lane. Likewise, the forwarding commands and data to and receiving data from one or more other ones of the antenna processing nodes, as shown at block 1020, is performed using only the second twisted-pair lane. In these embodiments, other twisted-pair lanes in a typical cable supporting four twisted-pair lanes are not used by this antenna processing node, but may be used by other groups of antenna processing nodes in the system.

In these embodiments, i.e., where the antenna processing node terminates only one twisted pair lane in each of the upstream and downstream directions, the receiving commands from and exchanging data with the controlling node using the first twisted-pair lane may comprise using a first Gigabit Ethernet or 10 Gigabit Ethernet data link layer and using a modified Gigabit Ethernet or 10 Gigabit Ethernet physical layer to map data processed by the first Gigabit Ethernet or 10 Gigabit Ethernet data link layer to and from only the first twisted-pair lane. Likewise, the forwarding commands and data to and receiving data from one or more other ones of the antenna processing nodes may comprise using a second Gigabit Ethernet or 10 Gigabit Ethernet data link layer and using the modified Gigabit Ethernet or 10 Gigabit Ethernet physical layer to map data processed by the second Gigabit Ethernet or 10 Gigabit Ethernet data link layer to and from only the second twisted pair lane.

In other embodiments, the first antenna processing node may terminate two twisted-pair lanes in each direction. In these embodiments, then, receiving commands from and exchanging data with the controlling node comprises using the first twisted-pair lane and a third twisted-pair lane of the physical layer interface. Similarly, forwarding commands and data to and receiving data from one or more other ones of the antenna processing nodes may comprise using the second twisted-pair lane and a fourth twisted-pair lane of the physical layer interface. The use of these third and fourth twisted-pair lanes is shown in Figure 10 at blocks 1030 and 1040, which are labeled as the “two-lane alternative.”

In these embodiments, the two twisted-pair lanes terminated in a given direction may be mapped to a single Ethernet stack, in a manner similar to but modified from how four twisted-pair lanes are mapped to an Ethernet stack in standard versions of 1000BASE-T or 10GBASE-T, for example. Thus, receiving commands from and exchanging data with the controlling node may comprise using a first Gigabit Ethernet or 10 Gigabit Ethernet data link layer and using a first modified Gigabit Ethernet or 10 Gigabit Ethernet physical layer to map data processed by the first Gigabit Ethernet or 10 Gigabit Ethernet data link layer to and from only the first and third twisted-pair lanes. Likewise, forwarding commands and data to and receiving data from one or more other ones of the antenna processing nodes may comprise using a second Gigabit Ethernet or 10 Gigabit Ethernet data link layer and using a second modified Gigabit Ethernet or 10 Gigabit Ethernet physical layer to map data processed by the second Gigabit Ethernet or 10 Gigabit Ethernet data link layer to and from only the second and fourth twisted-pair lanes.

In any of the embodiments described above, the receiving commands from and exchanging data with the controlling node and said forwarding commands and data to and receiving data from one or more other ones of the antenna processing nodes are performed via a single 8P8C or RJ45 connector interface. In the two-lane alternatives, this would use all 8 pins of the connector, to terminate two lanes in the upstream direction and two lanes in the downstream direction. It will be appreciated, of course, that this will require the use of a split cable attached to the 8-pin connector, to carry the two upstream lanes in one direction while carrying the two downstream lanes in the other. In embodiments of the one-lane alternatives described above, only four pins of the connector are needed to terminate the single lane in the upstream direction and the single lane in the downstream direction.

As discussed above a modified version of Power over Ethernet may be used here. Thus, in some embodiments, the method illustrated in Figure 10 may comprise receiving electrical power from the controlling node via at least one conductor of the first twisted-pair lane and supplying electrical power to the one or more other ones of the antenna processing nodes via at least one conductor of the second twisted-pair lane. This is shown at block 1005. Note that supplying electrical power to the one or more antenna processing nodes may simply comprise electrically connecting the conductor on which the electrical power is received, from the first twisted-pair lane, to the conductor for supplying power on the second twisted-pair lane. This effectively connects the antenna processing node and downstream antenna processing nodes in parallel, with respect to the power supplied by the controlling node. Generating a new high-voltage power supply on board the antenna processing node, for supplying downstream antenna processing nodes, is not necessary. Figure 11 is a block diagram illustrating an example controlling node 1100, according to some embodiments. Controlling node 1100 includes a processing circuit 1110, which in turn includes one or more processors 1104, controllers, or the like, coupled to memory 1106, which may comprise one or several types of memory, such as random-access memory, read-only memory, flash memory, etc. Stored in memory 1106 may be computer program code for execution by processor(s) 1104, including program code configured to cause the controlling node 1100 to carry out any one or more of the techniques described herein, such as the methods discussed above in connection with Figures 8 and 10.

Controlling node 1100 further comprises serial interface circuitry 1120 operatively coupled to the processing circuit 1110. Serial interface circuitry 1120 includes a first serial interface 1122 configured to transmit data to and receive data from one or several antenna processing nodes connected in series, via a serial link connected to the serial interface 1122. The one or several antenna processing nodes connected via this first serial interface 1122 may be considered to be a first stripe, branch, or chain. Serial interface circuitry 1120 also comprises a second serial interface 1124, configured to transmit data to and receive data from a second set of antenna processing nodes connected in series, via a serial link connected to the second serial interface 1124. These antenna processing nodes may be considered to be a second stripe, branch, or chain. Thus, the controlling node 1100 may be able to separately control two (or more) stripes, branches, or chains of antenna processing nodes, through respective serial interfaces.

More particularly, it will be appreciated that serial interface circuitry 1120 is (a) configured to communicate with a first subset of antenna processing nodes using only one or two twisted-pair lanes while communicating with a second subset of antenna processing nodes using another one or two twisted-pair lanes, e.g., in accordance with the method illustrated in Figure 9, and variants thereof.

While not shown in Figure 11, in some embodiments the controlling node 1100 may be collocated with or include an antenna processing node or comparable functionality, e.g., as shown in Figure 4. From a functional standpoint, this collocated antenna processing node functionality may be treated in the same manner as other antenna processing nodes in a series.

Referring again to Figure 4, this figure is a block diagram illustrating an example antenna processing node 400, according to some embodiments. Antenna processing node 400 includes radio circuitry 410 and antennas 415, processing circuit 420, and serial interface circuitry 430, which includes a first serial interface 432, initially facing “upstream” towards a controlling node, as well as a second serial interface 434, initially facing “downstream,” towards one or more subsequent antenna processing nodes. According to various embodiments as disclosed herein, the upstream interface may terminate only one or two twisted-pair lanes and the downstream interface may likewise terminate only one or two twisted-pair lanes, e.g., according to the methods illustrated in Figure 10, and variants thereof. Radio circuitry 410 includes receive (RX) and transmit (TX) functionality for communicating with one or more wireless devices via antennas 415. For downlink communications, i.e., radio communications to one or more wireless devices, the radio circuitry 410 includes TX circuitry 414 configured to receive baseband information relayed to the radio circuitry 410 from a controlling node, via the upstream serial interface 432 and the processing circuit 420. TX circuitry 414 includes upconverter circuits, power amplifier circuits, and filter circuits to convert this baseband information to radio frequency and condition it for transmission to one or more wireless devices. For uplink communications, i.e., radio communications from one or more wireless devices, the radio circuitry 410 includes RX circuitry 412 configured to receive wireless transmissions via antennas 415, amplify, filter, and downconvert the received transmissions, and sample the downconverted transmissions to obtain soft information corresponding to the received wireless transmission. This soft information may be in the form of I-Q samples, for instance, and may be interchangeably referred to as soft bits or soft bit information. The soft bit information is passed to processing circuit 420, for processing and further handling, which may include sending the soft bit information to the controlling node.

Processing circuit 420 includes one or more processors 424, controllers, or the like, coupled to memory 426, which may comprise one or several types of memory, such as random-access memory, read-only memory, flash memory, etc. Stored in memory 426 may be computer program code for execution by processor(s) 424, including program code configured to control the radio circuitry 410 and serial interface circuitry 430 and to cause the antenna processing node 400 to carry out any one or more of the techniques described herein, such as the methods discussed above in connection with Figure 10.

Further embodiments comprise distributed wireless systems comprising one or more controlling nodes like those described above as well as one or more antenna processing nodes. These distributed wireless systems may be deployed in any of a wide variety of configurations. The controlling node(s) in such a distributed wireless system may utilize any of the techniques described herein, e.g., as shown in Figure 9, while the antenna processing nodes in the system utilize any one or more of the techniques illustrated in Figure 10, for example.

Reference has been made herein to various embodiments. However, a person skilled in the art would recognize numerous variations to the described embodiments that would still fall within the scope of the claims. For example, the method embodiments described herein describes example methods through method steps being performed in a certain order. However, it is recognized that these sequences of events may take place in another order without departing from the scope of the claims. Furthermore, some method steps may be performed in parallel even though they have been described as being performed in sequence.

In the same manner, it should be noted that in the description of embodiments, the partition of functional blocks into particular units is by no means limiting. Contrarily, these partitions are merely examples. Functional blocks described herein as one unit may be split into two or more units. In the same manner, functional blocks that are described herein as being implemented as two or more units may be implemented as a single unit without departing from the scope of the claims.

Hence, it should be understood that the details of the described embodiments are merely for illustrative purpose and by no means limiting. Instead, all variations that fall within the range of the claims are intended to be embraced therein.