Title:
IMPROVED LAYOUT TECHNIQUE FOR A MATCHING CAPACITOR ARRAY USING A CONTINUOUS UPPER ELECTRODE
Document Type and Number:
WIPO Patent Application WO2000039821
Kind Code:
A3
Abstract:
A matching capacitor array is implemented on a single, monolithic integrated circuit. The array fastures a matrix of bottom electrodes and a plurality of continuous top electrode strips, where each continuous top electrode strip spans numerous bottom electrodes. The conductive contacts for each continuous top electrode strip are removed from the capacitor interface to the terminal ends of each of the continuous top electrode strips. The invention seeks to match or control parasitic and fringe capacitance, rather than to eliminate or minimize such capacitances. By creating a matched array, the parasitic and fringe capacitances of each matching capacitor unit cell are incorporated into the total capacitance of the unit cell.
Inventors:
YACH RANDY L
WOJEWODA IGOR
WOJEWODA IGOR
Application Number:
PCT/US1999/030528
Publication Date:
October 26, 2000
Filing Date:
December 20, 1999
Export Citation:
Assignee:
MICROCHIP TECH INC (US)
International Classes:
H01G4/38; H01L27/08; (IPC1-7): H01L27/08; H01L29/92
Foreign References:
| EP0419278A2 | 1991-03-27 | |||
| EP0810663A1 | 1997-12-03 | |||
| US5322438A | 1994-06-21 | |||
| US5838032A | 1998-11-17 |
Other References:
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 02 29 February 1996 (1996-02-29)
PATENT ABSTRACTS OF JAPAN vol. 014, no. 511 (E - 0999) 8 November 1990 (1990-11-08)
PATENT ABSTRACTS OF JAPAN vol. 014, no. 511 (E - 0999) 8 November 1990 (1990-11-08)
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