| US4954951A | 1990-09-04 | |||
| US3821715A | 1974-06-28 | |||
| US4701843A | 1987-10-20 | |||
| US4829484A | 1989-05-09 | |||
| US4910706A | 1990-03-20 | |||
| US4005395A | 1977-01-25 | |||
| US4953130A | 1990-08-28 | |||
| US3811117A | 1974-05-14 |
"Microprocessors", (MOTOROLA), 1983 (see page 3-470, 3-479, 3-484, 3-392, 3-481 ("FS), 3-481, ("HS").
See also references of EP 0549633A4
| 1. | A memory system comprising: a memory storing data; an address generator circuit generating an address having less significant bits and more significant bits; an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address; a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit; and a όe\aγ\ng cucuft coυpteά to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal. |
| 2. | A memory system as set forth in claim 1, wherein the detector circuit includes a buffer circuit coupled to the address generator circuit and storing the more significant bits of the address and a comparator circuit coupled to the address generator circuit and comparing the more significant bits of the address stored by the buffer circuit and the more significant bits of the address generated by the address generator circuit and generating the detector signal in response to the comparison thereof. |
| 3. | A memory system as set forth in claim 1, wherein the detector circuit includes an overflow circuit coupled to the address generator circuit and detecting an overflow to the more significant bits of the address generated by the address generator circuit and generating the detector signal in response to the overflow. |
| 4. | A memory system as set forth in claim 1, wherein the address generated by the address generator circuit further includes middle significant bits, wherein the delaying circuit is a first delaying circuit, wherein the delaying of the generating of the address by the address generator circuit is by the first delaying circuit and has a first delay period, and wherein the memory system further comprises: a second detector circuit coupled to the address generator circuit and generating a second detector signal in response to detection of a change in the middle significant bits of the address generated by the address generator circuit; and SUBSTITUTE SHEE a second delaying circuit coupled to the address generator circuit and to the second detector circuit and delaying generating of the address by the address generator circuit by a second delay period that has a different delay period than the first delay period in response to the second detector signal. |
| 5. | A memory system comprising: a memory having a plurality of memory chips and storing data; an address generator circuit generating an address having less significant bits and more significant bits; an addressing circuit coupled to the memory and to the address generator circuit and addressing data stored by the memory in response to the more significant bits of the address; and a scanout circuit coupled to the memory and to the address generator circuit and scanning out data stored by each of a plurality of memory chips in sequence in response to the less significant bits of the address. |
| 6. | A memory system as set forth in claim 5, further comprising a detector circuit coupled to the address generator circuit and generating a detector signal in response to the more significant bits of the address. |
| 7. | A memory system as set forth in claim 5, further comprising: a detector circuit coupled to the address generator circuit and generating a detector signal in response to the more significant bits of the address and a delaying circuit coupled to the address generator circuit and to the deteαor circuit and delaying generating of the address by the address generator circuit in response to the detector signal. |
| 8. | A memory system as set forth in claim 5, wherein the address generated by the address generator circuit further includes middle significant bits and wherein the memory system further comprises: a first detector circuit coupled to the address generator circuit and generating a first detector signal in response to the more significant bits of the address; a first delaying circuit coupled to the address generator circuit and to the first detector circuit and delaying generating of the address by the address generator circuit by a first delay period in response to the first detector signal; SUBSTITUTE SHEET a second detector circuit coupled to the address generator circuit and generating a second detector signal in response to the middle significant bits of the address; and a second delaying circuit coupled to the address generator circuit and to the second detector circuit and delaying generating of the address by the address generator circuit by a second delay period that has a different delay period than the first delay period in response to the second detector signal. |
| 9. | A memory system as set forth in claim 5, wherein the scanout circuit is arranged for selecting at least one of the integrated circuit memory chips to output data addressed by the chip addressing circuit in response to the less significant bits of the address and wherein the memory system further comprises a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit. |
| 10. | A memory system as set forth in claim 5, further comprising: an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address; a detector circuit coupled to the address generator circuit and generating a detector signal in response to the address generated by the address generator circuit; a scanout address update circuit coupled to the address generator circuit and to the detector circuit and updating the address generated by said address generator circuit at a first address update rate in response to a first state of the detector signal; and a readdressing address update circuit coupled to the address circuit and to the detector circuit and updating the address generated by said address generator circuit at a second address update rate that is lower than said first address update rate in response to a second state of the detector signal. |
| 11. | A memory system as set forth in claim 5, further comprising: an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address; and a comparator circuit coupled to the address generator circuit and generating a comparator signal in response to detection of a change in the address. SUBSTITUTE SHEET . |
| 12. | A memory system as set forth in claim 5, further comprising: a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the address generated by the address generator circuit; a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal; a scanout address update circuit updating the address at a first address update rate in response to a first state of the detector signal; and a readdressing address update circuit updating the address at a second address update rate that is lower than the first address update rate in response to a second state of the detector signal. |
| 13. | A memory system as set forth in claim 5, further comprising: a chip selection circuit coupled to the address generator circuit and to the plurality of integrated circuit memory chips and selecting at least one of the integrated circuit memory chips to output data addressed by the addressing circuit in response to the less significant bits of the address; a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit; and a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal. |
| 14. | A memory system comprising: an integrated circuit memory having a plurality of integrated circuit memory chips storing data; an address generator circuit generating an address having less significant bits and more significant bits; a chip addressing circuit coupled to the memory and to the address generator circuit and addressing data stored by each of the plurality of integrated circuit memory chips in response to the more significant bits of the address; and a chip select circuit coupled to the memory and to the address generator circuit and selecting one of the plurality of integrated circuit memory chips in response to the less significant bits of the address. SUBSTITUTE SHEET . |
| 15. | A memory system as set forth in claim 14, further comprising a detector circuit coupled to the address generator circuit and generating a detector signal in response to the more significant bits of the address. |
| 16. | A memory system as set forth in claim 14, further comprising: a detector circuit coupled to the address generator circuit and generating a detector signal in response to the more significant bits of the address and a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal. |
| 17. | A memory system as set forth in claim 14, wherein the address generated by the address generator circuit further includes middle significant bits and wherein the memory system further comprises: a first detector circuit coupled to the address generator circuit and generating a first detector signal in response to the more significant bits of the address; a first delaying circuit coupled to the address generator circuit and to the first detector circuit and delaying generating of the address by the address generator circuit by a first delay period in response to the first detector signal; a second detector circuit coupled to the address generator circuit and generating a second detector signal in response to the middle significant bits of the address; and a second delaying circuit coupled to the address generator circuit and to the second detector circuit and delaying generating of the address by the address generator circuit by a second delay period that has a different delay period than the first delay period in response to the second detector signal. |
| 18. | A memory system comprising: an integrated circuit memory having a plurality of integrated circuit memory chips storing data; ~ an address generator circuit generating an address having less significant bits and more significant bits; a chip addressing circuit coupled to the memory and to the address generator circuit and addressing data stored by each of the plurality of integrated circuit memory chips in response to the more significant bits of the address; SUBSTITUTE SHEET a chip select circuit coupled to the memory and to the address generator circuit and selecting one of the plurality of integrated circuit memory chips in response to the less significant bits of the address; a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address; and a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal. |
| 19. | A memory system comprising: a memory storing data; an address generator circuit generating an address having less significant bits and more significant bits; a detector circuit coupled to the address generator circuit and generating a first detector signal condition in response to detection of a change in the more significant bits of the address generated by the address generator circuit and generating a second detector signal condition in response to detection of the absence of a change in the more significant bits of the address generated by the address generator circuit; a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the first detector signal condition; and an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the memory in response to the address, said accessing circuit scanning out data stored by the memory at a higher data rate in response to the less significant bits of the address and readdressing data stored by the memory at a lower rate in response to the more significant bits of the address. |
| 20. | A memory computer system comprising: a first memory storing data; a read only memory storing a computer program; an address generator circuit generating an address having less significant bits and more significant bits; an accessing circuit coupled to the first memory and to the address generator circuit and accessing data stored by the memory in response to the address; tUBSTITUTE SHEET a stored program computer coupled to the accessing circuit and to the read only memory processing the data accessed by the accessing circuit under control of the program stored by the read only memory; a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator circuit; and a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal. |
| 21. | A memory system comprising: a memory storing data; an address generator circuit generating an address; an accessing circuit coupled to the memory and to the address generator and reading data stored by the memory to generate memory output data in response to the address; a processor coupled to the accessing circuit and processing the memory output data; a detector circuit coupled to the address generator circuit and generating a detector signal in response to detection of a change in the address generated by the address generator circuit; and a delaying circuit coupled to the address generator circuit and to the detector circuit and delaying generating of the address by the address generator circuit in response to the detector signal. |
| 22. | A memory system as set forth in claim 21, wherein the memory includes a plurality of RAMs storing data, and wherein the memory system further comprises: a scanout address update circuit coupled to the address generator circuit and to the detector circuit and updating the address generated by the address generator circuit at a first address update rate in response to a first state of the detector signal; and a readdressing address update circuit coupled to the address generator circuit and to the detector circuit and updating the address generated by the address generator circuit at a second address update rate that is lower than the first address update rate in response to a second state of the detector signal. SHEET TΓΓUTE BS . |
| 23. | A memory system as set forth in claim 21, wherein the includes a plurality of integrated circuit memory chips storing data, wherein the address generated by the address generator circuit has less significant bits and more significant bits, wherein the accessing circuit reads the data stored by the memory in response to the more significant bits of the address, wherein the accessing circuit reads data stored by the memory in response to the more significant bits of the address, and wherein the memory system further comprises: an addressing circuit coupled to the integrated circuit memory and to the address generator circuit and addressing data stored by the integrated circuit memory in response to the more significant bits of the address; a chip selection circuit coupled to the integrated circuit memory and to the address generator circuit and selecting an integrated circuit memory chip in response to the less significant bits of the address; an output circuit coupled to the addressing circuit, to the chip selection circuit, and to the memory and outputting the data read by the accessing circuit in response to the more significant bits of the address from an integrated circuit memory chip selected by the less significant bits of the address; an external scanout address update circuit coupled to the address generator circuit and to the deteαor circuit and updating the address generated by the address generator circuit at a first address update rate in response to a first state of the deteαor signal; and a readdressing address update circuit coupled to the address generator circuit and to the deteαor circuit and updating the address generated by address generator circuit at a second address update rate that is lower than said first address update rate in response to a second state of the deteαor signal. |
| 24. | A memory system as set forth in claim 21, wherein the memory includes a plurality of integrated circuit memory chips storing data; a chip addressing circuit coupled to the memory and to the address generator circuit and addressing data stored by each of the plurality of integrated circuit memory chips in response to the address; and a chip seleα circuit coupled to the memory and to the address generator circuit and seleαing one of the plurality of integrated circuit memory chips in response to the address. STITUTE SHEET . |
| 25. | A memory system as set forth in claim 21, wherein said memory includes a plurality of integrated circuit random access memory chips storing the digital data, wherein said memory chips have an address input circuit coupled to the addressing circuit and operating in response to the address and a multiple dimensional control circuit outputting the digital data under control of the output circuit. |
| 26. | A memory system comprising: an integrated circuit memory having a plurality of integrated circuit memory chips storing data; an address generator circuit generating an address; an addressing circuit coupled to the integrated circuit memory and to the address generator circuit and addressing data stored by the integrated circuit memory in response to the address; a chip seieαion circuit coupled to the integrated circuit memory and to the address generator circuit and seleαing an integrated circuit memory chip in response to the address; an accessing circuit coupled to the addressing circuit, to the chip seieαion circuit, and to the integrated circuit memory and outputting the data addressed in response to the address from an integrated circuit memory chip seleαed by the address; a deteαor circuit coupled to the address generator circuit and generating a deteαor signal in response to deteαion of a change in the address generated by the address generator circuit; a delaying circuit coupled to the address generator circuit and to the deteαor circuit and delaying generating of the address by the address generator circuit in response to the deteαor signal; an external scanout address update circuit coupled to the address generator circuit and to the deteαor circuit and updating the address generated by the address generator circuit at a first address update rate in response to a first state of the deteαor signal; and a readdressing address update circuit coupled to the address generator circuit and to the deteαor circuit and updating the address generated by address generator circuit at a second address update rate that is lower than said first address update rate in response to a second state of the detector signal. |
| 27. | A computer system comprising: an address circuit generating a memory address; an accessing circuit coupled to the address circuit for accessing computer instruαions from a dynamic memory in response to the memory address; a processing circuit coupled to the accessing circuit and executing the computer instruαions accessed thereby; and a memory refresh deteαor coupled to the accessing circuit and to the processing circuit and generating a memory refresh signal in response to deteαion of a period during execution of an instruαion by the processing circuit that the accessing circuit is not accessing a computer instruαion. |
| 28. | A computer system as set forth in claim 27, wherein the address circuit, the accessing circuit, the processing circuit, and the memory refresh deteαor are included on a first single integrated circuit chip and wherein the computer system further comprises a dynamic memory included on at least one other integrated circuit chips, coupled to the accessing circuit and storing the computer instruαions. |
| 29. | A computer system as set forth in claim 27, further comprising: a dynamic memory coupled to the accessing circuit and to the processing circuit and storing the computer instruαions; a refresh circuit coupled to the dynamic memory and to the memory refresh deteαor and refreshing the dynamic memory in response to the memory refresh signal for a period during execution of an instruαion by the processing circuit that the accessing circuit is not accessing a computer instruαion. |
| 30. | A computer system comprising: an address circuit generating a memory address; an accessing circuit coupled to the address circuit for accessing computer instruαions from a dynamic memory in response to the memory address; a processing circuit coupled to the accessing circuit and executing the computer instruαions accessed thereby; and a memory refresh circuit coupled to the processing circuit and refreshing a dynamic memory during execution of an instruαion by the processing circuit. SUBSTITUTE SHEET . |
| 31. | A computer system as set forth in claim 30, wherein the computer system further comprises a dynamic memory coupled to the accessing circuit and storing the computer instruαions. |
| 32. | A processor system comprising: an address circuit generating a memory address; an accessing circuit coupled to the address circuit for accessing data from a dynamic memory in response to the memory address; a processing circuit coupled to the accessing circuit for processing data accessed from a dynamic memory; and a memory refresh deteαor coupled to the accessing circuit and to the processing circuit and generating a memory refresh signal in response to deteαion of a period having sufficient time available to perform a refresh operation. |
| 33. | A processor system as set forth in claim 32, wherein the processor system further comprises a dynamic memory coupled to the accessing circuit and storing the data. |
| 34. | A memory system comprising: a dynamic memory storing data; a refresh circuit coupled to the dynamic memory and refreshing the data stored by the dynamic memory; and a refresh monitor coupled to the refresh circuit and generating a refresh number related to the number of refresh operations that are pending within a refresh period. |
| 35. | A computer system comprising: an address circuit generating a memory address; a dynamic memory storing computer instruαions; an accessing circuit coupled to the address circuit and to the dynamic memory and accessing ccfrπputer instruαions in response to the memory address; a computer coupled to the accessing circuit and executing the computer instruαions accessed thereby; a deteαor circuit coupled to the computer and generating a deteαor signal in response to deteαion of a period during execution of an SUBSTITUTE SHEET instruαion by the computer that the computer is not accessing the dynamic memory; and a refresh circuit coupled to the dynamic memory and to the computer and refreshing the dynamic memory during execution of an instruαion by the computer in response to the deteαor signal. |
| 36. | A display system comprising: a synchronization generator generating a synchronization signal; a display processor coupled to the synchronization generator and processing display information in synchronization with the synchronization signal; a display coupled to the synchronization generator and to the display processor and displaying display information in synchronization with the synchronization generator and in response to the display information processed by the display processor. |
| 37. | A display system as set forth in claim 36, wherein the synchronization signal is a frame synchronization signal. |
| 38. | A display system as set forth in claim 36, wherein the synchronization signal is a line synchronization signal. |
| 39. | A memory system comprising. a first address generator generating a first memory address; a second address generator generating a second memory address; a memory storing information; a memory accessing circuit coupled to the first address generator, to the second address generator, and to the memory and • '■essing information stored by the memory in response to the first memory addre« and to the second memory address. |
| 40. | A memory system comprising: an address generator generating a memory address; a memory storing information and including a plurality of memory chips eleαrically arranged in rows and columns of memory chips; an accessing circuit coupled to the address generator and to the memory and accessing information stored by the memory in response to the memory address; wherein the accessing circuit includes a row seleα circuit SUBSTITUTE SHEET seleαing a row of memory chips in response to a first portion of the memory address, a column seleα circuit seleαing a column of memory chips in response to a second portion of the memory address, and an output circuit outputting information from a memory chip that is seleαed by the row seleα circuit and by the column seleα circuit. |
| 41. | A display system comprising: a display memory storing a plurality of veαors each veαor having a plurality of pixels along the veαor direαion; a display processor generating a plurality of sets of coordinates each set of coordinates being related to a different veαor; a veαor generator coupled to the display processor and generating veαors each veαor having a plurality of pixels along the veαor direαion and each veαor being generated in response to a set of coordinates, wherein the veαor generator includes a) a first register storing a first number, b) a second register storing a second number, c) a third register storing a third number, d) a forth register storing a forth number, e) a first initial condition circuit coupled to the first register, the second register, the third register, and the forth register and loading an initial first number related to a first coordinate direαion into the first register, loading an initial second number related to a second coordinate direαion into the second register, loading an initial third number into the third register, and loading an initial forth number into the forth register, f) a first update circuit coupled to the first register and to the third register and repetitively updating the third number in response to the first number, and g) a second update circuit coupled to the second register and to the forth register and repetitively updating the forth number in response to the second number; and a writing circuit coupled to the third register, to the forth register, and to the dispteymemoryand writing a plurality of pixels along a veαor direαion of each veαor into the display memory in response to the third number SUBSTITUTE SHEET and in response to the forth number. |
| 42. | A display system as set forth in claim 41 , wherein the veαor generator further includes h) a fifth register storing a fifth number, i) a sixth register storing a sixth number, j) a seventh register storing a seventh number, k) an eighth register storing an eighth number, I) a second initial condition circuit coupled to the fifth register, the sixth register, the seventh register, and the eighth register and loading an initial fifth number into the fifth register, loading an initial sixth number into the sixth register, loading an initial seventh number into the seventh register, and loading an initial eighth number into the eighth register, m) a third update circuit coupled to the fifth register and to the seventh register and repetitively updating the seventh number in response to the fifth number, and n) a forth update circuit coupled to the sixth register and to the eighth register and repetitively updating the eighth number in response to the sixth number; and wherein the first initial condition circuit is further coupled to the seventh register and to the eighth register and loading the seventh number into the third register as the initial third number and loading the eighth number into the forth register as the initial forth number. SUBSTITUTE SHEET. |
(5) MACHINE CONTROL SYSTEM OPERATING FROM REMOTE COMMANDS S/N 05/230,872 filed on March 1, 1972 and now Patent No. 4,531,182 issued on July 23, 1985: (6) COORDINATE ROTATION FOR MACHINE CONTROL SYSTEM S/N 05/232,459 filed on March 7, 1972 and now Patent No. 4,370,720 issued on January 25, 1983: (7) DIGITAL FEEDBACK CONTROL SYSTEM S/N 05/246,867 filed on April 24, 1972 and now Patent No. 4,310,878 issued on January 12, 1982: (8) COMPUTERIZED SYSTEM FOR OPERATOR INTERACTION S/N 05/288,247 filed on September 11, 1972 and now patent No. 4,121,284 issued on October 17, 1978: (9) A SYSTEM FOR INTERFACING A COMPUTER TO A MACHINE S/N 05/291,394 filed on September 22, 1972 and now Patent No. 4,396,976 issued on August 2, 1983: (10) DIGITAL ARRANGEMENT FOR PROCESSING SQUAREWAVE SIGNALS S/N 05/302,771 filed on November 1, 1972; still pending in the PTO: (1 1) APPARATUS AND METHOD FOR PROVIDING INTERACTIVE AUDIO COMMUNICATION S/N 05/325,933 filed on January 22, 1973 and now Patent No. 4,016,540 issued on April 5, 1977: (12) ELECTRONIC CALCULATOR SYSTEM HAVING AUDIO MESSAGES FOR OPERATOR INTERACTION S/N 05/325,941 filed on January 22, 1973 and now Patent No. 4,060,848 issued on November 29, 1 77: (13) ILLUMINATION CONTROL SYSTEM S/N 05/366,714 filed on June 4, 1973 and now Patent No. 3,986,022 issued on October 12, 1976: (14) DIGITAL SIGNAL PROCESSOR FOR SERVO VELOCITY CONTROL S/N 05/339,817 filed on March 9, 1973 and now Patent No. 4,034,276 issued on July 5, 1977: (15) MONOLITHIC DATA PROCESSOR WITH MEMORY REFRESH S/N 05/402,520 filed on October 1, 1973; now Patent No. 4,825,364 issued on April 25, 1989: (16) HOLOGRAPHIC SYSTEM FOR OBJECT LOCATION AND IDENTIFICATION S/N 05/490,816 filed on July 22, 1974 and now Patent No. 4,029,853 issued on June 24, 1980: (17) COMPUTERIZED MACHINE CONTROL SYSTEM S/N 05/476,743 filed on June 5, 1974 and now Patent No. 4,364,110 issued on December 14, 1982: (18) SIGNAL PROCESSING AND MEMORY ARRANGEMENT S/N 05/522,559 filed on November 1 1, 1974 and now Patent No. 4,209,852 issued
SUBSTITUTE SHEET
on June 24, 1980: (19) METHOD AND APPARATUS FOR SIGNAL ENHANCEMENT WITH IMPROVED DIGITAL FILTERING S/N 05/550,231 filed on February 14, 1975 and now Patent No. 4,209,843 issued on June 24, 1980: (20) ILLUMINATION SIGNAL PROCESSING SYSTEM S/N 05/727,330 filed on September 27, 1976; now abandoned: (21) PROJECTION TELEVISION SYSTEM USING LIQUID CRYSTAL DEVICES S/N 05/730,756 filed on October 7, 1976; now abandoned: (22) INCREMENTAL DIGITAL FILTER S/N 05/754,660 filed on December 27, 1976 and now patent No. 4,486,850 issued on December 4, 1984: (23) MEANS AND METHOD FOR COMPUTERIZED SOUND SYNTHESIS S/N 05/752,240 filed on December 20, 1976; now abandoned: (24) VOICE SIGNAL PROCESSING SYSTEM S/N 05/801,879 filed on May 13, 1977 and now patent No. 4,144,582 issued on March 13, 1979: (25) ANALOG READ ONLY MEMORY S/N 05/812,285 filed on July 1, 1977 and now Patent No. 4,371,953 issued on February 1, 1983: (26) DATA PROCESSOR ARCHITECTURE S/N 05/844,765 filed on October 25, 1977; now patent No. 4,523,290 issued on June 1 1 , 1985: (27) DIGITAL SOUND SYSTEM FOR CONSUMER PRODUCTS S/N 05/849,812 filed on November 9, 1977; now pending in the PTO: (28) ELECTRO-OPTICAL ILLUMINATION CONTROL SYSTEM S/N 05/860,278 filed on December 13, 1977 and now Patent No. 4,471,385 issued on September 1 1, 1984: (29) MEMORY SYSTEM HAVING SERVO COMPENSATION S/N 05/889,301 filed on March 23, 1978 and now Patent No. 4,322,819 issued on March 30, 1982: where this application is further a continuation in part of copending parent applications IMPROVED MEMORY ARCHITECTURE HAVING MULTI- DIMENSIONAL ADDRESSING S/N 06/661,649 filed on October 17, 1984 and now abandoned in favor of continuing applications; MICROCOMPUTER CONTROL OF MACHINES S/N 05/860,256 filed on December 14, 1977 and now Patent No. 4,829,419 issued on May 9, 1989; and MONOLITHIC DATA PROCESSOR WITH MEMORY REFRESH S/N 05/402,520 filed on October 1, 1973 now Patent No. 4,825,364 issued on April 25, 1989: where all of the above referenced patent applications are by Gilbert P. Hyatt; where the benefit of the filing dates of all of the above referenced applications are herein claimed in accordance with the United States Code such
as with 35 USC 120 and 35 USC 121; where all of the above listed patents and patent applications are incorporated herein by reference as if fully set forth at length herein; and where one skilled in the art will be able to combine the disclosures in said applications and patents that are incorporated by reference with the disclosure in the instant application from the disclosures therein and the disclosures herein.
BACKGROUND OF THE INVENTION FIELD OF THE INVENTION The field of the present invention is memory systems. PRIOR ART The prior art in memory systems includes integrated circuit, core, bubble, CCD, RAM and other types of memory systems. The most pertinent prior art is integrated circuit RAM systems. The prior art provides RAMs having tristate control for memory data lines to permit bussing of memory data lines and to facilitate bi-directional communication to the RAM for reading and writing of information from the bus. The most pertinent prior art in memory systems is discussed in the parent applications related to memories and is represented by the art cited herein.
SUMMARY OF THE INVENTION The present invention is generally directed to improved filter, display, and memory architecture. The filter architecture provides a simpler filter processor, such as with filtering on the fly and with single bit filter processing. The display architecture provides an improved filter display for displaying filtered images and for displaying graphics images. The memory architecture provides an improved memory for filter and display processing and for memory applications in general for greater performance and economy of implementation. In one memory configuration, a speed improvement is obtained by a combination of addressing the memory at a relatively low rate and scanning information out of the memory at a relatively high rate. This may be characterized as a multi-dimensional memory architecture, where the addressing logic forms a first dimension and the scanout logic forms a second dimension. This speed improvement can be implemented by using the memory tristate control logic for data scanout operations in conjunction with addressing logic to provide both, re-addressing and scanout of memory data. In accordance with a feature of the present invention, a sampled filtering
display system is provided. In accordance with another feature of the present invention, a filtering system having a display for an operator to determine when adequate filtering has been performed is provided. In accordance with another feature of the present invention, a filter display system having iterative filter processing for iteratively enhancing an image is provided. In accordance with another feature of the present invention, an improved sampled filter display system is provided. In accordance with another feature of the present invention, an improved sampled filter device is provided in the form of a correlator. A further feature of the present invention provides an improved display system. A still further feature of the present invention provides an improved filter processor for a display system. In accordance with still another feature of the present invention, a compositing-after-correlation display arrangement is provided. Yet another feature of the present invention provides a multi-channel filter display arrangement. A still further feature of the present invention provides for generation and processing of overlapping signature signals. Yet another feature of the present invention provides a filter memory arrangement. Yet another feature of the present invention provides an improved performance memory arrangement. Yet another feature of the present invention provides a closed loop memory arrangement. Yet another feature of the present invention provides an adaptive memory arrangement. Yet another feature of the present invention provides a memory detector arrangement. Yet another feature of the present invention provides a memory delay arrangement. Yet another feature of the present invention provides an improved DRAM arrangement. Yet another feature of the present invention provides an improved memory refresh arrangement. Yet another feature of the present invention provides an improved memory
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addressing arrangement. Yet another feature of the present invention provides an improved memory architecture. Yet another feature of the present invention provides an improved memory controller arrangement. The foregoing and other objects, features, and advantages of the present invention will become apparent from the following detailed description of preferred embodiments of this invention as illustrated in the accompanied drawings.
BRIEF DESCRIPTION OF THE DRAWINGS A better understanding of the present invention may be obtained from a consideration of the detailed description hereinafter taken in conjunction with the drawings, which are briefly described below. Fig 1 is a block diagram representation of an arrangement for implementing the system of the present invention. Fig 2 is a block diagram representation of an arrangement for implementing the addressing and architecture of the memory of the present invention. Fig 3 is a diagram of an address generator partitioned into an X-address component and a Y-address component. Figs 4A to 4S (herein referred to as Fig 4) comprise memory designs: where Fig 4A is a diagram of an address generator concatenating an X-address component and a Y-address component, Figs 4B and 4C are block diagram representations of memory addressing arrangements, Fig 4D is a block diagram and schematic representation of a memory overflow detector and comparitor detector arrangement. Fig 4E is a block diagram and schematic representation of a memory comparitor detector arrangement, Fig 4F is a block diagram of a two dimensional memory addressing arrangement, Fig 4G is a block diagram of a single dimensional memory addressing arrangement, Figs 4H to 4L are schematic diagrams of memory addressing arrangements, Figs 4M to 40 are schematic diagrams of memory detector arrangements. Fig 4P is a schematic diagram of a memory refresh arrangement, and Figs 4Q to 4T are schematic diagrams of multiple memory detector arrangements. Figs 5A to 5C (herein referred to as Fig 5) comprise spatial filtering arrangements: where Fig 5A is a block diagram representation of a spatial filter arrangement; Fig 5B is a block diagram representation of a sum-of-the-products arrangement that can be used with the arrangement of Fig 5A; and Fig 5C is a block diagram of a 3-channel sum-of-the-products arrangement.
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Figs 6A to 6X (herein referred to as Fig 6) comprise detailed designs: where Fig 6A is a block diagram representation of a system configuration for implementation of the present invention; Fig 6B is a detailed schematic diagram of clock steering logic; Fig 6C is a detailed schematic diagram of clock gating logic; Fig 6D is a detailed schematic diagram of control logic; Fig 6E is a block diagram of a configuration for implementing the memory of the present invention; Fig 6F is a detailed schematic representation of logic for addressing and scanning-out memory information in accordance with the memory of Fig 6E; Figs 6G to 6J are detailed block diagram representations in accordance with the memory of Fig 6E; Figs 6K to 6N are detailed schematic diagram representations in accordance with the memory of Figs 6F and Figs 6G to 6J; Figs 60 and 6P are detailed schematic diagram representations of one configuration of an address generator that can be used in the system of the present invention; Figs 6Q and 6R are detailed schematic diagram representations of another configuration of an address generator that can be used in the system of the present invention; Fig 6S is a detailed schematic diagram representation of a video DAC channel; Fig 6T is a detailed schematic diagram representation of a video synchronization pulse generator and clock pulse generator; Fig 6U is a detailed schematic diagram representation of joystick interface logic; Fig 6V is a detailed schematic diagram representation of joystick analog to digital converters, Fig 6W is an alternate detailed schematic diagram of clock gating logic shown in Fig 6C; and Fig 6X is a detailed schematic diagram of a one shot circuit. Figs 7A to 71 (herein referred to as Fig 7) comprise controller waveform and schematic diagrams: where Figs 7A to 7D are waveform diagrams of memory signals; Figs 7E to 7G are schematic diagrams of one memory controller configuration; and Figs 7H and 71 are waveform diagrams of memory RAS and CAS signals. To facilitate disclosure of the illustrated embodiments, the components shown in Figs 1 to 7 of the drawings have been assigned reference numerals and a description of such components is given in the following detailed description. The components in the figures have in general been assigned reference numerals, where the hundreds digit of each reference numeral corresponds to the figure number. For example, the components in Fig 1 have reference numerals between 100 and 199 and the components in Figure 2 have reference numerals between 200 and 299, except that a component appearing in successive drawing figures has maintained the first reference numeral.
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DETAILED DESCRIPTION OF THE INVENTION GRAPHICS PROCESSOR A graphics processor architecture can be implemented with a address generator and control logic generating graphics vectors for storing into image memory. Image memory can then be scanned out, such as in a raster scan form to refresh a display. In one configuration, graphics vectors can be written into image memory on an offline basis and can be used to refresh the display on an online basis. Alternately, graphics vectors can .be written into image memory on an online basis time shared with refreshing of the display on an online basis. One arrangement of the graphics system of the present invention is shown in Fig 1. Supervisory processor 115A loads graphics commands into address generators 115B. Address generators 115B generate addresses of graphics vectors for loading into image memory 115C and for raster scanning image memory 115C. The raster scan addresses scan-out the image in image memory 115C through the CRT interface 115D to refresh CRT 115E. An experimental system has been constructed to demonstrate operation of the graphics display capability. The arrangement shown in Fig 1 has been implemented in hardware for refreshing the display in real time. A program, such as the BASIC PROGRAM LISTING GRAPH.ASC, can be used to control that experimental hardware for refreshing the display. In this experimental system, the graphics vectors are loaded in an offline manner with the LD.ASC Basic program set forth in the BASIC PROGRAM LISTING LD.ASC herein; emulating hardware loading of graphics vectors in an online manner. In this experimental system, graphics operation is initiated each frame with supervisory processor 115A and hardware refresh is performed with address generators 115B and image memory 115C. In a hardware configuration, graphics vector generation can be performed in real time using the software emulated vector generation capability implemented in hardware form. In one hardware configuration, graphic vectors can be generated cotemporaneously with refresh, such as with one set of address generators (i.e., the XR-address generator and the YR-address generator shown in Figs 6Q and 6R) generating graphics vectors into image memory while a second set of address generators (i.e., the XP-address generator and the YP-address generator shown in Figs 60 and 6P) are generating the raster scan addresses for scanning-out image memory for display. In this configuration, image memory can be implemented as a dual-ported image memory for simultaneously loading vectors into image memory and scanning-out image memory. In an alternate hardware configuration, graphic vectors can be generated and loaded into image
memory during the vertical sync pulse period when the raster scan is blanked; time sharing the logic and memory between raster scanout and graphics generation. In this configuration, during the vertical sync period, the address generators can generate graphic vector addresses for loading the graphic vectors into image memory and, after the vertical sync period, the address generators can generate the raster scan addresses for scanning-out image memory for display. The address generators can be used to generate graphic vectors and windows. For example, the LD.ASC program set forth in the BASIC PROGRAM LISTING LD.ASC herein has been used to load graphic vectors into image memory. This is achieved by using the address generators to generate the addresses of a vector and by strobing the color intensity of the vector into image memory. Periods of time exist when the address generators are in a stand-by condition. For example, in a configuration where the address generators are scanning-out image memory to refresh a display; the address generators may not be used during the vertical blanking period and therefore may be available for graphic generation. Also, in a configuration where the address generators are not used • during the horizontal blanking period, the address generators and therefore may be available for graphic generation during the horizontal blanking period. For example, a vertical blanking period of 1 -millisecond will permit the address generators to draw about 5,000-graphic vector pixels operating at a 5-MHz pixel rate. Consequently, a meaningful number of graphic vector pixels can be generated during standby periods, permitting time sharing of the address generators for both, scanning-out an image to refresh a display and graphic vector generation. A vector memory can be implemented to store parameters associated with the vectors to be generated. Vector memory can be loaded from various sources, such as from the supervisory processor that initializes the address generators, from a host processor, or from other sources. The vector memory can contain the start point coordinates and the vector deltas for the address generators and a quantity parameter or distance-to-go (DTG) parameter related to the quantity of vector steps to be generated for the particular vector. During image processing standby periods, graphic vector parameters can be loaded from the vector memory for generating the vectors with the address generators, similar to that performed with the LD.ASC program. After various standby periods, such as the horizontal and vertical synchronization periods; the address generators can be reinitialized; thereby overcoming the need to buffer scanout parameters.
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However, if the address generators will not be reinitizalized following vector generation, it may be necessary to buffer the scanout address parameters in a buffer memory for reloading the pixel address generators after vector generation, In the LD.ASC program, the number of steps for a vector are counted under program control in the supervisory processor. In a hardwired implementation, the number of steps for a vector can be counted with a hardware counter circuit. For example, the quantity or DTG parameter from the vector memory can be loaded into a 74LS169 counter as a parallel load parameter and the counter can be decremented in the count-down mode for each pixel step during vector generation. Generation of the vector can be terminated by detecting the underflow signal from the counter at the zero count. Loading of the address generators from the vector memory can be performed in a manner similar to loading the address generators from the supervisory processor, as shown in the LD.ASC program listing herein and as discussed relative to the supervisory processor interface herein. Setting of the vector color intensity from the vector memory can be performed in a manner similar to setting of the vector color intensity from the supervisory processor in the LD.ASC program. Selecting of the write-mode for the image memory can be performed in a manner similar to setting of the write-mode with the load command signal DOA6 by the supervisory processor in the LD.ASC program. Window generation can be implemented with parameters for a plurality of images stored in a window buffer memory and selected as the address generators scan across window boundaries during scanout and refresh of the CRT monitor. When the address generators cross window boundaries, the previous display parameters can be buffered in the buffer memory and the display parameters associated with the new image can be loaded from the window buffer memory into the address generators. Loading of display parameters associated with the new image from the window buffer memory can be accomplished as discussed above for loading of vector parameters during graphic vector generation. Storing of display parameters associated with the prior image into the window buffer memory can be accomplished by reversing the vector generation loading operation to obtain a window generation store operation.
SPATIAL FILTERING Display systems can be implemented with spatial filters for anti-aliasing, pattern recognition, enhancement, and other purposes. A spatial filter arrangement will now be discussed with reference to Figs 5 A to 5C. Fig 5A shows an arrangement of a display system. Address generator 520A
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generates pixel addresses to access a plurality of pixels, such as a 9-pixel kernel 520H, from image memory 520B. Pixel information can be latched in registers to provide parallel pixel words or can be accessed sequentially as provided with the BASIC PROGRAM LISTING GRAPH.ASC herein. Weight table 520C supplies a plurality of kernel weights appropriate to spatial filtering of the pixel kernel, such as a kernel of 9-weights 5201, from weight table 520C. Weight information can be latched in registers or in the weight table to provide parallel pixel words or can be accessed sequentially as provided with the BASIC PROGRAM LISTING GRAPH.ASC herein. The pixel intensities 10 to 18 are each applied to a corresponding multiplier 520E and the weights W0 to W8 are each applied to a corresponding multiplier 520E for multiplying the corresponding intensity and weight together to generate product signals 520J. Product signals 520J are summed together with summer 520F to generated a weighted and mixed pixel intensity, which is converted to analog signal form with DAC 520G to excite a CRT display. The arrangement discussed with reference to Fig 5 A is representative of a single color channel, such a single channel of a multiple color pixel; i.e., a red, green, or blue channel; and such as a monochromatic single channel. Intensity information INT and weight information WT can be input to multipliers 521 A for weighting the pixel intensities, which in turn can be input to adders 521 B and 521 D for generating weighted and summed signal 521 D. Three channels of the arrangement discussed with reference to Fig 5B can be combined to provide a 3- channel color spatial filter. For example, as shown in Fig 5C, 3-channels of intensity and weight information 52 IE are processed with sum-of-the-products logic 521 F to generate 3-channels of signals 521 G; such as red, green, and blue signals 521 D. The sum-of-the-products processing discussed above can be implemented with commercially available integrated circuit components, such as multiplier chips and adder chips. For example, multiplier chips are manufactured by TRW and adder chips are manufactured by Texas Instruments.
MEMORY CONSIDERATIONS General The memory architecture of the present invention has important advantages in implementing digital systems. It is applicable to special purpose systems; such as display systems, array processors, and pipeline processors; and is applicable to general purpose systems; such as general purpose digital computers. It incorporates various features that may be used individually or in combinations to
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enhance performance and efficiency. One feature provides for accessing of memory at a relatively slow addressing rate and at a relatively fast scanout rate. Another feature provides a buffer memory to permit accessing of memory at a lower rate and higher duty cycle for information that is utilized at a higher rate and lower duty cycle. Various other features are also discussed herein. Memory speed is an important consideration for design of digital systems; such as display systems, array processing systems, and pipeline systems. A configuration is discussed herein where system speed can be implemented to be significantly faster than implied by memory speed considerations. This configuration uses a combination of novel architectural features for outputting of relatively high bandwidth information with a relatively low bandwidth memory. Memory arrangements have previously been disclosed in the related patent applications referenced herein in accordance with the present invention; such as implementing re-addressing and scanout operations to enhance memory capabilities. Various embodiments were disclosed; including filter configurations, display configurations, and general purpose computer configurations. Now, filter configurations; display configurations; and general purpose computer configurations, including microcomputer and microprocessor configurations will be further disclosed. Also, other configurations; such as television, array processor, signal processor, , cache memory, artificial intelligence, and DMA configurations; will be disclosed. These disclosures are intended to be illustrative of other configurations; such as other special purpose computer configurations and other general purpose computer configurations. Display, signal processing, and filter processing configurations may be considered to be special purpose computer configurations. Also; filter processors, speech processors, signal processors, and display processors may be considered to be array processors. Also; filter processors and speech processors may be considered to be signal processors. Further; filter processors include correlation processors, Fourier transform processors, recursive filter processors, and others. Correlation processors include convolution processors and Fourier processors include fast Fourier transform (FFT) and discrete Fourier transform (DFT) processors. Nevertheless, the teachings herein are generally applicable to processor systems and memory systems and are not limited to the specific applications disclosed herein. The terms computer and processor may be used interchangeably herein. Some of the features of the present invention may be characterized as adaptive memory control, closed loop memory control, and memory servo control. For example, the memory may be considered to adaptively adjust to
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address characteristics. Also, the memory system may be considered to be in a closed loop or a servo loop by controlling address generation in response to the generated address. In one configuration; a detector detects a characteristic of the address, such as a change in the address MSBs, and invokes a time delay to delay generation of the next address in response thereto. The various features of the present invention and alternate implementations and uses thereof are disclosed herein. Although many of the disclosures are applicable to multiple categories, they are often placed in only one section herein in order to reduce replication and for convenience of disclosure. Also, although the various features of the present invention are applicable to many implementations and uses, they are often disclosed with specific examples of implementation and use in order to reduce replication and for convenience of disclosure. Hence, it is herein intended that the various disclosures be used in combinations and permutations independent of the section or context in which they are contained and it is herein intended that the various disclosures have different uses and implementations that are not limited to the specific examples of implementation and uses provided therewith. Memory performance can be significantly increased in accordance with the features of the present invention, such as increased by nearly four-fold based upon currently available DRAMs. For example, the Toshiba TC514256P-10 fast page mode DRAM has a read cycle period of 190-ns (t^ - 190-ns) and a fast page mode period of 55-ns (tpc - 55-ns) for almost a four-fold improvement (190/55 - 3.45). See the MOS MEMORY PRODUCTS DATA BOOK; 1986- 1987; by Toshiba; such as at pages 119, 121, 123, and 125. This near four-fold improvement may be degraded by various considerations; such as the need for RAS cycles to be interspersed with CAS cycles, the need for refresh cycles to be interspersed with CAS cycles, other time delays (i.e., rise times and fall times) in the CAS cycles, optimizing synchronous timing based upon a finite resolution master clock pulse, and other considerations. However, a significant improvement approaching a four-fold improvement can be achieved with this Toshiba DRAM. Further, custom DRAMs that are specially configured for a memory architecture in accordance with the present invention may achieve improvements of greater than the above discussed near four-fold improvement. This near four-fold improvement may be enhanced by various considerations; such as reduced propagation delay for monolithic circuits on-the-chip and optimizing scanout circuitry on-the-chip for increased speed. The memory architectures previously disclosed in the related patent applications and as further disclosed herein provides the architeαure to facilitate this memory
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enhancement. Memory performance may be further increased in accordance with the memory refresh features of the present invention based upon currently available DRAMs. For example, detecting a time available period where memory refreshing can be performed without contention with processor memory operations and invoking memory refresh operations therein can increase memory performance over other methods, such as over cycle stealing methods. Many of the features of the present invention are related to control of a memory and control of a processor in response to an address. Many types of processors; such as general purpose processors, special purpose processors, display processors, television display processors, signal processors, array processors, database processors, filter processors, stored program processors, DMA processors, cache memory processors, artificial intelligence processors, etc.; and many types of memories; such as DRAMs, SRAMs, ROMs, CCD memories, magnetic bubble memories, core memories, magnetostrictive delay line memories, and other types of memories; can be implemented in accordance with features of the present invention. Microprocessors, display processors, and other processors disclosed herein are examples of other types of processors that can be utilized. Also; SRAMs, DRAMs, and other memories disclosed herein and in said related patent applications are examples of other types of memories that can be utilized. The features of the present invention are discussed in the context of RAMs. These RAM-related discussions can also be implemented for read only memories (ROMs); such as well known mask programmable ROMs, EROMs, and EEROMs. For example, ROMs can be constructed having output enable circuits for implementing external scanout, having RAS circuits for row addressing, and CAS circuits for column addressing; which circuits can be used to implement the scanout and re-addressing features of the present invention, such as using detectors and delaying circuits. An arrangement is disclosed herein for gating a clock (i.e., Figs 6C and 6D); such as to slow down memory operations for re-addressing and to speed up memory operations for scanout. Such clock gating arrangements can be used for disabling and delaying computer operations to facilitate use of the disclosed memory architecture. Other arrangements can also be used. For example, conventional computers have circuits for disabling or delaying operations, such as "wait state" circuits and "hold" circuits, which are appropriate for disabling and delaying computer operations to facilitate scanout and re-addressing. One objective of the present memory architecture is to use lower speed and
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lower cost memories (i.e., one-megabit DRAMs) in applications that need higher speed memories (i.e., 256K SRAMs and higher speed DRAMs) by controlling the lower speed memories to operate as if they were higher speed and higher cost memories. In a DRAM based configuration; it is often desirable for the processor to be able to intensively access information, for the memory refresh controller to refresh the memories, and for memory refreshing to take a minimum of time away from processing. The combination of a fast scanout arrangement and a memory refresh arrangement having a minimum of contention between memory refreshing and processing permits lower speed DRAMs to perform as if they were higher speed memories. Several arrangements are disclosed herein. The various features of the present invention can be used in combination with other features of the present invention or can be used independent of other features of the present invention. For example, memory refreshing features of the present invention can be used in combination with memory scanout and re- addressing features of the present invention. Alternately, memory refreshing features of the present invention can be used independent of memory scanout and re-addressing features of the present invention.
Various configurations of systems, memory architectures, memory circuits, detectors, etc. are discussed herein to illustrate different ways of practicing the present invention. Various system configurations can be provided in accordance with the present invention. Figs 4B and 4C show many of the elements of systems implemented in accordance with the present invention. Many of these elements are described together with reference to Figs 4B and 4C and may be described separately with reference to other figures. Because there are various ways to implement the features of the present invention and because there are various elements and methods taught in conjunction with the features of the present invention, it is herein intended that these elements be usable in various combinations theretogether and in various combinations with prior art elements and methods. For example, a memory architecture disclosed herein may have particular advantages when used with the CAS scanout and RAS re-addressing features of the present invention and may also have advantages when used with prior full cycle RAS and CAS addressing. Various configurations will now be discussed with reference to Figs 4B and 4C. Processor 216 controls address register 218 with control signals 217 to generate address signals 219 (i.e.. Figs 6A and 60 to 6R). In a display system,
processor 216 may include an arithmetic unit adding a delta parameter to an address parameter or to a position parameter stored in address register 218 for generating address 21 . In a television system, processor 216 may include a display processor adding a delta parameter to an address parameter or to a position parameter stored in address register 218 for generating address 219. In a computer system, processor 216 may include a program counter or address register incrementing an address or loading an address stored in address register 218 to address instructions or operands with address 21 . In an array processor system, processor 216 may include an array processor for processing array information, controlling address register 218 to address array information with address 219. In signal processor system, processor 216 may include a signal processor for processing signal information, controlling address register 218 to address signal information with address 219. In a database memory system, processor 216 may include a relational processor for comparing database information to locate desired information in the database and for controlling address register 218 to address database information with address 219. Address 219 stored in address register 218 is used to address memory 222; such as for accessing a pixel for display in a display system or for accessing an instruction or operand for use in a stored program computer. Address 219 stored in address register 218 can be further processed by detector 220, such as to detect a change in the MSBs of address 219 (i.e.; Figs 4D, 4F, 6C, and 6W). Memory 222 can be a single memory or can include a plurality of memories, such as memories 222A to 222B, and other circuits 222K (i.e.; Figs 4F to 4K and 6E to 6N). Detector 220 can be a single detector or can include a plurality of detectors, such as detectors 220A, 220B, 220C, and 220D for detecting different conditions of address 219 for controlling memory operations and processor operations. For example, if a change in the MSBs of the address is not detected, scanout operations can proceed for higher performance, and if a change in the MSBs of the address is detected, alternate operations can be commanded. Such alternate operations can include re- addressing memory 222, such as by generating a RAS memory cycle for controlling memory 222 in response to detector signal 221, and can include slowing down, disabling, or otherwise modifying operation of processor 216 in response to detector signal 221 to be consistent with the re-addressing or RAS cycle operation. Figs 4B and 4C are shown in different ways to illustrate different ways of portraying the system architecture. For example. Fig 4B shows detector signals 221 controlling processor 216, such as for invoking a delay, and controlling
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memory 222, such as for generating a RAS cycle and Fig 4C shows detector signals 221 controlling processor 216, such as for invoking a delay, without expressly showing detector signals controlling memory 222, such as for generating a RAS cycle. However, all details of implementation need not be shown in the more general block diagrams because they will become apparent when discussed in conjunction with the more detailed implementation diagrams. Fig 4C shows a configuration having a plurality of detectors 220C to 220D for invoking a plurality of different delays with detector signals 221C to 221 D. Different delays can be implemented for different addressing conditions; such as for invoking a first short delay for internal scanout operations, invoking a second longer delay for external scanout operations, and invoking a third even longer delay for re-addressing operations or such as for invoking a first short delay for operations in a first memory, invoking a second longer delay for operations in a second memory, and invoking a third even longer delay for operations in a third memory. Different memories, such as memories 222 A to 222 B generating memory output signals 223A to 223B respectively, and other circuits 222K generating signals 223C can be implemented in a multiple memory configuration. A very detailed example of one way to implement features of the present invention for a display system is discussed with reference to Figs 1 to 4, 5A to 5D, and 6A to 6X. The arrangement shown in Fig 4B corresponds to this detailed discussion of a display system and Fig 4C provides a variation to this detailed discussion of a display system. For example; processor 216 corresponds to the supervisory processor, the supervisory processor interface, and the sync pulse processing logic (i.e.; Figs 6A, 6B, and 6D and the discussions related thereto). Processor 216 controls address register 218 (i.e.; Figs 60, 6P, 6Q, and 6R and the discussions related thereto) with control signals 217 (i.e.; Figs 6B and 6D and the discussions related thereto) to generate address signals 219 (i.e.; Figs 6E, 6F, 60, 6P, 6Q, and 6R and the discussions related thereto). Address signals 219 (i.e.; Figs 6E, 6F, 60, 6P, 6Q, and 6R and the discussions related thereto) stored in address register 218 (i.e.; Figs 60, 6P, 6Q, and 6R and the discussions related thereto) is used to address memory 222 (i.e.; Figs 6E to 6N and the discussions related thereto) ; such as for accessing a pixel for display. Address signals 219 (i.e.; Figs 6E, 6F, 60, 6P, 6Q, and 6R and the discussions related thereto) stored in address register 218 (i.e.; Figs 60, 6P, 6Q, and 6R and the discussions related thereto) is further processed by detector 220 (i.e.; Fig 6C and the discussions related thereto) to detect a change in the MSBs of the address (i.e.; overflow signals Cl, C2, SN1, and SN2 in Fig 6C and the discussions
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related thereto). If a change in the MSBs of the address is not detected by the detector (i.e.; gate U13A-6 and flip-flop U23C-10 in Fig 6C and the discussions related thereto), scanout operations (i.e.; controlled by scanout clock U12A-8 in Figs 6B and 6Q can proceed for higher performance. If a change in the MSBs of the address is detected by the detector (i.e.; gate U13A-6 and flip-flop U23C-10 in Fig 6C and the discussions related thereto), alternate operations can be commanded. Such alternate operation can include re-addressing memory 222 with a RAS-type re-addressing operation (i.e.; controlled by re-addressing clock U12A-6 in Figs 6B and 6Q. The configuration shown in Fig 4B will now be discussed in greater detail in the context of the display system disclosed in Figs 1 to 4, 5A to 5D, and 6A to 6X. Processor 216 may include supervisory processor 61 OA and control logic 61 OB, address register 218 may include address generators 61 OC, memory 222 may include memory 61 OD, and detector 220 may be represented by the overflow circuitry in address generators 61 OC generating the overflow signal (Figs 4B, 4C, and 6A). The configuration shown in Fig 4B will now be discussed in the context of a television system, similar to the display system supra. Processor 216 may include supervisory processor 610A and control logic 610B, address register 218 may include address generators 61 OC, memory 222 may include memory 61 OD, and detector 220 may be represented by the overflow circuitry in address generators 61 OC generating the overflow signal (Figs 4B, 4C, and 6A). The configuration shown in Fig 4B will now be disclosed in the context of a stored program computer system. Processor 216 may be a microprocessor IC chip controlling address register 218 on the same IC chip lay incrementing address register 218 in accordance with program counter operations and by loading address register 218 in accordance with transfer operations. Memory 222 may be the computer main memory storing instructions to be accessed under control of address signal 219 for instruction execution by processor 216. Address 219 stored in address register 218 is further processed by detector 220 to detect a change in the MSBs of the address. If a change in the MSBs of the address is not detected, scanout operations can proceed for higher performance. If a change in the MSBs of the address is detected, alternate operation can be commanded. Such alternate operation can include re-addressing memory 222, such as by generating a RAS memory cycle for DRAMs under control of detector signal 221, and can include slowing down, disabling, or otherwise modifying operation of processor 216 to be consistent with the re-addressing or RAS cycle operation.
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The configuration shown in Fig 4B will now be disclosed in the context of an array processor system. Processor 216 may be an array processor advancing address register 218 in accordance with an array processor addressing algorithm, such as an FFT addressing algorithm or a correlation on the fly addressing algorithm. Memory 222 may be the array memory storing an array of information to be accessed under control of address signal 219 for array processing by processor 216. Address 219 stored in address register 218 is further processed by detector 220 to detect a change in the MSBs of the address. If a change in the MSBs of the address is not detected, scanout operations can proceed for higher performance. If a change in the MSBs of the address is detected, alternate operation can be commanded. Such alternate operation can include re-addressing memory 222, such as by generating a RAS memory cycle for DRAMs under control of detector signal 221, and can include slowing down, disabling, or otherwise modifying operation of array processor 216 to be consistent with the re-addressing or RAS cycle operation. The configuration shown in Fig 4B will now be disclosed in the context of a database memory system. Processor 216 may be a relational processor for relational database processing by advancing address register 218 in accordance with a database memory addressing algorithm. Memory 222 may be the database memory storing database information to be accessed under control of address signal 219 for relational processing by processor 216. Address 219 stored in address register 218 is further processed by detector 220 to detect a change in the MSBs of the address. If a change in the MSBs of the address is not detected, scanout operations can proceed for higher performance. If a change in the MSBs of the address is detected, alternate operation can be commanded. Such alternate operation can include re-addressing memory 222, such as by generating a RAS memory cycle for DRAMs under control of detector signal 221 , and can include slowing down, disabling, or otherwise modifying operation of relational processor 216 to be consistent with the re-addressing or RAS cycle operation. The configuration shown in Fig 4B will now be disclosed in the context of a signal processing system. Processor 216 may be a signal processor for signal processing by updating address register 218 in accordance with a signal processing addressing algorithm. Memory 222 may be the signal processing memory storing information for signal processing to be accessed under control of address signal 219 for signal processing by processor 216. Address 219 stored in address register 218 is further processed by detector 220 to detect a change in the MSBs of the address. If a change in the MSBs of the address is not detected,
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scanout operations can proceed for higher performance. If a change in the MSBs of the address is detected, alternate operation can be commanded. Such alternate operation can include re-addressing memory 222, such as by generating a RAS memory cycle for DRAMs under control of detector signal 221, and can include slowing down, disabling, or otherwise modifying operation of filter processor 216 to be consistent with the re-addressing or RAS cycle operation. The configuration shown in Fig 4B will now be disclosed in the context of a filter system. Processor 216 may be a filter processor for filter processing by updating address register 218 in accordance with a filter addressing algorithm. Memory 222 may be the filter memory storing information for filtering to be accessed under control of address signal 219 for filter processing by processor 216. Address 219 stored in address register 218 is further processed by detector 220 to detect a change in the MSBs of the address. If a change in the MSBs of the address is not detected, scanout operations can proceed for higher performance. If a change in the MSBs of the address is detected, alternate operation can be commanded. Such alternate operation can include re- addressing memory 222, such as by generating a RAS memory cycle for DRAMs under control of detector signal 221, and can include slowing down, disabling, or otherwise modifying operation of filter processor 216 to be consistent with the re-addressing or RAS cycle operation. The configuration shown in Fig 4B will now be disclosed in the context of an artificial intelligence system. Processor 216 may be an artificial intelligence processor for artificial intelligence processing, such as inference processing, by updating address register 218 in accordance with an artificial intelligence addressing algorithm. Memory 222 may be the artificial intelligence memory storing information for artificial intelligence processing to be accessed under control of address signal 219 for artificial intelligence processing by processor 216. Address 219 stored in address register 218 is further processed by detector 220 to detect a change in the MSBs of the address. If a change in the MSBs of the address is not detected, scanout operations can proceed for higher performance. If a change in the MSBs of the address is detected, alternate operation can be commanded. Such alternate operation can include re- addressing memory 222, such as by generating a RAS memory cycle for DRAMs under control of detector signal 221, and can include slowing down, disabling, or otherwise modifying operation of artificial intelligence processor 216 to be consistent with the re-addressing or RAS cycle operation. Various alternate memory configurations are discussed herein and in the
related patent applications. For example; SRAM, DRAM, CCD, magnetic bubble memory, and other memory configurations are disclosed in the related patent applications and are further disclosed herein. Configurations using Mitsubishi RAMs are disclosed herein, such as with reference to Figs 6E to 6N. These Mitsubishi RAM configurations implement column and row logic for MSB re-addressing and for LSB scanout, respectively. Toshiba DRAMs are configured with columns and rows, as with said Mitsubishi RAM configuration, but the columns and rows are reversed in designation. Hence, the Toshiba DRAM columns and rows correspond to the scanout and re- addressing respectively (Mitsubishi RAM rows and columns respectively) of the previously disclosed Fig 6E to 6N configuration. The memory architecture of the present invention, discussed with reference to Figs 6E to 6N using Mitsubishi RAMs, excites the memory IC chips simultaneously using the LSBs and MSBs of the memory address (i.e., Fig 6F). In the alternate DRAM configuration, it may be desirable to multiplex the MSBs (rows) and the LSBs (columns) under control of RAS and CAS strobes respectively (i.e., Figs 4H to 4K). Hence, in alternate configurations; it may be desirable to modify the clock gating logic to separate the re-addressing and scanout clocks to be RAS and CAS signals respectively. For example, the shorter period scanout clock U12A-8 and the longer period re-addressing clock U12A-6 (Fig 6C) are shown combined to generate a dual rate clock signal U21 D-8 (Fig 6Q for the Mitsubishi RAM configuration (i.e., Figs 6E to 6N). Alternately, the dual rate control signals can be maintained separate as a CAS signal (i.e., U12A-8) and a RAS signal (i.e., U12A-6) supra to strobe said alternate DRAM configuration and to control the address multiplexer. CCD memory configurations and magnetic bubble memory configurations have previously been disclosed in the related patent applications. These CCD memory configurations and magnetic bubble memory configurations are disclosed implementing improved access circuits, such as with multiple recirculation paths; implementing various types of refreshing, such as adaptive refreshing; and implementing various other memory inventive features.
Brief Description A memory architecture in accordance with the present invention will now be discussed with reference to Figs 1 and 2. Alternate configurations can be provided to implement the system of the present invention. However, this configuration is exemplary of the system of the present invention. Input device 115A generates input information under control of input clock 115G. Address
generator 115B generates addresses for memory 115C under control of input clock 115G, such as for storing information from input device 115A in memory 115C or for accessing information from memory 115C under control of input device 115A. Memory 115C outputs information accessed with address generator 115B under control of input clock 115G. Buffer 115D receives information accessed from memory 115C for buffering therein under control of input clock 115G and generates information buffered therein under control of output clock 115F. Output device 115E, such as a display monitor, receives buffered information from buffer 115D under control of output clock 115F. This permits information to be accessed from memory 115C asynchronous with information to be output to output device 115E. Hence, buffer 115D can input information under control of input clock 115G and can output information under control of output clock 115F for resynchronizing of information flow, averaging of information rate, reorganizing of information into groups, and for other purposes. In an alternate configuration, information from memory 115C can be output directly to output device 115E under control of input clock 115G, such as with input clock 115G and output clock 115F being the same clock and being connected theretogether. A multi-dimensional address configuration is shown in Fig 2. Address generator 115B generates an address word having a re-addressing portion 215E, a Y-scanout portion, 215G, and an X-scanout portion 215F. This arrangement has particular advantages because the X-scanout signal 215F and the Y-scanout signal 215G can be generated more rapidly than re-addressing signal 215E to access or to write into memory 115C. Memory 115C is shown partitioned onto 2-boards 215B and 215D. RAMs on the 2-boards can be addressed with re-addressing logic 215E. The RAMs are shown organized in an X-Y array of rows and columns. The X-scanout signals are decoded into a plurality of row signals shown radiating horizontally right from the X-scanout line 115F. The Y-scanout signals are decoded into a plurality of column signals shown radiating vertically up from the Y-scanout line 115G. The decoded row and column line signals enabled 1-row and 1 -column as a function of the X-scanout and Y-scanout address portions, respectively. Consequently, 1- RAM at the intersection of the row and column enable signals is enabled to output the information addressed with re-addressing signal 215E and all other RAMs are disabled from outputting the information addressed with re-addressing signal 215E. Various address register configurations will now be discussed with reference
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to Figs 3 and 4. Fig 3 shows a dual address register configuration having an X- address register and a Y-address register. This arrangement is particularly applicable to display systems having a 2-dimensional memory map and generating vectors for storing into an image memory or for reading out of an image memory. The X-address register and the Y-address register can be separately controlled to generate a 2-dimensional vector for accessing a pixel in the memory. Actually, the 2-address registers can be considered to be concatenated to form a single address parameter for memory accessing. However, two separate 2-dimensional address registers are a convenient way of visualizing a single dimensional memory configured into a 2-dimensional memory map. In a configuration discussed for the experimental system herein, the 6-most significant bits of each register are combined for an 11 -bit re- addressing word and a 1-bit board select signal while the 3-least significant bits of each register are separately decoded to select one of 8-rows and one of 8- columns on each board in accordance with the X-scanout signal 215F and Y- scanout signal 215G discussed with reference to Fig 3. Fig 4A shows a single address register configuration, which can be implemented by concatenating the X-register and Y-register shown in Fig 3 or, alternately, may be conceptually defined as a single register, a quadruple register, or other configurations. Selected bits of this single address register may be used to control re-addressing and row and column select for the memory in accordance with Fig 2. Many configurations of signal groupings can be implemented; such as using signals XAO, XA1, XA4, XA6, YA3, YA4, and YA6 for re-addressing; signals XA3, XA7, YA5, and YA8 for X-scanout decoding; and signals YAO, YA1, YA2, XA2, XA5, XA8, and YA7 for Y-scanout decoding as an alternate to the above configuration discussed with reference to Fig 3. Memory addressing may be configured in a multi-dimensional form; such as 2-dimensional, 3-dimensional, or 4-dimensional form. For example, address generation may be performed with a plurality of different address generators; such as an X-address generator for one portion of a 2-dimensional address and a Y-address generator for the other portion of a 2-dimensional address, as discussed for a 2-dimensional memory map configuration herein. Also, addresses that are generated with a single address generator can be partitioned into multi- dimensional addresses; such as a 16-bit computer instruction address being partitioned into a W-dimension address for the most significant 4-bits, an X- dimension address for the next less significant 4-bits, a Y-dimension address for the next less significant 4-bits, and a Z-dimension address for the least significant 4-bits. Also, a multi-dimensional address, such as the X-dimensional address and
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Y-dimensional address for a display configuration, can be concatenated into a single address by combining the different portions thereof; such as combining the Y-address dimension as the most significant portion of the address word and the X-address dimension as the least significant portion of the address word. In describing the novel architecture of the memory of the present invention, the word "dimension" and words relating thereto have been adapted to mean the different forms of addressing the RAMs. For example, the RAMs are addressed with a re-addressing portion of the address and a scanout portion of the address, which may be considered to be 2-dimensional addressing, and the scanout portion of the address are divided into row select signals to the G-bar pins and column select signals to the S-bar pins of the RAMs, which may be considered to be 2-dimensional scanout addressing. A memory having an address with the combination of a 1 -dimensional re-addressing portion and a 2- dimensional scanout portion may be considered to be a 3-dimensional memory. This terminology is different from terminology associated with 2-spatial dimensions of an image, such as implemented in a memory map, and 2-spatial dimensions of an image, such as displayed on a monitor. The memory arrangement discussed herein can be applied to a display system, as discussed in greater detail herein. Image pixels can be accessed in sequence for output to a display monitor. The memory can be configured in a 2- dimensional form, such as 1 -dimension being the data block address and the other dimension being the pixel address within a block. Alternately, the address can be partitioned into a plurality of bytes from a least significant byte to a most significant byte and each byte can be used to address a different dimension of the memory. Image memory scanout can be implemented by scanning sequential addresses at a higher rate and by re-addressing the memory at a lower rate, such as with a gated clock. A gating signal can be used to gate the memory access clock without gating the output clock, such as a DAC clock; permitting display operations to proceed under control of the non-gated output clock without being affected by gating of the memory clock. An output buffer memory can be used to temporarily store pixel information to reduce sensitivity of the display to gating of the memory clock. A buffer memory also permits accessing of the image memory at a relatively high duty cycle even though the information may be output to the display at a lower duty cycle, or at a relatively low portion of the time that the memory information is available, or by not utilizing the information immediately after the information becomes available from the image memory. A buffer memory also permits accessing of image memory substantially as fast as image memory can be accessed, reducing
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constraint from output speed considerations. The memory arrangement discussed herein can also be applied to a correlator processor memory. Data can be accessed in sequence for execution by the correlator. The memory can be configured in a 2-dimensional form, such as 1- dimension being the data block address and the other dimension being the data address within a block. Alternately, the address can be partitioned into a plurality of bytes from a least significant byte to a most significant byte and each byte can be used to address a different dimension of the memory. Data scanout can be implemented by scanning sequential addresses at a higher rate and by re- addressing the memory at a lower rate, such as with a gated clock. A gating signal can be used to gate the memory access clock without gating the output clock, permitting correlator operations to proceed under control of the non- gated output clock without being effected by gating of the memory clock. A buffer memory can be used to temporarily store correlation information to reduce sensitivity of the correlator to gating of the memory clock. A buffer memory also permits accessing of the correlator data at a relatively high duty cycle even though the information may be processed at a lower duty cycle, or at a relatively low portion of the time that the memory information is available, or by not utilizing the information immediately after the information becomes available. A buffer memory also permits accessing of correlator data substantially as fast as the data memory can be accessed, reducing constraints from output speed considerations. The memory arrangement discussed herein can also be applied to an FFT processor memory. Data can be accessed in sequence for execution by the FFT processor. The memory can be configured in a 2-dimensional form, such as 1- dimension being the data block address and the other dimension being the data address within a block. Alternately, the address can be partitioned into a plurality of bytes from a least significant byte to a most significant byte and each byte can be used to address a different dimension of the memory. Data scanout can be implemented by scanning sequential addresses at a higher rate and by re- addressing the memory at a lower rate, such as with a gated clock. A gating signal can be used to gate the memory access clock without gating the output clock, permitting FFT operations to proceed under control of the non-gated output clock without being effected by gating of the memory clock. A buffer memory can be used to temporarily store FFT information to reduce sensitivity of the FFT processor to gating of the memory clock. A buffer memory also permits accessing of the FFT data at a relatively high duty cycle even though the information may be processed at a lower duty cycle, or at a relatively low
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portion of the time that the memory information is available, or by not utilizing the information immediately after the information becomes available. A buffer memory also permits accessing of FFT data substantially as fast as the data memory can be accessed, reducing constraints from output speed considerations. The memory arrangement discussed herein can also be applied to general purpose computer memory. Instructions can be accessed in sequence for execution by the computer arithmetic and control logic. The memory can be configured in a 2-dimeπsional form, such as 1 -dimension being the instruction or data block address and the other dimension being the instruction or data address within a block. Alternately, the address can be partitioned into a plurality of bytes from a least significant byte to a most significant byte and each byte can be used to address a different dimension of the memory. Instruction and data scanout can be implemented by scanning sequential addresses at a higher rate and by re-addressing the memory at a lower rate, such as with a gated clock. A gating signal can be used to gate the memory access clock without gating the output clock, permitting processing to proceed under control of the non-gated output clock without being effected by gating of the memory clock. A buffer memory can be used to temporarily store computer instructions and data to reduce sensitivity of the computer to gating of the memory clock. A buffer memory also permits accessing of the computer instructions and data at a relatively high duty cycle even though the information may be processed at a lower duty cycle, or at a relatively low portion of the time that the memory information is available, or by not utilizing the information immediately after the information becomes available. A buffer memory also permits accessing of computer instructions and data substantially as fast as the memory can be accessed, reducing constraints from output speed considerations. Memory architectural features pertaining to high speed scanout in conjunction with re-addressing can provide speed enhancement, such as a 3-fold improvement in speed. These feature are particularly pertinent to RAMs having multiple tristate control signals; such as the Mitsubishi Electric M58725P RAMs. RAMs having a single tristate control signal can also be used with this configuration, but may involve additional decoder logic to decode scanout address signals, such as with linear select architecture consistent with a single tristate control signal. The memory architecture of the present invention may be discussed in the content of a display application for purposes of illustration. However, this memory architecture is applicable to computer main memories, buffer
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memories, signal processing memories, and other memory applications in addition to display memories.
Re-Addressing And Scanout Memory Architecture Multiple dimension image memory architecture, as previously discussed, involves simultaneous accessing of multiple pixels, such as in a 2-dimensional X Y array, to increase effective memory speed. Such a configuration is appropriate for a 2-dimensional horizontal and vertical scanout for refreshing a display monitor and is also appropriate for other applications; such as general purpose computers and special purpose processors. Such a memory architecture may need buffer registers for temporary storage of accessed information, such as for temporary storage of accessed pixels so that a new memory access cycle may be initiated while the previously accessed pixels are being output to refresh the display monitor. An alternate configuration is discussed herein where a block of pixels is simultaneously accessed and is scanned-out without the need for buffer registers or overlapping memory accesses. This configuration can involve a multiple access period, where stored information is scanned out from an accessed block at high rate (shorter period) and a new block of stored information is accessed at a lower rate (lower period). A buffer memory, such as a FIFO or a double buffer memory, can be used to equalize these rate and period differences. A novel memory architecture will now be discussed which enhances memory speed and economy. This architecture can be characterized as a multi- dimensional memory architecture that is divided into 2-address portions, a high speed address portion and a slow speed address portion. Another characteristic is a combination scanout and re-addressing architeαure. Another charaαerization is use of tristate memory control logic to reduce the need for buffer registers and multiplexing logic. This can be accomplished by taking advantage of certain features of RAMs. Conventional RAMs have a plurality of input address lines for addressing stored information, tristate output data direαion control logic for seleαing data input for writing and data output for reading, and tristate chip seleα logic for gating output information onto a bus. Use of these circuit features in a novel form implemented in the memory architeαure described herein provides important advantages. For example, tristate data input and output control logic can be used in conjunαion with tristate chip seleα logic to provide a high speed 2-dimensional scanout for rapid accessing of RAMs. The 2-dimensional scanout arrangement reduces auxiliary decoding and seleαion logic, reduces output
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buffer logic, is compatible with 2-dimensional memory map architertures, and facilitates relatively high speed operation with relatively low speed RAMs. Higher speed scanout can be used in conjunαion with slower speed addressing of the RAMs to provide an average access rate that is significantly higher than the addressing rate. For example, the Mitsubishi Eleαric M58725P RAMs have a 200-ns address period and a 100-ns scanout period. Assuming that a system will scanout 4-parameters before re-addressing is necessary and assuming that re-addressing is implemented with 3-scanout clock periods, 5- parameters can be accessed in 7-clock periods; 4-parameters times 1 -clock period per parameter plus 1 -parameter times 3-clock periods per parameter; in comparison to conventional re-addressing, where 5-parameters can be accessed in 15-clock periods (5-parameters times 3-clock periods/parameter). This scanout and re-addressing example yields an average of 1.4-clock periods per pixel for the scanout and re-addressing configuration compared to 3-clock periods per pixel for the re-addressing configuration, yielding an improvement of about 2- times in speed for this example. RAMs are conventionally addressed with a number of address lines, such as 11 -address lines for a 2,048 word RAM. Address signals typically propagate through the memory array and consequently can have relatively long propagation delays. RAMs conventionally have tristate enable signals to permit bussing of output signals and to seleα data input for storing and data output for accessing of data. The tristate enable signals can be used to gate the RAM outputs and consequently can have relatively short propagation delays. The present multi-dimensional memory configuration uses less frequent accessing of data with the slower address signals (re-addressingTand uses more frequent accessing of data with the faster scanout control signals. Therefore, the average propagation delay is reduced, being a weighted average of several shorter scanout propagation delays and a single longer address propagation delay. Speed is enhanced by changing the clock period to be a funαion of the addressing operation, such as a longer clock period for re-addressing and a shorter clock period for scanout. A buffer memory; such as a FIFO, double buffer, cache, or scratchpad memory; can be used to buffer output information from the memory for providing a constant memory output clock period in response to the variable memory input clock period. A specific example will now be provided to illustrate use of relatively longer propagation delay address signals to seleα a single block of 64-pixels and using relatively shorter propagation delay tristate control signals to seleα a pixel from
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the seleαed block. Each address generator generates a concatenated address having a 3-bit tristate control signal portion and a 6-bit address signal portion. The 3-bit tristate control signal address can be implemented with the least significant bits (LSBs) of the address word and the 6-address bits can be implemented with the most significant bits (MSBs) of the address word. The address generators can be implemented to update the address, where the LSBs can be updated more frequently than the MSBs and where the addresses can scan through a block of pixels as the LSBs are updated and change to a different block of pixels when the MSBs are updated. Updating of the MSBs can be deteαed with an overflow from the LSBs to the MSBs in the address generator. Therefore, the LSBs can be updated relatively rapidly to scanout with the faster tristate control signals through the pixels within a block and the MSBs can be updated relatively slowly to change the seleαed block. For purposes of illustration, an experimental configuration with an image memory having 262,144-pixels arranged in a 512-by-512 pixel memory map was implemented. Also for simplicity, Mitsubishi 58725P RAMs, Texas Instruments 7400 series TTL logic, and Intel logic is used. The Mitsubishi RAMs have 2K-words by 8-bits per word. Therefore, 128-RAMs are used to provide 262, 144-pixels. For efficiency of implementation, the RAMs are arranged in two 2-dimensional boards each having a binary quantity (i.e., 8) RAMs for each dimension. Consequently, the 128-RAMs are arranged on 2-boards each having 64-RAMs, arranged in an 8-by-8 block of RAMs per board. Each RAM has an 11-bit address for accessing one of 2048-words. Another address bit is used in this configuration for seleαing one of the two RAM boards. For convenience of discussion, the 11-bit address and the 1-bit board seleα signals are organized in a 6-bit X-address dimension and a 6-bit Y-address dimension to seleα one block of 64-pixels out of 4096 blocks of 64-pixels. This arrangement is shown in the memory diagrams and tables included herewith. The memory map contains a 64-by-64 array of blocks for a total of 4096 blocks. The 12-address bits are organized into a 6-bit Y-axis address and a 6-bit X-axis address for a 64-by-64 array of blocks. The 6-bit X-axis address is divided into a 5-bit X-axis address to each RAM and a 6th X-axis address bit to seleα one of the two 64-RAM boards. Use of the X-address bit as a board seleα bit causes the 64- by-64 array of RAMs to have alternate X-dimensional columns to be seleαed from different boards. Alternately, use of the most significant X-address bit for the board seleα bit would cause the 64-by-64 array of RAMs to have all of the X- dimensional RAMs in one board adjacent to each other and all of the X- dimensional RAMs in the other board adjacent to each other.
Each of the 4096-blocks of pixels can be configured in an 8-by-8 array of 64- pixels. One of the 8-by-8 arrays of 64-pixels is shown in the image memory diagrams and tables included herewith. The 8-by-8 array can be addressed with a 2-dimensional 3-bit by 3-bit address organized in a 3-bit X-address and a 3-bit Y-address format. Each of the two 3-bit address portions can be decoded into 8- address lines, yielding an 8-by-8 array of address lines. If one of the first group of 8-address lines is excited to seleα a row of pixels and the second group of 8- address lines is excited to seleα a column of pixels, then the one pixel at the interseαion of the row address line and column address line is seleαed out of the 64-ρixels per block. The memory scanout and re-addressing architeαure can be implemented for cutting across image memory lines to generate a veαor drawn at an angle to the raster lines and can be efficiently used in a raster scan image memory. For example, raster scan outputs proceed on a line-by-line basis; consistent with the line organization of the image memory. In such an arrangement, a single tri-state control signal can be used for scanout as the line progresses, with re-addressing being performed at block boundaries. In this configuration, a block may be a 1- dimensional line of pixels; in contrast to the above described 2-dimensional array of pixels per block. Block traversing in a 1 -dimensional memory system is more nearly constant than in a multi-dimensional memory system. For example, a linear block along a scanline can have all pixels in the block accessed frame- after-frame independent of veαor considerations. This may be different from a system having a 2-dimensional scanout block with veαors because a 2- dimensional scanout block may have different numbers of pixels traversed within a block as a funαion of the veαor parameters. For example, the number of pixels traversed may be a funαion of the pixel entry point to the block and a funαion of the scanout veαor angle through the block, where the pixel entry point may be a funαion of veαor position and the scanout angle may be a funαioπ of veαor slope. The maximum, typical, average, and minimum number of pixels scanned in a block can be different for different configurations. For example, in a raster scan arrangement; all pixels in a block may be scanned for each traverse of the linear block. Therefore, in a 1 -dimensional block configuration; the maximum, typical, average, and minimum number of pixels scanned in a block may be the same; which is the total number of pixels per block. In a 2-dimensional block configuration having veαor direαions, the maximum number of pixels may be the number of pixels along the diagonal of the block; the minimum number of pixels may be a single pixel, such as a scan clipping the corner of a block; and
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the typical number and average number may be inbetween the maximum and minimum, such as determined by typical and average block geometry relationships. Consequently, in a linear block raster scanout configuration, greater average scanout rates may be obtained due to the scanout of more pixels per block. A buffer memory configuration can have the form of a multiple buffer, such as a double buffer. Alternately, the memory configuration discussed herein having gated clocks and a plurality of clock periods can be implemented with a smaller buffer memory to average a plurality of clock periods. For example, a 16-word FIFO can be used for loading at an input word rate under control of the gated clock pulse having a plurality of clock periods and for unloading at a clock rate consistent with the output word rate. The FIFO may be implemented with the S/N 74LS222, S/N 74LS224, or S/N 74S225 circuits which provide 16- words having 4-bits or 5-bits. These FIFOs can be configured in parallel to provide the 8-bits per word, as shown for the experimental configuration, or can provide other word sizes.
Memory Enhancement The output of memory in the experimental configuration can be implemented to propagate down a datapipe to a buffer memory without communication with the front end control logic and address generators. Therefore, it can be considered to be implemented in a pipeline form. This pipeline permits introducing clock skew, where the clock to the output data pipe can be skewed ahead of the clock to the input at the data pipe. This permits greater speed in view of propagation delay considerations. For example, in the experimental configuration, the output registers are clocked with the 180-degree-phase clock and, consequently, provide a 1.5-clock period for propagation delay. One design consideration for this configuration is that propagation delay through the memory is less than 1/2-clock period or the newer high speed information from the next clock may be clocked into the datapipe with the 1.5-clock period clock.
Memory Map Display Architeαure An architeαure of one form of memory map for a display will now be discussed. This memory map stores an image as a 2-dimensional array of pixels. In a monochromatic configuration, each pixel contains 1 -intensity parameter. In a color configuration, each pixel contains 3-intensity parameters; red, blue, and green intensity parameters. Additional information can be contained in a pixel word; such as other parameters, flags, and control information. All information
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for a particular pixel can be packed together in a pixel word. Accessing of a pixel word can be implemented to access all information pertaining to the particular pixel word with one access or, alternately, can access portions of the pixel word for each of multiple accesses per pixel word. For simplicity of discussion herein, operations on a pixel word may be discussed as operations on a pixel. Memory map configurations having 1 -dimensional and multi-dimensional architeαures have been discussed. Multi-dimensional architeαures provide enhanced performance and flexibility, such as by accessing multiple pixels simultaneously. Multi-dimensional architeαure provides important advantages. It provides high speed, because of the addressing of 64-pixels in parallel and because the tristate seieα signals have shorter propagation delays than the address signals. It provides flexibility, because the tristate seleα signals can traverse the 64-pixel block at any veαor angle and through any continuous sequence of pixels. It provides circuit efficiency because much of the address decode and tristate logic is implemented on the memory chips, because a multi-dimensional addressing arrangement is more efficient than a 1 -dimensional addressing arrangement, and because the tristate logic reduces the need for output registers. A configuration for simultaneous accessing of an 8-by-8 2-dimensional array of 64-pixels is shown in Figs 6E to 6N. A pixel address selects 64-pixels at a time out of the total array of pixels, such as out of 262,144-pixels in a 512-pixel by 512-pixel array. A subset of the 64-pixel block is then addressed with tristate enable signals, such as chip seleα and output seleα signals. Tristate seleα signals can be used to scan through a 64-pixel block to seleα a sequence of pixels therefrom. The experimental configuration has been construαed having a 512-pixel by 512-pixel memory map. For convenience of experimentation, static 16K-RAM chips are used for memory map implementation. Typical circuits are the TMS- 4016 RAM from Texas Instruments Inc. and the M58725P static RAM from Mitsubishi Eleαric. These circuits are configured in the form of a 2K-word by 8- bit static RAM having an 11-bit address, a tristate chip seleα, and a tristate output enable. Conventionally, the chip seleα and output enable are used to provide output bussing and to reduce the need for an output register. In the present configuration, the chip seleα and output enable signals are used to provide 2-additional dimensions of memory addressing. For example, the 11- address lines are used to seleα a block of 64-pixels out of 262,144-pixels; the chip seleα signal is used to seleα a column of 8-pixels out of the seleαed block
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of 64-pixels; and the output enable signal is used to seleα a row of 8-pixels out of the seleαed block of 64-pixels. The seleαion of a column of 8-pixels and a row of 8-pixels with the chip seleα signal and the output enable signal selects a single pixel at the interseαion of that column and row from the seleαed block of 64-pixels. Consequently, a 3-dimensional architeαure having address seleαion of a 64-pixel block, chip seleαion of an 8-pixel column in that block, and output enable seleαion of an 8-pixel row in that block uniquely selects a single pixel out of 262, 144-pixels. Memory chips have particular charaαeristics that can be adapted to memory architeαures which are particularly appropriate for the systems discussed herein. For example, memory circuits conventionally have address lines and tristate seleα lines. The address lines are typically used to seleα a pixel per chip and the tristate seleα lines are typically used to disconneα undesired chips from the output bus and to reverse data direαion for read and write operations. However, use of the address lines to seleα a block of pixels and use of the tristate seleα lines to scan through the block of pixels provides particular advantages. The access time from the address seleα is significantly greater than the access time from the chip seleα or the output enable seleα. Therefore, accessing with the chip seleα and output enable signals can proceed at a significantly faster rate than accessing with the address seleα. The address seleα lines can be excited with the most significant bits (MSBs) of the X-address and Y-address generated with the address generators. The chip seleα and output enable signals can be excited with the decoded least significant bits (LSBs) of the X-address and Y-address generated with the address generators. For a 512-pixel by 512-pixel memory map having block of 64- pixels, the 6-MSBs of the Y-address and the 6-MSBs of the X-address can be combined into a 12-bit address to seleα one of 4096 blocks of 64-pixels. The 3- LSBs of the Y-address and the 3-LSBs of the X-address can be used to seleα one of 8-rows and one of 8 columns, respeαively. As the address generation proceeds within a block of pixels, the address proceeds along a line at the appropriate veαor angle through the block as the 3-LSBs of the X-address and the 3-LSBs of the Y-address are updated. When the address update progresses into the MSBs of either the X-address or Y-address, such as with an overflow; a new block of pixels is accessed and the address generation then proceeds within this new block of pixels along a line at the appropriate angle through the block. The time period for memory accessing of a new block of pixels can be implemented to be longer than the time period for scanning pixels within a previously accessed block of pixels. This can be provided by scanning the pixels
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within a block at a higher rate and then accessing a new block at a lower rate. This can be implemented by using a higher clock rate to scan pixels within a block, to deteα an overflow condition in the X-address and Y-address generators from the LSBs to the MSBs as being indicative of the need to access a new block of pixels, and to switch over to a lower clock rate for accessing of the new block of pixels. The arrangement discussed with reference to Figs 6E to 6N illustrates 64-RAM chips in an 8-by-8 array of chips. Two of these 8x8 arrays of chips are used for a 512-pixel by 512-pixel memory map that is implemented in 64-pixel blocks with 2K-by-8 static RAMs. Each 2K-block array of pixels is seleαed with 11 -bits of the 12-bit address. The particular one of the two 64-chip boards is seleαed with the remaining bit of the 12-bit address. This is shown with the 5-bits from the X- address and the 6-bits from the Y-address being bussed to all 128-chips of both boards and with 1-bit of the X-address being used to seleα one of the 2-boards in the uncomplemented state and the other of the 2-boards in the complemented state. The row seleα and the column seleα are each implemented by decoding 3-bits with a decoder to generate one of 8-signals to seleα one of 8-rows and one of 8-columns, respeαively. The 11 -address lines are bussed to the address input lines of each RAM chip. The 8-data lines are bussed from the data output lines of each RAM chip. Each column seleα line is bussed to all 8-chips in the related column for each of the two blocks. Each row seleα line is bussed to all 8- chips in the related row for each of the 2-boards. Consequently, the 11 -address lines seleα 2-boards of 64-chips each, the twelfth address line selects one of 2- boards, and the 6 "scanout" lines seleα one of 64-pixels per board.
Image Memory An image memory for a display in accordance with the present invention can take various forms; such as being implemented with static RAMs, dynamic RAMs, CCDs, ROMs, and other memory devices. The memory architeαure can be a random access, sequential access, block access, or other form of architeαure. The image memory can be implemented in an unbuffered form, or in a buffered form; such as with a double buffer, in conjunαion with various line buffers, and in conjunαion with frame buffers. These various alternatives can be adapted to operate with the present invention based upon the teachings herein showing a detailed design of a RAM image memory using static RAMs and accessed in a block oriented scanout arrangement. This configuration will now be discussed in detail with reference to Figs 6E to 6N. Address generators for use with the memory arrangement shown in Figs 6E to
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6N are discussed with reference to Figs 60 to 6R. The address generators can generate sequential addresses at the appropriate vector angle through image memory. Multiple RAM chips, in this example all RAM chips, are addressed with the more significant bits of the same address word for simultaneously accessing the corresponding word in each of the multiple RAM chips. The less significant bits of the address word are used to seleα which of the chips is to be enabled for outputting onto the output bus. The chip enable control is a higher speed control and hence permits higher speed memory operations when scanning out within a memory block and the chip address control is a lower speed control and hence involves lower speed memory operations when re- addressing. Therefore, two types of addressing will be described with reference to Figs 6E to 6N, which are re-addressing with the more significant address bits and scanout with the less significant address bits. Re-addressing is performed with fanout buffers U19A for the Y-address bits and U19D for the X-address bits. These buffers generate the drive current necessary to fanout to a large number of RAM chips. In this configuration, 64- RAM chips are grouped on each of two image memory boards with each board having replicated buffers to facilitate increased speed and modularity. The buffer outputs are applied to the address inputs of the RAM chips. During scanout, the addresses are maintained constant. During re-addressing, the addresses are changed. Scanout is performed with decoders U19B, U19C, and U19E. The less significant address bits are applied to these decoders and decoded into X-address and Y-address signals. The X-address signals seleα rows of RAM chips and the Y- address signals seleα columns of RAM chips in a 2-dimensional configuration on each board. Replicating memory address logic on each board facilitates increased speed and modularity. Each row and each column is composed of 8- RAM chips for an 8-by-8 array of RAM chips per board. The Y-axis decoder UI 9B is addressed with the less significant Y-address bits YAO, YA1, and YA2 for decoding of column signals. The decoded column signals are applied to the RAM chip seleα pin, pin 18, to seleα the column of RAM chips and are applied to the Intel 8216 bus interface chips associated with that column for outputting to the memory output bus. Seleαion of one of the 2-boards is provided with the fourth from the least significant X-address bit XA3 applied to UI 9B-6 and to the Intel 8216 chip seleα logic. XA3-bar is used to seleα memory board-1, XA3 is used to seleα memory board-2. Therefore, as the scanout proceeds in the X-direαion, the same block on alternate boards are seleαed without re-addressing; effeαively providing a
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16-column by 8-row aspeα ratio of RAM chips. Enabling of U19B with XA3 or XA3-bar to pin-6 is an optional control; where seleαion of one of two memory boards is performed with the Intel 8216 bus interface logic, as described below. Gating the column addresses U19B-6 with the XA3 and XA3-bar signals reduces memory power consumption. The X-axis decoders U19C and U19E are addressed with the least significant X-address bits XAO, XA1 , and XA2 for decoding of row signals. Decoder U 19C is used for read operations, where the decoded row signals are applied to the RAM data enable pin, pin 20, to seleα the row of RAM chips for read operations. The RAM data enable control, pin 20, is conventionally used for seleαing data direαion during read and write operations. However, in this configuration; it is also used to facilitate 2-dimensional scanout capability. Decoder U19E is used for write operations, where the decoded row signals are applied to the write control pin, pin 21, to seleα the row of RAM chips for write operations. The DIEN-bar signal is generated from the computer run/load-bar signal DOA6; enabling U19C-6 for read operations during the run mode when DIEN-bar is 1- set, disabling U19C-6 for read operations during the load mode when DIEN-bar is 0-set, enabling U19E-5 for write operations during the load mode when DIEN- bar is 0-set, and disabling U19E-5 for write operations during the run mode when DIEN-bar is 1-set. Therefore, during the run mode, U19C is enabled for reading image memory and U19E is disabled for preventing writing into image memory. Also, during the load mode, U19C is disabled to prevent reading of image memory and U19E is enabled for permitting writing into image memory. Enabling of UI 9E enables the write pulse W-bar input to U19E-4 to be steered to the appropriate row of RAM chips for writing into the RAM chip that is enabled with the chip seleα column signal to pin 18. The RAM chip data lines carry the output byte from the seleαed RAM chip during read operations and carry the input byte to the seleαed RAM chip during write operations. A shared bi-direαional bus struαure is used for bi-direαional communication with the RAM chips. Intel 8216 bus interface circuits are used for bi-direαional communication between a read bus and a write bus and the RAM chip. Each Intel 8216 can accommodated 4-lines, where Intel 8216 chips are used in pairs; U17A and U18A, U17B and U18B, U17C and U18C, and U17D and U18D; to accommodate the 8-lines of a RAM data byte. As can be seen in the memory schematics (Figs 6E to 6N); on the system bus side, the 8- input unidireαional lines for each pair of Intel 8216s are conneαed to different lines on the system write bus and the 8-output unidireαional lines for each pair of Intel 8216s are conneαed to different lines on the system read bus. On the
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memory side, the bi-direαional input and output buffers of the 8216s are internally conneαed together to provide 8-bi-direαional lines conneαing to the 8-lines for each RAM chip associated with the particular pair of Intel 8216s. The design connects the data buses for a pair of columns of RAM chips to a single pair of Intel 8216s. This facilitates a tradeoff of the number of Intel 8216 chips used and the speed of operation. A pair of NAND-gates UI 7E and U18E are used to OR the two column seleα signals associated with the pair of Intel 8216s and to AND the board seleα signal XA3 or XA3-bar for seleαion of the pair of Intel 8216s as a funαion of the seleαed board and the seleαed column pair of RAMs on that board. The seleαed pair of Intel 8216s conneα the seleαed RAM to the input bus or output bus under control of the above described signals. The run/load-bar signal applied as the DIEN-bar signal on pin 15 of the Intel 8216s selects the direαion of data communication. If the DIEN-bar signal is 1- set, indicative of the run mode of operation; the 1-set signal applied to pin-15 of an Intel 8216 commands data output from the RAM data bus to the memory output data bus for reading of RAM. If the DIEN-bar signal is 0-set, indicative of the load mode of operation; the 0-set signal applied to pin-15 of an Intel 8216 commands data input to the RAM data bus from the memory input data bus for writing into RAM. During read operations, all RAM chips are addressed with the same address signals and one of the RAM chips is seleαed with a combination of a column seleα signal and a row seleα signal. The seleαed RAM chip will have its output data lines enabled to be applied to the output data bus through the Intel 8216 bus interface chips. The column seleα signal also seleOs the Intel 8216 bus interface chips associated with seleαed column for applying the column-related RAM bus to the data bus for reading. During write operations, all RAM chips are addressed with the same address signals and one of the RAM chips is seleαed with a combination of a column seleα signal and a row-seleαed write pulse for writing the information from the data lines into the seleαed RAM chip. The column seleα signal also seleOs the Intel 8216 bus interface chips associated with the seleαed column for applying the input data from the data bus to the RAM chips for writing.
Improved IC Memory Chip An improved IC memory chip, can be implemented in accordance with the teachings of the present system and can provide important advantages over conventional memory chips. This improved memory chip can have multiple
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tristate control chip seleα inputs, similar to the 2-dimensional arrangement of the chip seleα and data enable signals. Also, each memory chip can have an output register to latch the accessed data, where the output register has an output tristate seieα with multi-dimensional seleαion. The data can be latched for scanout and new data can be accessed with a changing address. The data can be strobed into the output register before re-addressing the RAM, such as with a data hold strobe. Multiple dimensions of tristate output seleα, can be implemented, exemplified by the 2D tristate control of the system disclosed herein. 2D, 4D, and other multi-dimensional tristate controls can provide further advantages in decoding and scanning-out from image memory.
Memory logical Pesign The memory implemented for the experimental configuration is implemented in a multiple board arrangement, where each board contains 64-RAMs organized in a logical 8-RAM column by 8-RAM row 2-dimensional array. All RAMs receive the same address. All 8-RAMs in an 8-RAM row receive the same X- seleα signal, which is different from the X-seleα signal for all other rows. All 8- RAMs in an 8-RAM column receive the same Y-seleα signal, which is different from the Y-seleα signal for all other columns. The input data and output data signals are bussed together for groups of 16-RAMs and interfaced with Intel 8216s for conneαing to the system databus. The regular array of RAMs lends itself to a tabular wire list type of documentation. MEMORY TABLE-A to MEMORY TABLE-D list the interconneαions for the 64-RAM array on a board. The RAMs are organized in a physical 4-row by 16-column array comprising row-A to row-D and column-1 to column-8. Each RAM is identified by the physical row and column designation; where RAM U1A is the RAM that occupies the row-A and column-1 position, RAM U6C is the RAM that occupies the row-C and column-6 position, and the other RAMs occupy the other positions in row-A to row-D and column-! to column-16. MEMORY TABLE-A lists the conneαions for pin-1 to pin-12 of the first group of 32-RAMs. MEMORY TABLE-B lists the conneαions for pin-1 to pin-12 of the second group of 32-RAMs. MEMORY TABLE-C lists the conneαions for pin-13 to pin-24 of the first group of 32-RAMs. MEMORY TABLE-D lists the conneαions for pin-13 to pin-24 of the second group of 32-RAMs. The address conneαions are the same for all RAMs; where pins 1 to 8, 19, 22, and 23 are conneαed to an 11 -wire address bus; where each bus wire
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connects the same pin on each RAM. The vertical scanout pin, pin 18, for all 8- RAMs in a logical column are conneαed together and are conneαed to the vertical scanout signal from U19B corresponding to the particular logical column. The horizontal scanout pin, pin 20, for all 8-RAMs in a logical row are conneαed together and are conneαed to the horizontal scanout signal from UI 9C corresponding to the particular logical row. The horizontal write pin, pin 21, for all 8-RAMs in a logical row are conneαed together and are conneαed to the horizontal write signal from U19E corresponding to the particular logical row. The databus conneαions are the same for all RAMs in a double logical column or single physical column array; where pins 9 to 11 and 13 to 17 are conneαed to an 8-wire data bus conneαing all 16-RAMs in the double logical column or single physical column group. A pair of Intel 8216s conneα each 16- RAM databus to the system databus with bi-direαional read and write signal paths. Four pairs of Intel 8216s bi-direαional ly conneα all 64-RAMs to the system databus.
Other Memory Configurations Various configurations of the memory of the present invention have been above to illustrate how the various features and devices of the memory of the present invention can be used to implement a system. These configurations are illustrative of a large number of other configurations that can be implemented from the teachings herein. The memory configuration of the present invention has been discussed relative to implementing a 2D memory map for an image processing system and has briefly been discussed for other applications. It is herein intended that the memory architeαure of the present invention be usable with other types of display systems and with other systems, such as computer systems and signal processing systems, that are not display systems. The memory configuration of the present invention has been discussed in memory map form with an address derived from an X-axis address component and a Y-axis address component. Alternately, other addressing configurations can be implemented; such as a single address component for what may be considered to be a 1 D memory, a 3-address component for what may be considered to be a 3D memory map, and other memory addressing configurations. The memory configuration of the present invention has been discussed with reference to an integrated circuit RAM of the Mitsubishi M58725P-type.
However, the teachings of the present invention are also appropriate for other integrated circuit RAMs and are also appropriate for integrated circuit ROMs and other memory technologies. The memory configuration of the present invention has been discussed for a RAM component having 2-tristate control signals for controlling the tristate input and output of the RAM. Alternately, other numbers of tristate control signals can be accommodated; such as 1 -tristate control signal, 3-tristate control signals, 5- tristate control signals, and other quantities of tristate control signals. The architeαure for 2-tristate control signals permits implementation of what may be termed a 2-dimensional scanout arrangement having X-scanout control signals and Y-scanout control signals. Alternately, for a configuration having RAMs with 1-tristate control signal, a memory architeαure that may be termed a 1- dimensional scanout arrangement can be implemented having 1-scanout signal to each RAM. The 1 -scanout signal may be a single dimensional decode of the scanout portion of the address; such as 6-scanout bits being decoded to 64-RAM control signals with a different one of the 64-control signals going to each RAM tristate control signal input. Alternately, for a configuration having RAMs with more than 2-tristate control signals; such as 3-tristate control signals; a memory architeαure that may be termed a multi-dimensional scanout arrangement; such as a 3D scanout arrangement; can be implemented with multiple scanout signals to each RAM; such as 3-scanout signals to each RAM. For example, the scanout portion of the address word can be divided into 3-groups of scanout signals, similar to the 2-groups of scanout signals for the arrangement discussed with reference to Figs 6E to 6N, and 1 -signal from each of the 3-groups of scanout signals can be applied to a different one of the 3-tristate control inputs to the RAM for what may be considered to be a 3D-scanout control arrangement. The memory configuration of the present invention has been discussed for an arrangement that applies the same re-addressing portion of the address word to all RAMs. Alternately, the re-addressing portion of the address word can be partitioned to different RAMs; such as with decoding of a portion of the address and seleαing blocks of RAMs with the decoded signals, such as to the chip seleα pin of the RAMs. The multi-dimensional memory addressing arrangement discussed herein has been illustrated with reference to RAMs having 2-tristate control pins. Such multi-dimensional addressing can be implemented with a memory having a single tristate control pin, as discussed above, with digital logic to convert the single tristate control pin to a multi-dimensional scanout addressing arrangement. For example, the single tristate control pin, if implemented in
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complement logic form for seleαing with a complement signal, can be accessed with a 2-dimensional scanout arrangement by NAN Ding the 2-scanout address signals, such as the row seleα signal and the column seleα signal, with a NAND-gate to control the single tristate pin of the RAM. Similarly, multiple dimensional scanout control signals can be combined with logic external to the RAM to adapt the external scanout control signals to the particular capabilities of the RAM. For example, a 6-dimensional scanout arrangement can be adapted for a 3-dimensional tristate controlled RAM by combining the 6-dimensional scanout signals into pairs processed with two input NAND-gates to control the 3- tristate pins. Alternately, this 6-dimensional scanout arrangement can be adapted for a 2-dimensional tristate controlled RAM by combining the 6- dimensional scanout signals into groups of 3-signals processed with 3-input NAND-gates to control the 2-tristate pins. The memory configuration of the present invention has been discussed for an arrangement that pre-buses the data lines of 16-RAMs into a pre-databus and then further buses the 16-RAM pre-bused signals together onto a system databus. Other partitioning of bused data signals can be provided. For example, all data signals can be bused together onto the system databus without the intervening pre-busing of the 1 -RAM data outputs. Alternately, other combinations of RAMs than 16-RAMs can have the data lines pre-bused, such as pre-busing of the data lines of 8-RAMs together.
MEMORY ADDRESSING Introduαion Memory addressing can be performed in various ways. A new and novel memory addressing invention using memory scanout and memory re-addressing will now be is discussed in greater detail. Memory addressing, such as addressing Toshiba TC514256P DRAMs, is conventionally implemented with a combination of a RAS (row) memory operation followed by a CAS (column) memory operation. See the MOS MEMORY PRODUCTS DATA BOOK by Toshiba. Various examples are provided herein in the form of sync pulse related memory re-addressing. For simplicity of discussion; an interlaced scan configuration will be discussed, such as having a 17-ms field sync period, a 34- ms frame sync period, and a 64-us line sync period. Other scan configurations can also be provided; such as a progressive scan configuration having a 17-ms frame sync period and a 32-us line sync period. Various memory addressing configurations are discussed below. Memory re-
addressing is discussed in the context of deteαing a suitable time; such as a time available period (i.e.; a horizontal sync pulse period or a vertical sync period in a display system, a suitable instruαion execution period in a computer, etc) or a cycle stealing condition (i.e.; an overflow condition) or other condition and invoking memory re-addressing in response to this deteαion. Various implementations of memory refreshing are discussed herein, such as time available memory refreshing and cycle stealing memory refreshing; which may also be used to implement memory re-addressing. For example; a memory re-addressing operation can often be invoked concurrently with a memory refresh operation because the memory-related processing is often not being performed during a memory refresh operation. Alternately; memory re- addressing operations and memory refresh operations can be invoked separately. Other memory re-addressing configurations can also be implemented. The memory addressing configuration that uses a memory re-addressing deteαor to deteα a suitable memory re-addressing period and that invokes a memory re-addressing operation in response thereto may be considered to be an adaptive memory re-addressing configuration. This is because it adapts to the operations of the memory to provide memory re-addressing operations rather than having a fixed memory re-addressing cycle (such as re-addressing for every memory read or for every write cycle). Such an adaptive memory arrangement can result in advantages, such as significantly increased performance.
Scanout And Re-addressing Charaαerization Re-addressing and scanout in accordance with the present invention will now be discussed. Re-addressing is performed by addressing the array of memory locations in a memory element (i.e., in a DRAM chip or plurality of memory chips) to access the addressed data (i.e., a byte or a word) from the array of memory locations. This addressing or re-addressing is a relatively slow operation, such as due to propagation delays of the address signals through the memory array to seleα the data to be accessed. The addressed data that is accessed from the memory is often held stable for outputting in various configurations. In one configuration, the accessed data is held stable at the output of the memory by the address being held stable at the input to the memory. In another configuration, the accessed data is held stable at the output of the memory by the accessed data being loaded into an output register. In yet another configuration, the accessed data is held stable at the output of the memory by the sense amplifiers. Other configurations for holding the accessed data stable can also be provided.
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Memory elements, such as RAMs, often have seleαion circuits in the output of the element, such as to seleα all of the output data being held stable or to seleα some of the output data being held stable. For example, the Mitsubishi RAMs discussed herein access 8-bits at a time and the seleαioπ circuit, the chip seleα or output enable circuit G*, selects all 8-bits for outputting. Alternately, the Toshiba DRAMs discussed herein access 256-columns of 4-bits each (1- million bits) at a time and the seleαion circuit, the CAS column address selects one of the 256-column 4-bit nibbles for outputting. In addition, control of the output enable OE* signal to the OE* circuit or gating of the CAS* signal to the CAS* circuit can provide a chip seleα funαion. Because the data being held stable at the output has already been accessed, gating of this data; such as with a CAS column address, a chip seieα signal, or an output enable signal; is a relatively high speed operation and is herein charaαerized as a scanout operation. For simplicity of discussion, scanout operations controlled with external decoding and seleαion circuits, such as 74LS138 decoders (i.e., Fig 6F), are herein called external scanout operations and scanout operations controlled with internal decoding and seleαion circuits, such as CAS column addressing (i.e., Figs 4F to 4K), are herein called internal scanout operations. As further discussed herein, internal scanout operations and external scanout operations are compatible therebetween and can be used in combination, such as discussed with reference to Figs 4H to 4K herein. In view of the above, the accessing of data from a memory array (addressing or re-addressing) is a relatively slow operation and gating out of already accessed data from a memory output circuit (scanout) is a relatively fast operation. Hence, in various configurations discussed herein; memory re-addressing operations may be minimized and scanout operations may be maximized. DRAM systems, such as implemented in the IBM PCs, are conventionally implemented with a full cycle combined RAS and CAS cycle operation for reading and for writing and with a hardware bank or page seleα by combining the address MSBs to seleα the bank or page of DRAM chips. The RAS and CAS cycle is conventionally implemented with a full cycle RAS row address operation followed by a CAS column address operation for each read or write cycle. The conventional full cycle RAS and CAS operations are significantly slower than scanout operations of the present invention. For example, in the example herein relative to a Toshiba TC514256P-10 DRAM; a conventional full cycle RAS and CAS memory operation may be nearly four- times slower than a CAS-related scanout operation in accordance with the present invention supra.
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A bank or page seleα is conventionally implemented with an MSB address decoder for decoding MSBs to generate a chip seleα signal. The chip seleα signal is typically used for gating RAS or CAS signals to the chip RAS or CAS input. When this bank seleα or page seleα circuit is used in coπjunαion with conventional full cycle RAS and CAS operations, it is significantly slower than external scanout operations in accordance with the present invention. This is because external scanout operations are higher in speed then RAS row operations, about comparable in speed with CAS column address operations, and hence external scanout operations may be nearly four times faster than conventional full RAS and CAS operations supra. When external scanout is used in conjunαion with internal scanout operations in accordance with the present invention, it extends the scanout address space into the spatial domain and hence permits more scanout operations before a RAS re-addressing operation is needed. The conventional full RAS and CAS cycle and the conventional bank seleα or page seleα circuitry is illustrated with the IBM PC XT DRAM architeαure. This architeαure teaches away from the re-addressing and scanout features of the present invention and also teaches away from the external scanout and internal scanout features of the present invention. Upgrades to the IBM PC to praαice the features of the present invention is discussed herein. The various features of the present invention need not be used in combination, but can be used separately from one another. For example; even though the re-addressing and scanout features of the present invention and the external scanout and internal scanout features of the present invention are significantly different from the full cycle RAS and CAS operations and the bank seleα or page seleα circuits in the IBM PC/XT, other features of the present invention are not inherently locked to the re-addressing and scanout features nor to the external scanout and internal scanout features of the present invention. These other features of the present invention can be used with conventional memory architeαures; such as with a conventional full cycle RAS and CAS memory and with such as with a conventional bank seleα or page seleα memory. For example, the two dimensional (X-axis and Y-axis) address configuration is independent of whether the DRAMs are addressed with full cycle RAS and CAS operations, or bank seleα using address MSBs, or the re- addressing and scanout features of the present invention. Also, time available refreshing is independent of whether the DRAMs are addressed with RAS and CAS cycles, or bank seleα using address MSBs, or the re-addressing and scanout features of the present invention.
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The external scanout features of the present invention may be charaαerized by seleαing different memories (i.e., DRAM chips) to output data, such to output data to a data bus or to output data to dedicated data lines, without the need to RAS re-address the DRAM chips inbetween external scanout operations in the same bank or page of memory. For example, a plurality of DRAM chips can all be RAS row addressed (re-addressing) together and then can be sequentially chip seleαed (externally scanned out) in order to scan out the previously RAS row addressed data from the plurality of DRAM chips before having to be again re- addressed. In one configuration, a plurality of DRAM chips can all be simultaneously RAS row addressed and can then be sequentially chip seleαed in order to externally scan out the RAS row addressed data to a data bus from the plurality of DRAM chips before having to be again re-address. External scanout can be implemented by using the chip seleα to scanout the data without the need to re-address. The chip seleα can be implemented with an on-the-chip chip seleα circuit controlled by a chip seleα CS pin, or can be implemented by gating or steering the CAS signals to an on-the-chip CAS circuit controlled by a CAS pin, or can be implemented with an on-the-chip output enable circuit controlled by an output enable OE pin, or can be implemented with an off-the- chip chip seleα circuit, or can be implemented by gating or steering the CAS signals to an off-the-chip output enable circuit, or can be implemented by other circuits. Such chip seleαion is often significantly faster than a re-addressing operation and hence can result in significantly better performance than available with full cycle re-addressing operations. For simplicity of discussion, the external scanout feature of the present invention may be shown herein having the external scanout-related DRAM chips all being RAS row addressed with the same row address. Alternate embodiments can be provided having the external scanout-related DRAM chips RAS loaded with different row addresses infra. In alternate embodiments of the external scanout feature of the present invention, the external scanout-related DRAM chips need not all be RAS loaded with the same row address. For example, although it may be convenient to RAS- load all of the DRAM chips with the same address for reading and/or writing operations so that the information in the spatial domain is stored in adjacent addresses (i.e., addresses having the same MSBs); other configurations can be implemented that achieve these features of the present invention without RAS- loading all of the DRAM chips with the same address for reading and/or writing operations. Various configurations of external scanout will now be discussed. The terminology "master" will be used, such as pertaining to non-adjacent re-
soB S Tπurε SHB r
addressing, to represent an address parameter where the bits have not as yet been complemented or otherwise adapted for non-adjacencies. Non-adjacent re-addressing for external scanout lft'ΪWWMbeHl jstrate - with-a first example. If an MSB RAS-related address bit of a master address parameter is complemented for a first DRAM chip and is uncomplemented for a second DRAM chip, the RAS row address that is loaded into the first DRAM will be different from the RAS row address that is loaded into the second DRAM (by the complemented and uncomplemented bit, respeαively) and hence the address space in the first DRAM chip will be different from the address in the second DRAM chip. The address spaces in the first DRAM chip and in the second DRAM chip have correspondence with the master address, where the scanout and re-addressing feature of the present invention can be utilized in such a configuration. For simplicity of discussion, complementing and noncomplementing is discussed for a single bit of the MSB RAS-related address bits. Multiple MSB RAS-related address bits can be complemented and uncomplemented in various combinations between a plurality of DRAM chips with consistent results. Non-adjacent re-addressing for external scanout will now be illustrated with a second example. Jf MSB RAS-related address bits of a master address parameter are interchanged for a first DRAM chip and are either not interchanged or are interchanged differently for a second DRAM chip, the RAS row address that is loaded into the first DRAM chip will be different from the RAS row address that is loaded into the second DRAM chip (by the interchanged bits and either the non-interchanged bits or the different interchanged bits, respeαively) and hence the address space in the first DRAM chip will be different from the address in the second DRAM chip. The address spaces in the first DRAM chip and in the second DRAM chip have correspondence with the master address, where the scanout and re-addressing feature of the present invention can be utilized in such a configuration. For simplicity of discussion, interchanging and either noninterchanging or different interchanging may be discussed for a single bit pair of the MSB RAS-related address bits. Multiple MSB RAS-related address bits can be interchanged and non interchanged or interchanged differently in various combinations between a plurality of DRAM chips with consistent results. Non-adjacent re-addressing for external scanout will now be illustrated with a third example. If two MSB RAS-related address bits of a master address parameter are encoded in a first manner for a first DRAM chip and are either not encoded or are encoded in a second manner for a second DRAM chip, the RAS row address that is loaded into the first DRAM chip will be different from the
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RAS row address that is loaded into the second DRAM chip (by the first encoding and either the not encoding or the second encoding, respeαively) and hence the address space in the first DRAM chip will be different from the address in the second DRAM chip. The address spaces in the first DRAM chip and in the second DRAM chip have correspondence with the master address, where the scanout and re-addressing feature of the present invention can be utilized in such a configuration. For simplicity of discussion, different methods of encoding and or not encoding for different DRAM chips may be discussed for a single bit pair of the MSB RAS-related address bits. Multiple MSB RAS-related address bits can be differently encoded in various combinations between a plurality of DRAM chips with consistent results. DRAM chip seleαive re-addressing for external scanout will now be illustrated with a third example. If DRAM chips are seleαed for RAS re- addressing, such as by gating the RAS signals to different DRAM chips, then different DRAM chips can be re-addressed separately. Hence, the RAS row address that is loaded into the DRAM chips can be different from each other. Many other configurations can be implemented; such as configurations having complementing and uncomplementing of master address MSBs, and/or having interchanging of master address MSBs, and/or having different encoding of master address MSBs, and/or having different decoding of master address MSBs before inputting to the DRAM chips, and/or having separate seleαion of different DRAM chips. These configurations can be used in combination; where for example complementing and uncomplementing of one or more master address MSBs, and/or interchanging or not interchanging of one pair or more master address MSBs, and/or encoding or either not encoding or encoding differently of master address MSBs, and/or decoding or either not decoding or encoding differently of master address MSBs, and/or having separate seleαion of different DRAM chips can be used in combinations therebetween with the same results. In view of the above, it will become clear that the scanout and re-addressing features of the present invention can be praαiced in various ways to achieve significant improvements in performance compared to conventional arrangements. For simplicity of discussion and for consistency with the display system configuration previously discussed, memory operations may be disclosed herein in the form of memory accessing operations. However, a disclosure of memory accessing operations is herein intended to be illustrative of using the features of the present invention for writing operations, for read-modify-write operations,
and for other memory operations. Further, the term memory scanout herein is intended to be equally applicable to write operations as well as to read operations; where memory scanout terminology is intended to illustrate or to encompass memory scanin terminology. One skilled in the art would readily be able to apply the disclosures of memory accessing operations to implement the features of the present invention for writing operations, for read-modify-write operations, and for other memory operations based upon the disclosures herein. For example, the differences between access (read) and write operations may be little more than controlling the WRITE signal, or other write related signal, to be high or low. Further, various write operations are disclosed herein, such as with reference to Figs 6E to 6N. Still further; write operations, read-modify-write operations, and other operations and the waveforms related thereto and the implementations thereof are well known in the art, such as disclosed in the Toshiba DATA BOOK referenced herein. Hence, one skilled in the art would readily be able to implement the teachings of the present invention with other memory operations, such as write operations and read-modify-write operations, from the teachings herein. The term blocks of memory is used herein in conjunαion with memory re- addressing and memory scanout operations. For example, a block of memory is the memory locations that are accessible with memory scanout operations without the need to invoke a memory re-addressing operation and a block of memory is changed with a re-addressing operation; providing scanout within a block of memory and re-addressing between blocks of memory.
External Scanout And Internal Scanout External scanout and internal scanout can be implemented individually or in combination, such as to facilitate enhanced performance. The configurations discussed with reference to Figs 4H to 4K illustrate combinations of external scanout and internal scanout. The configurations discussed with reference to Figs 4F, 4G, 4L, and 7A to 7D illustrate internal scanout. External scanout can be implemented by externally distributing the scanout address region, such as among multiple DRAM chips arrayed in a memory. Internal scanout can be implemented by internally distributing the scanout address region, such as among multiple bits arrayed in a register in the same DRAM chip. External scanout and internal scanout can be combined to generate a combination external scanout and internal scanout implementation by distributing the scanout address region among multiple memory elements arrayed in a memory and among multiple bits arrayed in each of the multiple
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memory elements. For example, external scanout and internal scanout can be combined by externally distributing the scanout address region among multiple DRAM chips arrayed in a memory and by internally distributing the scanout address region among multiple bits arrayed in a register in each of the multiple DRAM chips.
DETECTOR CIRCUITS Introduαion Various deteαor circuits can be implemented to provide a control signal for controlling memory operations; such as re-addressing, scanout, and refreshing operations in accordance with the present invention. Deteαors for deteαing a memory re-address condition, for deteαing a memory scanout condition, for deteαing a memory refresh condition, and for deteαing other memory conditions can be implemented from the teachings herein. Various deteαor circuits disclosed herein may be use in the configurations shown in Figs 4B and 4C. For example, overflow deteαors are described with reference to Fig 6C for controlling memory re-addressing and overflow deteαors, comparitor deteαors, anticipatory deteαors, modal deteαors, time available deteαors, and refresh deteαors are disclosed herein. Memory operations can be controlled in response to memory deteαor circuitry for generating a deteαor signal in response to deteαing a memory condition. Memory operation invoking circuitry; also called memory operation controlling, commanding, execution, or performing circuitry; controls the appropriate memory operation in response to the deteαor signals. For simplicity of discussion; memory deteαors and memory operation invoking-circuitry may be disclosed in the context of a memory deteαor; where the memory operation invoking circuitry may be implicit in the memory deteαor circuitry discussion. For example, the overflow deteαor discussed with reference to Fig 6C has the memory operation invoking circuitry contained therewith, such as in the time delay circuitry associated with flip-flops K1 and K2 and the clock gating logic U12A-6 and U12A-8 which facilitates re-addressing operations. For simplicity of discussion, memory re-addressing and memory scanout deteαors may be discussed in the configuration of monitoring MSBs of an address register and generating a deteαor signal when the MSBs of the address register change. Alternately, other memory re-addressing and scanout deteαors can be implemented; including an anticipatory deteαor for memory re- addressing and scanout that need not monitor address MSBs, a modal deteαor for memory re-addressing and scanout that need not monitor address MSBs, and
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a time available deteαor for memory re-addressing and scanout that need not monitor address MSBs infra. Other memory re-addressing and scanout deteαors can also be implemented. It is herein intended that various deteαors can be used in combination. For example, address deteαors and refresh deteαors can be used in combination. Also, a modal deteαor can be used to invoke re-addressing for a mode change and an overflow deteαor or a comparitor deteαor or a time available deteαor can be used to invoke re-addressing for a change in the address MSBs without a mode change. Also, in a display configuration or a television configuration; a modal deteαor can be used to invoke re-addressing for an image change and an overflow deteαor or a comparitor deteαor or a time available deteαor can be used to invoke re-addressing for a memory block change without an Image change. Also, in a microprocessor configuration; a moda-I deteαor can be used to invoke re-addressing for execution of a transfer instruαion and an overflow deteαor or a comparitor deteαor or a time available deteαor can be used to invoke re-addressing for a block change without execution of a transfer instruαion. Also, in an array processor configuration; a modal deteαor can be used to invoke re-addressing for an array change and an overflow deteαor or a comparitor deteαor or a time available deteαor can be used to invoke re- addressing for a memory block change without an array change. Also, in a filter processor configuration; a modal deteαor can be used to invoke re-addressing for a filter reference change and an overflow deteαor or a comparitor deteαor or a time available deteαor can be used to invoke re-addressing for a memory block change without a filter reference change. Also, in a signal processor configuration; a modal deteαor can be used to invoke re-addressing for a signal change and an overflow deteαor or a comparitor deteαor or a time available deteαor can be used to invoke re-addressing for a memory block change without a signal change. Also, in an artificial intelligence processor configuration; a modal deteαor can be used to invoke re-addressing for an artificial intelligence inference change and an overflow deteαor or a comparitor deteαor or a time available deteαor can be used to invoke re-addressing for a memory block change without an artificial intelligence inference change. A memory re-addressing deteαor can be implemented with a combination of various memory re-addressing deteαor circuits, such as the combination of a time available memory re-addressing deteαor circuit and such as a non-time available memory re-addressing deteαor circuit (i.e., an overflow memory re- addressing deteαor circuit). In such a combination deteαor circuit, the time available deteαor circuit can initiate memory re-addressing operations and,
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when the time available deteαor circuit terminates the time available period, a non-time available deteαor circuit (i.e., an overflow deteαor circuit) can delay or disable processor operations to permit any memory re-addressing operation that is in process when the time available deteαor terminates the time available period to complete the memory re-addressing operation. A deteαor can be implemented as a combination of deteαors and memory operation invoking circuitry can be implemented to complete an invoked operation, as will now be illustrated with an example discussed with reference to Fig 6W. In this example; signal F4* represents a time available condition, such as a RUN signal or a sync pulse signal. The time available condition can be deteαed with a deteαor circuit for invoking a memory operation, such as a memory re-addressing operation and/or a memory refresh operation. Deteαor signal F4* is shown generating signals U14A-6 and U21 E-8 to invoke a memory re-addressing operation and can also be used to invoke a memory refresh operation. Once a memory operation is invoked with flip-flop Kl; the memory operation continues until flip-flops K2 and K3 complete the cycle. If the F4* deteαor signal period ends before the memory operation cycle has been completed, the memory operation will still be completed because flip-flops Kl, K2, and K3 store the deteαor signal until the cycle is completed. Other circuits that insure completion of a memory re-addressing operation or a memory refresh operation can also be implemented. The memory refresh deteαor circuits can be discussed herein for deteαing a condition that is suitable for invoking a plurality of memory refresh operations for each deteαion. However, it may not be necessary or it may not be desirable to invoke a plurality of re-addressing operations during the same condition with such deteαors. This is because the re-addressing address might not change during a time available period having a duration sufficient for multiple memory refresh operations. Hence, it may be desirable to limit memory re-addressing to a single re-addressing operation in a time available condition envelope. This can be implemented in various ways; such as by processing the deteαor signal with a one-shot circuit as discussed with reference to Fig 6W relative to deteαor signal F2*. Memory deteαors may be discussed herein in various forms; such as overflow deteαors, comparitor deteαors, anticipatory deteαors, modal deteαors, time available deteαors, and other deteαors. However, a deteαor may fit several charaαerizations. For example, the RUN signal discussed with reference to Figs 6A et seq herein may be used to implement an anticipatory deteαor, a modal deteαor, and a time available deteαor.
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Overflow Deteαor Circuits Overflow deteαor circuits are discussed with reference to Fig 6C for deteαing when the MSBs of an address have changed in order to control re- addressing. This can be implemented as an alternate to or in addition to comparitor deteαor circuits, anticipatory deteαor circuits, time available deteαor circuits, modal deteαor circuits, and other deteαor circuits. This overflow deteαor monitors the carry signal as being indicative of an overflow as a funαion of the sign of the address in the slope register. Other overflow deteαors can be provided. For example, an overflow deteαor that determines an overflow as a funαion of both, the sign of the address in the address register and the sign of the parameter added to or subtraαed from the address, can be implemented from the teachings herein. When an overflow is deteαed, overflow deteαor output signal U21 B-2 and U12A-6 command a lower clock rate re-addressing operation (Fig 6Q. If an overflow is not deteαed, overflow deteαor output signal U23C-10 and U12A-8 command a higher clock rate scanout operation (Fig 6Q. Overflow control signal generation will now be disclosed with reference to Fig 4D. Address register 410 is composed of the least significant bits (LSBs) 412 and the most significant bits (MSBs) 414 conneαed by overflow logic 416 for generating overflow signal 418 in response to an overflow from the LSBs to the MSBs, as discussed with reference to Fig 6C. The address stored in address register 410 can be changed in various ways; such as by adding a parameter 420A and/or 421A to the address stored in address register 410 and such as by loading an address 420A and/or 421 A into address register 410. An arrangement is disclosed with reference to Fig 6C for generating a memory control signal to gate a clock by deteαing an overflow of an address generator as being indicative of the need to re-address the memory. Such an arrangement is particularly appropriate to address counter type systems where an address counter advances toward an overflow condition and eventually overflows to change the more significant bits. The display processor disclosed with reference to Figs 60 to 6R is such an address counter system, thereby facilitating overflow deteαion to generate a memory control signal. Conventional computer systems have address counters or address counters, thereby facilitating overflow deteαion to generate a memory control signal. A configuration that adds a parameter 420A and/or 421 A into address register 410 will now be disclosed. For a configuration that adds a parameter 420A to the LSBs 412 of address register 410 but does not add a parameter 421 A to the
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MSBs 412 of address register 410, the MSBs 414 of address register 410 are not changed if an overflow signal 418 is not generated and the MSBs 414 of address register 410 are changed if an overflow signal 418 is generated. This is in accordance with the overflow implementation shown in Figs 6C and 60 to 6R. For a configuration that adds a parameter 421 A into the MSBs 414 of address register 410 in combination with adding a parameter 420A into the LSBs 414 of address register 410, the MSBs 414 of address register 410 are changed independent of whether an overflow signal 418 is generated. This is different from the overflow implementation shown in Figs 6C and 60 to 6R. For a configuration that adds a parameter 421A into the MSBs 414 of address register 410 without adding a parameter 420A into the LSBs 414 of address register 410, the MSBs 414 of address register 410 are changed but an overflow signal 418 is not generated. This also is different from the overflow implementation shown in Figs 6C and 60 to 6R. Hence, a configuration that adds a parameter into the MSBs 414 of address register 410 may need an implementation different from the overflow implementation shown in Figs 6C and 60 to 6R. A configuration that loads an address 420A and/or 421 A into address register 410 will now be discussed. For a configuration that loads an address 420A into the LSBs 412 of address register 410 but does not load an address 421 A into the MSBs 414 of address register 410, the MSBs 414 of address register 410 are not changed and an overflow signal 418 is not generated. This is similar to the overflow implementation shown in Figs 6C and 60 to 6R. For a configuration that loads an address 421A into the MSBs 414 of address register 410 (either in combination with loading an address 420A into the LSBs 414 of address register 410 or without loading an address 420A into the LSBs 414 of address register 410), the MSBs 414 of address register 410 are changed but an overflow signal 418 is not generated. This is similar to the overflow implementation shown in Figs 6C and 60 to 6R. Hence, a configuration that loads an address 421 A into the MSBs of address register 410 may need an implementation different from the previously disclosed overflow implementation. In view of the above, overflow signal generation is particularly appropriate in configurations where the overflow bit position is more significant than the MSB position that is to be changed by the updating operations of the address counter so that the more significant bits are changed by an overflow from the less significant bits infra. This is the environment for the display processor disclosed with reference to Figs 6C and 60 to 6R because the slope parameter stored in the slope register, which was used to update the address register, is shown having a maximum magnitude that is less significant than the overflow
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SUB sTiTuτe
magnitude. However, in other configurations, the MSBs 414 may be changed without generating an overflow signal 418 from the LSBs 412 supra. For example, in other configurations, the parameter added to address register 410 may have MSBs 421 A that are more significant than the overflow bit position or the parameter loaded into address register 410 may load MSBs 421 A that can change the MSBs 421 A of address register 410 without generating an overflow signal 418. Also, in said display application, the more significant bits of the address register may be changed other than by an overflow from the less significant bits. For example, the slope parameter stored in the slope register can alternately be implemented to have a maximum magnitude that is more significant than the overflow magnitude and hence can change the more significant bits by a direα update of these more significant bits rather than by an overflow from the LSBs or in addition to an overflow from the LSBs.
Comparitor Peteqor Circuits Comparitor deteαor circuits can be implemented as an alternate to or in addition to overflow deteαo: circuits, anticipatory deteαor circuits, time available deteαor circuits, modal deteαor circuits, and other deteαor circuits. For example, in a comparitor deteαor configuration; a comparitor can be used to compare the prior MSBs and the next MSBs to deteα a change in the MSBs of the address. A comparitor deteαor arrangement is shown in Fig 4D for use in conjunαion with a memory address register; such as for implementation in a microprocessor, in a display processor, in a filter processor, in a database processor, in a cache memory processor, in an artificial intelligence processor, or in other processors. This configuration is particularly appropriate for implementation in close conjunαion with the memory address register 410; such as on the same IC chip with the memory address register. In this configuration; comparitor 422 can be used to compare the prior MSBs, such as MSBs 42 I B stored in address register 410, and the next MSBs, such as MSBs 421A that will be clocked into the address register 410 on the next address register clock pulse, to deteα a change in the MSBs 414 of the address stored in address register 410. If a difference is deteαed, comparitor deteαor output signal 423 can be used to invoke a slower re-addressing operation. If a difference is not deteαed, comparitor deteαor output signal 423 can be used to invoke a faster scanout operation. An alternate comparitor deteαor arrangement is shown in Fig 4E for use in conjunαion with a memory address register; such as for implementation in a microprocessor, in a display processor, in a filter processor, in a database
rr rr*
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processor, in a cache memory processor, in an artificial intelligence processor, or in other processors. This configuration is particularly appropriate -for 'various memory implementations; such as for an off-the-chip deteαor that does not have access to all of the address signals and for a shared address register configuration. A configuration that implements the deteαor external to the memory address register 410, such as off the IC chip that contains the memory address register, will now be discussed. The comparitor arrangement shown in Fig 4E can be used with a processor already having an address register embedded therein, such as in an IC chip, and hence not being fully accessible for conneαion to the comparitor circuits. An existing microprocessor (i.e., Fig 4E) can have MSB memory address signals 421 B, which are output from MSB memory address register 414, available on the external address bus; but may not have MSB memory address signals 421 A, which are input to MSB memory address register 414, available externally. This configuration (Fig 4E) is particularly appropriate for updating an existing microprocessor that was not implemented with an address MSB change deteαor therein and which may have limited external access to the address register for implementing a Fig 4D deteαor. In a limited accessibility case, an external MSB buffer register 414A can be implemented (in addition to the internal address register MSBs 414) to store the prior address MSBs (redundant with the address register MSBs 414), such as for implementation external to a microprocessor IC chip. In this configuration; comparitor 422 can be used to compare the prior MSBs, such as MSBs 421 C stored in external buffer register 414A, and the next MSBs, such as MSBs 421 B that will be clocked into the external MSB buffer register 414A, to deteα a change in the MSBs 421 B of the address stored in address register 410. If a difference is deteαed, comparitor deteαor output signal 423 can be used to invoke a slower re-addressing operation. If a difference is not deteαed, comparitor deteαor output signal 423 can be used to invoke a faster scanout operation. A shared address register configuration, such as an address register configuration that shares the address register between RAM operations and non- RAM operations or between first RAM operations in a first RAM and second RAM operations in a second RAM, can use buffer 414A to store the RAM-related address MSBs while the address register 414 is being used to address other circuits. One configuration of such a comparitor arrangement is shown in Fig 4E. For example, a microprocessor can have MSB memory address signals 421 B, which are output from MSB memory address register 414, and loaded into buffer
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register 414A for temporary storage. This configuration (Fig 4E) is particularly appropriate for storing the address MSBs from a prior operation in buffer 414A while the address register 414 is being used for addressing other circuits. In this configuration; comparitor 422 can be used to compare the prior MSBs and the next MSBs to deteα a change in the MSBs 421 of the address stored in address register 410 supra and can also be used to buffer the address MSBs while the address register is being used to address other circuits, as discussed for a shared address register configuration below. Various circuits can be used for loading the address MSBs 421 B into external MSB buffer register 414A (Fig 4E), such as a multiphase clock 01 and 02. In one configuration, the loading of the prior address MSBs 421 B into buffer register 414A shortly follows 02. The loading of the MSBs 421A into the MSBs 41 of address register 410 under control of the 01 clock or otherwise changing of the MSBs 414 of address register 410 can precede the memory access operation. This facilitates generation of the control signal (i.e., comparitor signal 423) to initiate alternate memory operations, such as generating a re-addressing operation before accessing memory if the MSBs 421 B have changed. Various types of comparitors can be used. One common comparitor is a 74LS85 four bit comparitor having four A inputs to be compared with four B inputs and generating an output signal O^. g when the four A inputs are equal to the four B inputs. The four bit 74LS85 comparitor can be expanded to very large word sizes; as discussed in the Shottky TTL Data Book by Motorola Inc., such as at page 4-61. In various configurations, such as a shared address register configuration; it may be desirable to control operation of buffer 414A and comparitor 422 with a control signal. For example, control signal 432H can be generated by logic 432J deteαing whether address signals 421 B are within the instant RAM address space or are outside of the instant RAM address space. Control signal 432H can be used to gate the 02 clock 432 E with gate 432 F, which is shown as a NAND gate for convenience of discussion, to generate gated 02 clock 432G to seleαively control buffer register 414A. Also, control signal 432H can be used to control comparitor 422, such as to enable and disable comparitor signal 423 for enabling and disabling auxiliary memory operations. For example, in a 74LS85 four bit comparitor; the cascading input signals can be controlled to enable or disable the output signals. Logic 432J can be implemented with conventional logic gates, such as And gates, OR gates, and NOT gates to generate address deteαor signal 432 H to deteα when the address MSBs pertain to the instant RAM address space. If the
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instant RAM address space is continuous and can be represented by a simple combination of address signals and complements of address signals, such as with the top half of the memory address space being dedicated to the instant RAM; then a simple AND gate and inverter gates or their equivalents for ANDing together all of the address lines in complemented and non-complemented form may be sufficient to implement logic 432J. Alternately, if the RAM address space is not continuous or is otherwise not a simple binary combination of address bits; then various AND gates, OR gates and inverter gates or their equivalents may be needed to implement logic 432J. In certain configurations there may be advantages to implementing a Fig 4D type comparitor compared to a Fig 4E type comparitor. For example, placing the comparitor deteαor circuit on the processor IC chip and hence having access to internal signals rather than placing it on another IC chip and hence not having access to internal signals may include the advantages of a) reducing the IC chip count, b) reducing external IC chip interconneαions, c) reducing circuitry, and d) increasing performance. For example, placing deteαor circuitry on the IC processor chip should reduce additional IC chips needed to contain external deteαor circuitry and the related external interconneαions. Further, there may be a reduαion in the total amount of circuitry by eliminating the external buffer register 414A, shown in the Fig 4E configuration, by using a Fig 4D configuration. Also, the Fig 4D type comparitor performs what may be called an early comparison before the address MSBs 421 B are changed, which may have advantages in certain applications, while the Fig 4E type comparitor performs what may be called a late comparison after the address MSBs 421 B have changed. Such an early comparison can reduce the effeα of propagation delays by providing an early initiation of propagation delays for improved performance. For example; in the Fig 4D configuration, the propagation delay of address signal 421 A through comparitor 422 can precede the clocking of register 414, while in the Fig 4E configuration, the propagation delay of address signal 421 B through comparitor 422 cannot precede the clocking of register 414. Alternately, in other configurations there may be advantages to implementing a Fig 4E type comparitor compared to a Fig 4D type comparitor. One such configuration may be a shared address register configuration, such as discussed in the shared address register seαion herein. Further, some of the disadvantages of placing the deteαor circuit off-the-chip supra may not be pertinent to a
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particular configuration. For example, an off-the-chip comparitor deteαor may be implemented on another IC chip together with other circuitry and hence an off-the-chip deteαor may not involve an extra IC chip or extra circuitry; an additional address buffer register can be implemented for other reasons and hence an off-the-chip deteαor may not involve extra circuitry; and memory cycles may follow sufficiently later than the clocking of the internal address register that the required propagation delay time is readily available for an off- the-chip deteαor configuration and hence an off-the-chip deteαor may not reduce performance. A comparitor deteαor can be used in the circuit of Fig 6C in place of the overflow deteαor, such as by replacing overflow deteαor signal U13A-6 to U23C-1 1 with the comparitor deteαor output signal 423. Minor logical considerations may be necessary; such as inserting of an inverter for polarity, inserting of a buffer gate for fanout, use of higher speed gates for propagation delay reduαion, and other considerations. For example, overflow deteαor signal U13A-6 generates a negative voltage logic (NVL) signal and inverter U14A-6 converts the NVL signal to a positive voltage logic (PVL) signal.
Anticipatory DgteflQr Circ i s Anticipatory deteαor circuits can be implemented as an alternate to or in addition to overflow deteαor circuits, comparitor deteαor circuits, time available deteαor circuits, modal deteαor circuits, and other deteαor circuits. For example, in an anticipatory deteαor configuration; a re-addressing operation may not be aαually detected but may be anticipated, such as by deteαing a condition that anticipates the need for a re-addressing operation. An anticipatory deteαor can be implemented with an overflow circuit that detects a future need for a re-addressing operation, rather than an immediate need for a re-addressing operation; such as deteαing the need for a re-addressing operation that will be needed a propagation delay later, or a clock pulse later, or a line sync pulse later, or a memory access later, etc. For example, an anticipatory overflow deteαor can be implemented to anticipate an overflow by logically testing prior stages in an address adder, such as with the carry lookahead implemented in the address adder shown in Figs 60 to 6R. Said 74F283 adder stages incorporate a four bit fast carry lookahead. Other carry look-ahead circuits are well known. A separate carry lookahead circuit, such as implemented with a 74LS182 circuit, can be used for deteαion of a re- addressing condition, such as to anticipate an overflow to the address MSBs before the overflow to the address MSBs aαually occurs. Alternately, a shared
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carry lookahead circuit can be implemented for both, deteαion of a re- addressing condition and generating a carry to the MSBs of the address register, such as disclosed with the carry lookahead circuit in the 74F283 adder circuits shown in Figs 60 to 6R. Another type of anticipatory deteαor can be implemented by monitoring signals that are known to precede the need for a re-addressing operation, such as by designing an anticipatory deteαor circuit to generate such an anticipatory signal or by identifying such a signal that has been generated for other purposes and is available as an anticipatory deteαor signal. For example, the RUN signal U13A-8 is generated to enable gating of clock signals with gates U12A-6 and U12A-8; where the RUN signal going high is anticipatory of the start of a run mode of operation and hence is anticipatory of the need for a re-addressing operation associated with the start of a run mode. Hence, certain modal signals described herein for invoking a modal deteαor can also implement an anticipatory modal deteαor. A stored program computer can implement anticipatory memory addressing operations, such as implementing memory re-addressing in response to conditions that are anticipated to invoke operations needing re-addressing. For example, an instruαion deteαor can be used to deteα instruαions that anticipate re-addressing, such as long branch or long jump instruαions. Signals associated with the start of execution of such instruαions provide the anticipatory signals to invoke a re-addressing operation before the address counter is loaded with the new address and hence provide anticipatory control of re-addressing operations. A processor having micro-operations; such as a state machine, a micro- programmable processor, or a processor having micro-operations; can implement anticipatory memory addressing operations, such as implementing memory re-addressing in response to states, micro-operations, or micro- instruαions that are anticipated to invoke operations needing re-addressing. For example, a micro-instruαion deteαor can be used to deteα micro-instruαions that anticipate re-addressing, such as branch or jump micro-instruαions. Signals associated with the execution of such micro-instruαions provide the anticipatory signals to invoke a re-addressing operation before the address counter is loaded with the new address and hence provide anticipatory control of re-addressing operations. Various stored program computer configurations will now be discussed with reference to the Motorola 68HC11 single chip microcomputer; particularly with reference to Seαion-5 of the Motorola 68HC11 Programmer's Reference
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Manual; and with reference to the discussion in conjunαion with time available deteαor circuits herein. An instruαion execution cycle having time available is indicated with the symbol $FFFF in the "Address Bus" column and with the term "Irrelevant Data" in the "Data Bus" column. Each instruαion first accesses the opcode, decodes the opcode thereby identifying the instruαion to be executed, and then proceeds with the instruαion execution including any time available cycles. The time available cycles always follow the opcode access and decoding for an instruαion. Hence, time available cycles are implicitly known or implicitly anticipated one or more cycles before a time available cycle is invoked. Hence, the micro-operations in the 68HC11 can provide anticipatory micro-operation signals for memory re-addressing and memory refreshing. An anticipatory deteαor arrangement can be used for implementation in a microprocessor, in a display processor, in a filter processor, in a database processor, in a cache memory processor, in an artificial intelligence processor, or in other processors. It is particularly appropriate for implementation in high speed memory applications because anticipatory deteαion can be faster than aαual deteαion.
Modal Deteαor Circuits Memory re-addressing and memory scanout deteαor circuits can be implemented by deteαing changes in modes of operation that imply re- addressing. For example, a system that operates in a single block of memory with memory scanout operations in a particular mode and that operates in different blocks of memory for different modes can invoke re-addressing operations in response to deteαion of a mode change. Modal deteαor circuits can be implemented as an alternate to or in addition to overflow deteαor circuits, comparitor deteαor circuits, anticipatory deteαor circuits, time available deteαor circuits, and other deteαor circuits. For example, in a modal deteαor configuration, a modal signal can be used to invoke re-addressing as being implicit in a mode change condition. Mode changes often imply changes in operation. For example, in a display system, a change from the field sync pulse being high (i.e., field processing without display operations) to the field sync pulse being low (i.e., display operations without field processing) or alternately a change from the field sync pulse being low (i.e., display operations without field processing) to the field sync pulse being high (i.e., field processing without display operations) can involve a re-addressing operation implicit in the change in the modes of operation. Similarly, in a display system, a change from the line sync pulse
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being high (i.e., line processing without display operations) to the line sync pulse being low (i.e., display operations without line processing) or alternately a change from the line sync pulse being low (i.e., display operations without line processing) to the line sync pulse being high (i.e., line processing without display operations) can involve a re-addressing operation implicit in the change in the modes of operation. Also, a change from a run mode to a standby mode or alternately a change from a standby mode to a run mode can involve a re- addressing operation implicit in the change in the modes of operation. Also, a power turn on condition or a reset condition can involve a re-addressing operation implicit in the startup or initialization processing that is to be performed. In various configurations, a mode change can imply a change in the memory address MSBs and hence possible, or probable, or certain re-addressing operation. Certain-type modal changes typically can be used to invoke re- addressing. Probable-type or possible-type modal changes can also be used to invoke re-addressing. For example, in a display system having a plurality of images each being stored in a different one or ones of the blocks of memory; an image change can imply certain re-addressing. Also, in a display system having a plurality of images being stored in a plurality of the blocks of memory but having at least portions of different images stored in the same block of memory; an image change can imply probable or possible re-addressing. Also, in a television system having a plurality of scanlines each being stored in a different one or ones of the blocks of memory; a scanline change can imply certain re- addressing. Also, in a television system having a plurality of scanlines being stored in a plurality of the blocks of memory but having at least portions of different scanlines stored in the same block of memory; an scanline change can imply probable or possible re-addressing. Also, in a microprocessor system having a plurality of program routines each being stored in a different one or ones of the blocks of memory; transfer from one program routine to another program routine can imply certain re-addressing. Also, in a microprocessor system having a plurality of program routines being stored in a plurality of the blocks of memory but having at least portions of different program routines stored in the same block of memory; transfer from one program routine to another program routine can imply probable or possible re-addressing. Also, in an array processor system having a plurality of arrays each being stored in a different one or ones of the blocks of memory; an array change can imply certain re-addressing. Also, in an array processor system having a plurality of arrays being stored in a plurality of the blocks of memory but having at least portions of
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different arrays stored in the same block of memory; an array change can imply probable or possible re-addressing. Also, in a database system having a plurality of database pages each being stored in a different one or ones of the blocks of memory; a database page change can imply certain re-addressing. Also, in a database system having a plurality of database pages being stored in a plurality of the blocks of memory but having at least portions of different database pages stored in the same block of memory; a database page change can imply probable or possible re-addressing. Also, in a filter system having a plurality of input signals or reference signals each being stored in a different one or ones of the blocks of memory; a signal change or a reference change can imply certain re- addressing. Also, in a filter processor system having a plurality of signals or references being stored in a plurality of the blocks of memory but having at least portions of different signals or references stored in the same block of memory; a signal or reference change can imply probable or possible re-addressing. Also, in a signal processor system having a plurality of signals each being stored in a different one or ones of the blocks of memory; a signal change can imply certain re-addressing. Also, in a signal processor system having a plurality of signals being stored in a plurality of the blocks of memory but having at least portions of different signals stored in the same block of memory; a signal change can imply probable or possible re-addressing. Also, in a DMA system having information being stored in different blocks of memory; a new DMA transfer being invoked can imply certain re-addressing. Also, in a DMA system having information being stored in a plurality of the blocks of memory but having at least portions of the information stored in the same block of memory; a DMA transfer being invoked can imply probable or possible re-addressing. Also, in an artificial intelligence system having a plurality of inferences each being stored in a different one or ones of the blocks of memory; an inference change can imply certain re-addressing. Also, in a cache memory system having a plurality of pages each being stored in a different one or ones of the blocks of memory; a page change can imply certain re-addressing. Particular implementations of modal deteαors will now be discussed for a display configuration with reference to Fig 6W. These Fig 6W discussions are illustrative of many other types of modal detectors and are illustrative of many other applications of modal deteαors (i.e.; display application, television application, stored program processor application, array processor application, signal processor application, filter processor application, DMA application, cache memory application, artificial intelligence application, and database processor application).
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Fig 6C, which is similar to Fig 6W, is discussed in detail herein. Three primary changes have been made to Fig 6C to arrive at Fig 6W. First, gate U13A-6 has been changed from an AS20 4-input NAND gate to an AS30 eight input NAND gate having modal deteαor inputs F1 *, F2*, F3*, and F4* to new pins 3, 6, 1 1, and 12. Second, flip-flops U23C and U21 B have been changed from flip-flops not having a set input (74LS174 flip-flops) to flip-flops K1, K2, and K3 having a set input S D * (i.e., 74LS74 flip-flops). Third, the RUN signal U13A- 8 is shown input to set inputs Sp* of flip-flops Kl , K2, and K3. 74LS174 flip-flops implement a clear circuit MR* (Fig 6C) and not a set circuit Sp*. Alternately, it is convenient for this example to use flip-flops having set circuits Sp* (Fig 6W). Such set circuits Sp* are well known in the art, as used on LS74 flip-flops. Gate AS30 has modal deteαor inputs F1 *, F2*, F3*, and F4* to new pins 3, 6, 1 1, and 12 to supplement overflow deteαor inputs to pins 1, 2, 4, and 5. If any one or more of the deteαor inputs, including modal inputs and overflow deteαor inputs, to the pins of NAND gate AS30 goes low; then re-addressing operations will be invoked until the last of the deteαor inputs; either modal deteαor inputs, or overflow deteαor inputs, or other inputs; again goes high. The state of the modal signal can be changed with an inverter, such as the inverter in the modal deteαor signal F1 line, so that a high modal signal (instead of a low modal signal) will invoke re-addressing operations. Also, a one-shot circuit can be used to generate a short re-addressing command pulse in response to a deteαor signal level. See the one-shot circuit in modal deteαor signal line F2*. For example, if the F3* modal deteαor signal goes low and remains low for a period of time, such as for a mode period; then (in the Fig 6W configuration) re-addressing is continuously invoked until the F3* modal deteαor signal again goes high. However, if the F2* modal deteαor signal goes low and remains low, then the one-shot circuit in the F2* signal line causes a relatively short pulse to be generated to invoke a single re-addressing operation independent of the amount of time that the F2 * signal remains low. Various types of one-shot circuits can be used. For example, the 74LS221 monostable multivibrator can be used as a one-shot circuit to generate a single output pulse in response to an input level. Also, a synchronous one-shot circuit, such as shown in Fig 6X, can be used to generate a short synchronous output pulse 632B and 632C in response to an input signal 632D. This synchronous one-shot circuit 632A generates a positive level transition output pulse 632B in response to the input signal 632D making a transition from a low signal level to a high signal level and generates a negative level transition output pulse 632C in
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response to the input signal 632D making a transition from a high signal level to a low signal level. One-shot circuit 632A shifts input signal 632D first into flip- flop 632G on a first clock pulse and then into flip-flop 632F on a second clock pulse. Following input signal 632D going high, the transitionary condition of flip-flop 632G being set and flip-flop 632F being reset after occurrence of said first clock pulse is detected by gate 632E. Following input signal 632D going low, the transitionary condition of flip-flop 632G being reset and flip-flop 632F being set after occurrence of said first clock pulse is deteαed by gate 632F. LSOO NAND gates 632E and 632F are shown in the output of one-shot circuit 632A to generate negative going output pulses to be consistent with the logic of the AS30 NAND gate (Fig 6W). Alternately, LS08 AND gates can be used in place of the LSOO NAND gates in the output of one-shot circuit (Fig 6X) to generate positive going output pulses for a deteαor circuit using a high signal level to invoke re-addressing. Such one-shot circuits are further disclosed in the referenced patent applications. Further, one skilled in the art will readily understand the operation thereof from the schematic diagram in Fig 6X and the discussion of operation supra. The RUN signal U13A-8 is shown input to the set inputs of flip-flops K1, K2, and K3 so that the RUN signal will set flip-flops Kl, K2, and K3 when low and will permit normal flip-flop operation when high. Because the RUN signal sets flip-flops K1 , K2, and K3 when low; flip-flops K1, K2, and K3 are in the set state when the RUN signal first goes high. Flip-flops Kl, K2, and K3 being set implies a re-addressing operation, similar to an overflow signal to pins 1 , 2, 4, or 5 of NAND gates U13A-6 and AS30 being in the low state when an overflow is deteαed. Hence, inputting of a normally high modal signal to the set inputs of flip-flops K1 , K2, and K3 invokes a re-addressing operation for the first operation after the modal signal goes high. Similarly, a plurality of normally high modal signals can be ANDed together and input to the set input of flip-flops K1 , K2, and K3 so that any one or more of these ANDed signals going low will invoke a re-addressing operation when all of these ANDed modal signals again become high. Similarly, a one-shot circuit can be used to set flip-flops K1, K2, and K3; such as by generating a negative going pulse in response to a positive level transition or a negative going transition supra. Other logical arrangements will permit other combinations of modal signals to set flip-flops Kl , K2, and K3 in response to a modal signal implying re-addressing. Alternately, the RUN signal U13A-8 is shown input to the F3* input of NAND gate AS30 so that the RUN signal will invoke re-addressing operations when low and hence will enter the run mode with a re-addressing operation.
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Because the RUN signal to F3* causes flip-flops Kl, K2, and K3 to be set through the D input pins when low; flip-flops Kl, K2, and K3 are in the set state when the RUN signal first goes high. Flip-flops Kl, K2, and K3 being set implies a re- addressing operation, similar to an overflow signal to pins 1, 2, 4, or 5 of NAND gates U13A-6 and AS30 being in the low state when an overflow is deteαed. Hence, inputting of a normally high modal signal (i.e., RUN) to NAND gate AS30 invokes a re-addressing operation for the first operation after the modal signal goes high. Similarly, a plurality of normally high modal signals can be ANDed together and input to NAND gate AS30 so that any one or more of these ANDed signals going low will invoke a re-addressing operation when all of these ANDed modal signals again become high. Similarly, a one-shot circuit can be used to generate a modal deteαor signal (i.e., RUN) to NAND gate AS30, such as the one-shot circuit associated with the F2* deteαor signal generating a negative going pulse in response to a positive level transition of a modal signal (i.e., RUN) or a negative going transition of a modal signal (i.e., RUN) supra. Other logical arrangements will permit other combinations of modal signals to invoke re-addressing.
Time Available Deteαor Circuits Time available deteαor circuits can be implemented as an alternate to or in addition to overflow deteαor circuits, comparitor deteαor circuits, anticipatory deteαor circuits, modal deteαor circuits, and other deteαor circuits. For example, in a time available deteαor configuration; a memory re-addressing operation may not aαually be deteαed but may be executed because time is available for performing a re-addressing operation. Such time-available memory address operations can provide important advantages, such as enhancing performance. A time available deteαor can be implemented by deteαing a time available condition, such as modal condition having time available or an instruαion execution condition having time available, to invoke memory addressing operations, such as independent of whether addressing is necessary or alternately by determining that addressing is necessary. For example, the RUN signal U13A-8 is generated to enable gating of clock signals with gates U12A-6 and U12A-8; where the RUN signal being low is indicative of a time that memory operations are not being invoked for displaying pixels and hence time may be available for memory refreshing and memory re-addressing. Certain modal signals described herein for invoking a modal deteαor can also implement a time available modal deteαor.
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A time available deteαor arrangement can be implemented in a microprocessor, in a display processor, in a filter processor, in a database processor, in an artificial intelligence processor, or in other processors. It is particularly appropriate for implementation in high speed memory applications because scanout and re-addressing in response to aαual deteαion of a suitable memory condition can provide higher performance than normal RAS* and CAS* addressing and because time available deteαion can provide higher performance than aαuai deteαion. Time available deteαors generate an addressing time available signal in response to deteαion of time being available for memory operations, such as memory re-addressing operations. For example; various time available memory refresh deteαors are discussed herein, which discussions are also applicable to time available memory re-addressing deteαors. These time available memory refresh deteαors generate time available memory refresh deteαor signals to control memory refresh operations. Also; various modal deteαors are discussed herein, which discussions are also applicable to time available memory addressing deteαors. These modal deteαors generate modal signals, many of which may have time available and hence may be charaαerized as time available deteαors generating deteαor signals to control memory addressing operations. Time available memory refresh deteαors, such as disclosed herein, can be used as time available addressing deteαors for memory addressing by generating time available addressing deteαor signals to invoke memory operations, such as memory re-addressing operations, in addition to or in place of generation of time available memory refresh deteαor signals. Also, time available memory refresh deteαor signals can be used to invoke memory operations, such as memory re- addressing operations, cotemporaneously or concurrently with memory refresh operations because the memory address register may be available for memory addressing operations, such as memory re-addressing operations, during memory refresh operations, such as in applications where the memory refresh address is being used to control the memory during memory refresh operations. For example, a time available memory refresh deteαor signal may be input to the F4* input or to the F2* one-shot input of the overflow deteαor circuit (Fig 6W) to invoke a memory re-addressing operation concurrently with a refresh operation if a memory refresh operation is invoked or independent of a refresh operation if a memory refresh operation is not invoked. The image memory line sync pulse memory refresh deteαors and the image memory field sync pulse memory refresh deteαors are discussed herein. Also
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discussed herein is a line sync memory refresh deteαor that deteOs a seleαed portion of a line sync pulse, the leading portion of a line sync pulse in this illustration. Alternately, the image memory line sync pulse memory refresh deteαors may be implemented as image memory line sync pulse time available memory re-addressing deteαors for generating line sync pulse time available memory re-addressing signals to invoke memory re-addressing; the image memory field sync pulse memory refresh deteαors may be implemented as image memory field sync pulse time available memory re-addressing deteαors for generating field sync pulse time available memory re-addressing signals to invoke memory re-addressing; and the image memory line sync pulse time available memory refresh deteαors that deteα a seleαed portion of a line sync pulse, the leading portion of a line sync pulse in this illustration may be implemented as image memory line sync pulse leading edge time available memory re-addressing detectors for generating field sync pulse leading edge time available memory re-addressing signals to invoke memory re-addressing. A stored program computer time available memory addressing deteαor can be implemented to perform memory addressing operations, such as to perform memory re-addressing on a time shared basis with program operations. For example, an instruction deteαor can be used to deteα instruαions or portions of instruαions that are suitable for memory re-addressing operations. In a micro- programmable computer, micro-instruαions can be implemented to generate memory re-addressing deteαor signals to invoke a memory re-addressing operations and/or memory refreshing operations. In other computers, states can be implemented to generate memory re-addressing deteαor signals to invoke memory re-addressing operations and/or memory refreshing operations. Time available memory addressing deteαors that are responsive to execution of a computer instruαion can be implemented by deteαing a suitable portion of an instruαion execution period, such as deteαing seleαed micro-operations of an instruαion, that are indicative of computer operations that do not use main memory for an appropriate period of time in order to invoke a memory addressing operation during that period of time. For example, an instruαion that processes a register operand, such as an instruαion that adds a register operand to the accumulator, may have to access an instruαion from main memory (as with an instruαion that adds a memory operand to the accumulator) but may not have to access an instruαion from main memory. Hence, an instruαion that processes a register operand may have time to invoke a memory re-addressing operation in place of the memory operand access that is not needed for such an instruαion. Other instruαions may have an instruαion execution micro-
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operation that does not access main memory and hence leaves time available for memory re-addressing. For example, an add instruαion may have an add instruαion execution micro-operation that does not access main memory and hence leaves time available for memory re-addressing. Also, certain instruαions may have significantly longer instruαion execution micro-operations, such as multiple and divide instruαions which may have eight or sixteen instruαion execution micro-operations that do not access main memory and hence leaves time available for memory re-addressing. See the related application Serial No. 101,881 and see Patent No. 4,371,923 for computer micro-operation disclosures; such as Figs 5A and 5B and the discussion related thereto. For example, these disclosures discuss main memory resident operand instruαions, discuss scratch pad memory resident operand instruαions, and discuss micro- operations related thereto. A stored program computer can implement time available memory addressing operations, such as implementing memory re-addressing and memory refresh operations on a time shared basis with stored program operations. For example, an instruαion deteαor can be used to deteα instruαions or portions of instruαions that are suitable for memory addressing operations, including memory re-addressing operations and memory refresh operations. Various stored program computer configurations will now be discussed with reference to the computer disclosed in related patent application Serial No. 101,881 and related Patent No. 4,371,923; particularly with reference to Figs 5A and 5B therein and the discussions related thereto disclosing a microprogram having micro-instruαions or micro-operations. Time available memory addressing deteαors that are responsive to execution of a computer instruαion can be implemented by deteαiπg a suitable portion of an instruαion execution period, such as deteαing seleαed micro-operations of an instruαion, that are indicative of computer operations that do not use main memory for an appropriate period of time in order to invoke a memory addressing operation during that period of time. For example, a group B instruαion processes a register operand, such as a DS add instruαion that adds a register operand to the accumulator, accesses the DS instruαion from main memory (as with a DP instruαion that adds a memory operand to the accumulator) but accesses an operand from a scratch pad register and hence does not have to access an operand from main memory. Hence, an instruαion that processes a register operand (i.e.; the group B instruαions) may have time to invoke a memory re-addressing operation and/or a memory refreshing operation in place of the memory operand access that is not needed for such an
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-59- instruαion. Other instruαions may have an instruαion execution micro- operation that does not access main memory and hence leaves time available for memory re-addressing. For example, the DP add instruαion has the FT add micro-operation that does not have a main memory access and hence leaves time available for memory re-addressing and memory refresh operations. Micro-operation signals can be generated by micro-operation logic, such as defined by the micro-operation signals in Table III of related patent application Serial No. 101,881 and related Patent No. 4,371,923. These micro-operation signals can be combined; such as shown with the P29, P30, P31, P39, P40, and P41 terms in Table II therein; to combine the micro-operation signals that are suitable for invoking memory operations. For example, micro-operation signals FY, FT, FU, FV, FW, FX, FAQ, FAB, FAC, FAD, and FAE; word-1 micro- operations having 16-bit times; can be logically combined FY + FT + FU + FV + FW + FX + FAQ + FAB + FAC + FAD + FAE to generate a time available deteαor signal to invoke memory re-addressing and memory refreshing operations. It may be desirable to inhibit retriggering, such as in a slower computer having relatively long micro-operation periods, and to insure completion of the memory operation cycle, such as in a faster computer having relatively short micro-operation periods. Retriggering can be inhibited with various circuits, such as with signal F2* having a one-shot circuit conneαed thereto (Fig 6W). Completion of a memory operation cycle can be insured with various circuits; such as with the K1, K2, and K3 flip-flop circuits (Fig 6W) that insure that the memory re-addressing cycle is completed before scanout operations are resumed. Certain micro-operations are particularly suitable for performing auxiliary memory operations, such as re-addressing and refreshing. For example; the FA, FB, and FC micro-operations of related patent application Serial No. 101,881 and related Patent No. 4,371,923 are particularly suited for memory refreshing operations because they constitute all of the word-0 micro-operations, because not one of these operations use the memory, and because each instruαion executed invokes one of these micro-operations. Because the FA, FB, and FC micro-operations constitute all of the word-0 micro-operations and because not one of these operations use the memory, the logic to invoke refreshing is simply the word-0 (W0) logical signal. Because each instruαion executed invokes one of the FA, FB, and FC micro-operations; refreshing is insured on a regular iterative basis. Various stored program computer configurations will now be discussed with reference to the Motorola 68HC11 single chip microcomputer; particularly with
reference to Seαion-5 of the Motorola 68HC11 Programmer's Reference Manual. An instruαion execution cycle having time available is indicated with the symbol $FFFF in the "Address Bus" column and with the term "Irrelevant Data" in the "Data Bus" column. Many of the 68HC11 instruαions have one time available cycle; some of the 68HC11 instruαions have two time available cycles; the MUL 68HC11 instruαion has eight time available cycles; and the FDIV and the IDIV 68HC11 instruαions have 39 time available cycles. Each cycle represents 500-ns in the 2-MHz version of the 68HC11. 500-ns should be sufficient for one or more refresh operations involving up to 200-ns each and should be sufficient for a re-addressing operation involving 250-ns or less. Hence, there is usually a considerable amount of time available during instruαioπ execution in the 68HC11 microprocessor. The cycle logic in the 68HC11 is implemented on-the-chip. One skilled in the computer art reviewing the logical design of the 68HC11 microcomputer will find logical signals that can be logically combined with digital logic to uniquely define the cycles to be used for time available processing. For example; various signals can be combined, such as with AND gates, to form micro-operation signals (i.e., the cycle-4 signal and the MUL instruαion) and the micro-operation signals can be logically combined, such as with OR gates, to form the deteαor signal that can be used to invoke the auxiliary memory operations, such as memory re-addressing and memory refreshing. The logical equations disclosed in the related patent application Serial No. 101,881 and related Patent No. 4,371,923 show how to combine various signals, such as with AND gates, to form micro-operation signals (i.e., the FAC micro-operation signal) and the micro-operation signals can be logically combined, such as with OR gates, to form memory deteαors signal that can be used to invoke auxiliary memory operations. Certain instruαions are arithmetic and logic unit (ALU) intensive in the 68HC11 and consequently have a significant of time available. For example, the MUL 68HC11 instruαion has eight time available cycles and the FDIV and the IDIV 68HC11 instruαion has 39 time available cycles. Consequently, such ALU intensive instruαions can provide extensive memory refreshing capability. For example, the 39 FDIV and IDIV time available can permit up to 100 refresh cycles to be performed, which can be 20% of the refresh requirements for an 8- ms period for the Toshiba DRAMs discussed herein. The micro-operations in the 68HC11 can provide anticipatory micro- operation signals for memory re-addressing and memory refreshing; as discussed under anticipatory deteαor circuits herein.
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A direα memory access (DMA) memory addressing deteαor can be implemented to invoke memory operations, such as re-addressing operations, on a time available basis in a DMA configuration that is suitable for time available memory re-addressing. For example, as discussed herein for memory refreshing; a DMA controller can have a separate DMA address register (just as many types of DRAMs have a separate refresh address register) and hence, during DMA operations using the DMA address register to address memory, the processor address register may be available for a time available re-addressing operation. A cache memory addressing detector can be implemented to invoke memory operations, such as re-addressing operations, on a time available basis in a cache memory configuration that is suitable for time available memory re-addressing. For example, as discussed herein for memory refreshing; a cache memory controller can have a separate cache memory address register (just as many types of DRAMs have a separate refresh address register) and hence, during cache memory operations using the cache memory address register to address memory, the processor address register may be available for a time available re-addressing operation. A filter processor, signal processor, or array processor memory re-addressing deteαor can be implemented to invoke memory addressing operations, such as memory re-addressing operations, on a time available basis in a filter processor, signal processor, or array processor configuration that is suitable for time available memory re-addressing. For example, if the processing operations are associated with one of a plurality of memories; then a memory not having processing operations at the particular time can be re-addressing at that time. Also, if the processing operations are relatively slower than memory speed; then a filter processing, signal processing, or array processing re-addressing deteαor can be implemented to deteα the time available inbetween processing operations to invoke re-addressing operations. For example; filter processing, signal processing, or array processing of input information may receive and process and store one input sample each microsecond. However, the above- described Toshiba DRAM may be able to store that input sample in 50-ns using the fast page scanout addressing mode. Hence, 950-ns may be available for DRAM re-addressing. An artificial intelligence processor memory re-addressing deteαor can be implemented to invoke memory addressing operations, such as memory re- addressing operations, on a time available basis in a artificial intelligence processor configuration that is suitable for time available memory re-addressing. For example, if the processing operations are associated with one of a plurality
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of memories; then a memory not having processing operations at the particular time can be re-addressing at that time. Also, if the processing operations are relatively slower than memory speed; then a artificial intetfigerrce-proeess-tπg re- addressing deteαor can be implemented to deteα the time available inbetween processing operations to invoke re-addressing operations. For example; artificial intelligence processing of inference information may process an inference operation each microsecond. However, the above-described Toshiba DRAM may be able to store the inference parameter in 50-ns using the fast page scanout addressing mode. Hence, 950-ns may be available for DRAM re-addressing. A display processor memory re-addressing deteαor can be implemented to invoke memory addressing operations, such as memory re-addressing operations, on a time available basis in a display processor configuration that is suitable for time available memory re-addressing. For example, if the processing operations are associated with one of a plurality of memories; then a memory not having processing operations at the particular time can be re-addressing at that time. Also, if the processing operations are relatively slower than memory speed; then a display processing re-addressing deteαor can be implemented to deteα the time available inbetween processing operations to invoke re- addressing operations. For example, display processing of pixel information may access and process and store one display pixel each microsecond. However, the above-described Toshiba DRAM may be able to store that input sample in 50-ns using the fast page scanout addressing mode. Hence, 950-ns may be available for DRAM re-addressing. Primary memory operations (i.e., non-refresh memory operations) may not be performed for various types of modal conditions. Hence, these various types of modal conditions, such as the RUN modal condition discussed herein, may also be considered to be time available conditions. Consequently; modal deteαor circuits related to these modal time available conditions may be considered to be time available deteαor circuits in addition to being modal deteαor circuits and may be considered to generate time available deteαor signals in addition to generating modal deteαor signals.
Programmable Detector Circuits A programmable deteαor can be implemented to deteα a re-addressing condition or a refreshing condition under program control and to invoke re- addressing and/or refreshing operations. For example, a deteαion program can be a software program, such as stored in RAM; a firmware program, such as stored in ROM; a microprogram, such as implemented in a micro-programmable
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processor; or other program. The deteαor can be programmed in various ways; such as using a compiler or other higher level language, an assembler, or direαly in machine code by a programmer. It can implement auxiliary memory operation strategy, such as a refresh strategy and a re-addressing strategy. For example, programming of a long branch or a long jump instruαion can be used to invoke re-addressing and programming 'of an ALU intensive instruαion, such as a multiply or a divide instruαion, can be used to invoke re-addressing and refreshing, such as discussed with reference to the 68HC1 1 microcomputer herein. Also, an address change across a block boundary can be used to invoke a re-addressing operation. One example disclosed herein uses a microprogram in a stored program processor for generating a deteαor signal in response to execution of an instruαion having time available for auxiliary memory operations, such as re- addressing and refreshing. This deteαor signal can be generated on an anticipatory basis or a non-anticipatory basis. Another example is a microprogram having a micro-instruαion bit or bits that can be set for invoking auxiliary memory operations at the appropriate times. Still another example is a stored program computer having instruαions for invoking auxiliary memory operations under program control. For example, the computer disclosed in said related application Serial No. 101,881 and in said Patent No. 4,371 ,923 can execute a discrete output instruαion to invoke auxiliary memory operations and can execute a micro-operation to invoke memory auxi I iary operations.
Retriggerable Deteαor Circuits Memory deteαor circuits can be implemented in various configurations, such as retriggerable deteαor circuits and such as non-retriggerable deteαor circuits. The re-addressing arrangement shown in Figs 6C and 6W may be considered to be a retriggerable re-addressing circuit. This is because; if an overflow condition is deteαed during a previously invoked re-addressing operation with one or more of gates U16A-3, U16A-6, U17A-3, and U17A-6; these gates will invoke another re-addressing operation. Similarly; if multiple continuous overflow conditions are deteαed during multiple continuous re-addressing operations with one or more of gates U16A-3, U16A-6, U17A-3, and U17A-6; these gates will continue to invoke re-addressing operations until the multiple continuous overflow conditions are concluded. Hence, a continuous sequence of re-addressing operations can be accommodated with such an overflow arrangement.
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In certain deteαor configurations; it may be desirable to implement a non- retriggerable addressing deteαor circuit. One reason is that it may be desirable to complete a memory addressing operation before the end of a deteαed condition so that the addressing operation will be completed before the end of the deteαed condition. For example, in the arrangement shown in Fig 6W; the modal RUN signal will invoke a re-addressing operation when deteαed as going low (the RUN* condition) by setting flip-flops Kl, K2, and K3 in sequence to facilitate a time delay for re-addressing operations. However, if the RUN signal remains low after the re-addressing operation has been completed, the circuit shown in Figs 6C and 6W will retrigger thereby initiating another re-addressing operation. This may be desirable for an overflow deteαor and invoking circuit, where multiple overflow conditions can occur in sequence, but this may be undesirable for a modal or a time-available deteαor and invoking circuit, where multiple re-addressing operations may be redundant and unnecessary. Retriggering of the circuit of Fig 6W can be inhibited by various circuit features. For example, use of a one-shot (i.e., see the F2* deteαor signal line and the discussion related thereto) can inhibit retriggering. The one-shot shown in Fig 6W can generate a leading edge pulse to initiate a re-addressing operation at the beginning of the deteαor signal (i.e., the F2* signal) to invoke re-addressing. Hence, assuming that the deteαor signal (i.e., the F2* signal) is longer than the re-addressing period and assuming that the duration of the one-shot output signal (AS30-11) is long enough to facilitate triggering and short enough to prevent retriggering (i.e., two CPE clock periods); re-addressing operations can be concluded before the end of the deteαor signal (i.e., the F2* signal) and hence facilitate higher performance. Xonversely, if retriggering is permitted, then the invoking circuit (Fig 6W) will retrigger until the end of the deteαor signal (i.e., the F2* signal), which can result in a re- addressing delay continuing beyond the deteαor signal (i.e., the F2* signal) and hence causing lower performance. Other circuits can be used to compensate for retriggering. For example, a memory addressing deteαor and invoking circuit can be configured to invoke one memory addressing operation, such as a memory re-addressing operation, and then to lockup, such as with the feedback signal U21 E-8 which resets the re- addressing time delay flip-flops K2 and K3 feeding back to disable the deteαor signal until the deteαor signal concludes and resets the time delay flip-flops K2 and K3. The circuit shown in Figs 6C and 6W can readily be modified by one skilled in the logical design art to implement such a lockup. For example, feedback signals U21 E-8 that resets flip-flops K2 and K3 can be removed to
disable retriggering; the clock gating signal to U4A and U4B can be generated for only a single period of time, such as during the period that flip-flop Kl is high and flip-flop K3 is low as can be deteαed with an AND gate of a NAND gate; and the deteαor signal can be logically processed to reset the K2 and K3 flip- flops at the end of the detector signal period, such as during the period that flip- flop Kl is low and flip-flop K3 is high. Alternately, the circuits associated with flip-flops Kl, K2, and K3 can be replaced with a monostable multivibrator; such a 74LS122 or a 74LS123 retriggerable monostable multivibrator for implementing a retriggerable memory addressing deteαor and invoking circuits and such as a 74LS221 non- retriggerable monostable multivibrator for implementing a non-retriggerable memory addressing deteαor and invoking circuits.
Seleαion Circuits Memory deteαor circuits are discussed herein for deteαing changes in the MSBs of an address, such as for invoking memory re-addressing operations. Seleαing, or partitioning or separating, the MSBs for re-addressing and the LSBs for scanout is shown in Figs 4H to 4K and is disclosed elsewhere herein. In various applications, it may be desirable to seleα the group of address MSBs that are used for invoking memory operations, such as for invoking memory re- addressing. Also, in various applications, it may be desirable to seleα the modes, time available conditions, etc. that are used for invoking memory operations, such as for invoking memory re-addressing. Also, in various applications, it may be desirable to seleα the group of address MSBs, the modes, the time available conditions, etc. that are used for invoking memory operations, in a convenient manner; such as by loading a configuration register with a parameter that automatically selects the group of address MSBs, the modes, the time available condition, etc. Two configurations for automatically seleαing the group of address MSBs that are used for the invoking memory operations will now be discussed with reference to Fig 4N for an overflow deteαor configuration that generates a plurality of overflow deteαor signals for seleαion of the desired deteαor signal and with reference to Fig 40 for a comparitor deteαor configuration that selects the address MSBs to be processed by the comparitor. These two configurations are illustrative of seleαion of other deteαors; such as anticipatory deteαors, modal detectors, time available deteαors, retriggerable and non-retriggerable deteαors, etc. and these two configurations are illustrative of other selection circuits for seleαing the address MSBs, the mode, the time available, etc.
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The seleαor circuits disclosed herein are particularly applicable to systems that need to change the memory deteαor configuration and to systems having an address generator that is not readily rewired, such as an IC chip or a PC board having the address generator contained thereon. In one configuration, it may be desirable to change the type of DRAM chips used in the system and hence it may be desirable to conveniently change the memory architeαure without rewiring to adapt to the new type of DRAM chips. For example, the Fig 4H configuration using by-1 DRAM chips has ten CAS column address bits and has ten RAS row address bits and the Fig 4J configuration using by-4 DRAM chips has nine CAS column address bits and has nine RAS column address bits. Hence, a memory architeαure using by-1 DRAM chips and optionally using by-4 DRAM chips (and not having external scanout as shown in Figs 4H to 4K to extend the scanout addressing circuits) may have to seleα either MSBs Al 0 to Al 9 for by-1 DRAMs and may have to seleα MSBs A9 to Al 7 for by-4 DRAMs. In another configuration, it may be desirable to change the amount of memory and hence to change the number of DRAM chips used in the system. This may involve changing the external scanout circuitry and hence it may be desirable to conveniently change the memory architeαure without rewiring. For example, the second and third Fig 4H configuration is disclosed as having 8- million words, ten internal scanout address bits, three external scanout address bits; indicating an overflow from the thirteenth address LSB. Alternately, for an example of a minimum memory architeαure, the second and third Fig 4H configurations can be adapted to having 1 -million words; involving ten internal scanout address bits and no external scanout address bits; indicating an overflow from the tenth address LSB. Alternately, for an example of a maximum memory architeαure, the second and third Fig 4H configurations can be adapted to having 32-million words; involving ten internal scanout address bits and five external scanout address bits; indicating an overflow from the fifteenth address LSB. Consequently, in this example; it is desirable to be able to seleα an overflow from the tenth to the fifteenth address LSBs. The seleαion configuration shown in Fig 4N includes an adder 450A for adding address parameters having a plurality of overflow deteαors for generating overflow deteαor signals 450B to invoke memory operations, a configuration register 450G for storing a configuration parameter, a decoder 450N for generating configuration control signals, and a seleαor 450D for seleαing one of the deteαor signals 450B as seleαed deteαor signal 450E to be used for invoking memory operations. Alternately, a seleαion configuration can be
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implemented with an address counter (in place of adder 450A) for counting to update an address parameter having a plurality of counter carry signals from counter stage to counter stage provided as overflow deteαor signals 450B for invoking memory operations, can be implemented with a configuration latch (in place of register 450G) for storing a configuration parameter, or can be implemented with other circuits. Many other alternate overflow deteαor seleαion configurations can be implemented from the teachings herein. Adder 450A can be implemented with 74LS183 dual adder circuits in place of the 74LS283 quad adder circuits disclosed in Figs 60 to 6R because, for the seleαion arrangement shown in Fig 4N, it may be desirable to have access to the carry from each stage, which carry signals from each stage are available with said 74LS183 dual adder circuit but are not available with said 74LS283 quad adder circuit. Configuration register 450G stores a configuration parameter for decoding with decoder 450N to generate configuration control signals 450P, 450Q, and 450R for seleαing one of the overflow deteαor signals 450B to generate the seleαed overflow deteαor signal with multiplexer 450D. Configuration register 450G can be implemented with a 74LS174 hex flip-flop circuit. It can be loaded under program control, under operator control, or under other control methods for seleαing the overflow signal. Configuration decoder 450N can be implemented with a 74LS138 decoder circuit. Seleαor 450D can be implemented with a 74LS151 multiplexer circuit for permitting the seleαed one of overflow signals 450B to pass through as signal 450E and for inhibiting the overflow signals 450B that are non-seleαed. Fig 4N shows eight overflow deteαor signals for simplicity of discussion. However; configuration register 450G and decoder 450N, adder 450A, and multiplexer 450D can readily be reduced or expanded to accommodate five, six, eight, sixteen, sixty-four, or other number of overflow deteαor signals. For configurations having less re-addressing MSBs; the reduαion in re-addressing MSBs is offset by the increase in scanout LSBs. The seleαion configuration shown in Fig 40 corresponds to the comparitor deteαor configurations shown in Figs 4D and 4E with the addition of seleαor circuits 451 H, 4511, and 451J inserted in the next address bit lines and seleαor circuits 451 K, 451 L, and 451 M inserted in the prior address bit lines operating under control of configuration register 450G and decoder 450N. MSB address register 414 corresponds to address register 414 (Fig 4D) and corresponds to buffer register 414A (Fig 4E). It loads address signals 451C corresponding to
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address signals 421 A (Fig 4D) and corresponding to address signals 421 B (Fig 4E) and it generates address signals 451 D corresponding to address signals 421 B (Fig 4D) and corresponding to address signals 42 IC (Fig 4E). Comparitor 422 corresponds to comparitor 422 (Figs 4D and 4E) for generating output signal 423 (Figs 4D and 4E) to be used for invoking memory operations in response to the address signals 451 B corresponding to address signals 42 I B (Fig 4D) and corresponding to address signals 42 IC (Fig 4E) and in response to the address signals 451 F corresponding to address signals 421 A (Fig 4D) and corresponding to address signals 421 B (Fig 4E). Configuration register 450G stores a configuration parameter for decoding with decoder 450N to generate configuration control signals 450P, 450Q, and 450R for seleαing one of the groups of next address MSBs with next address seleαors 451 H, 4511, and 451J respeαively to generate the seleαed next address MSBs 451 F to comparitor 422 and for seleαing one of the groups of prior address MSBs with prior address seleαors 451 K, 451 L, and 451M respeαively to generate the seleαed prior address MSBs 451 B to comparitor 422. in Fig 40; the groups of next address MSBs and the groups of prior address MSBs have correspondence therebetween. For example, the group of next address MSBs seleαed by seleαor circuit 451 H under control of seleαion signal 451 P and the group of prior address MSBs seleαed by seleαor circuit 451 K under control of the same seleαion signal 451 P have the same MSB configuration, all four address MSBs seleαed for MSB comparison. Also, the group of next address MSBs seleαed by seleαor circuit 4511 under control of seleαion signal 451 Q and the group of prior address MSBs seleαed by seleαor circuit 451 L under control of the same seleαion signal 451 Q have the same MSB configuration, three address MSBs seleαed for MSB comparison. Also, the group of next address MSBs seleαed by seleαor circuit 451J under control of seleαion signal 451 R and the group of prior address MSBs seleαed by seleαor circuit 451 M under control of the same seleαion signal 451 R have the same MSB configuration, three address MSBs seleαed for MSB comparison. The ground signals on the corresponding address lines of corresponding groups of next address MSBs and prior address MSBs insure that these unused bits properly compare for the prior and next address MSBs. Fig 40 shows four MSB address bits for simplicity of discussion. However; configuration register 450G and decoder 450N, address register 414, seleαor circuits 451 H to 451 M, and comparitor 422 can readily be expanded to accommodate five, six, eight, sixteen, sixty-four, or other number of address MSBs. Also, for configurations having more scanout LSBs and less re-addressing
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MSBs (shown by the seleαors having grounded inputs); the reduαion in re- addressing MSBs is offset by the increase in LSBs and hence the address signals replaced by the grounded inputs are indicated to have been reassigned to scanout logic, such as by increasing the external scanout bits and/or increasing the internal scanout bits. Configuration register 450G can be implemented with a 74LS174 hex flip- flop circuit. Configuration register 450G can be loaded under program control, under operator control, or under other control methods for seleαing the overflow signal. Configuration decoder 450N can be implemented with a 74LS138 decoder circuit. Address register 414 can be implemented with a 74LS174 hex flip-flop circuit. Address seleαors 451 H, 4511, 451 , 451 L, and 451M can be implemented with 74LS365 tristate buffer circuits which are seleαed by signals from decoder 450N. In a configuration using a 74LS138 decoder and 74LS365 seleαor circuits, the decoder generates complement (NVL) output signals and the seleαor circuits use complement (NVL) input control signals.
Shared Address Register In various applications, an address register may be shared for addressing other circuits in addition to the memory being discussed. The other circuits, other than the memory being discussed (the subjeα memory), may include another memory (another memory circuit) or a plurality of other memories (other memory circuits) in a multiple memory configuration. Shared address register configurations that share the address register between the subjeα memory and such other circuits will now be discussed. Such other circuits may be dedicated to blocks of the address space that are different from the blocks of address space dedicated to the subjeα memory. Hence, it may not be necessary to generate re-addressing operations for the subjeα memory when accessing data from or storing data into another circuit. For example, the RAS row address in a DRAM of the subjeα memory is typically changed to access data from or store data into a DRAM location in a different block of subjeα memory supra. However, accessing data from or storing data into another circuit may not affeα the DRAMs of the subjeα memory and hence the DRAMs of the subjeα memory may not need to be re-addressed when accessing data from or storing data into another circuit. Similarly, when returning to operations in the subjeα memory after accessing data from or
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storing data into another circuit that is in another block of address space; it may not be necessary to re-address the subjeα memory for continuing operations in the subjeα memory in the same block that was addressed before the data was accessed from or stored into the other circuit. Conversely, when returning to operations in the subjeα memory after accessing data from or storing data into another circuit that is in another block of address space; it may be necessary to re-address the subjeα memory for continuing operations in the subjeα memory in a different block then was addressed before the data was accessed from or stored into the other circuit. In summary, it may not be necessary to re-address the subjeα memory when an intervening operation for another circuit sharing the address register of the subjeα memory is in a different block then with the prior operation of the subjeα memory and the continuing operation of the subjeα memory is in the same block as with the prior operation of the subjeα memory. However, it may be necessary to re-address the subjeα memory independent of whether there is an intervening operation sharing the memory address register when the continuing operation in the subjeα memory is in a different block then with the prior operation of the subjeα memory. Different memories may be memories that have separate re-addressing; such as different DRAMs having steered RAS signals and hence can be separately RAS re-addressed, different DRAMs having separate chip seleα signals and hence can be separately RAS re-addressed, and different memories having separate addressing struαures and hence can be separately re-addressed. Each of the plurality of memories may be in blocks of address space that is different from the blocks address space of the other memories. Hence, it may not be necessary to generate re-addressing operations in other memory circuits when accessing data from or storing data into the subjeα memory. For example, the RAS row address in a subjeα DRAM is typically changed to access data from or store data into a DRAM location in a different block of the subjeα DRAM. However, accessing data from or storing data into another DRAM having separate re-addressing may not affeα the subjeα DRAM and hence the subjeα DRAM may not need to be re-addressed when accessing data from or storing data into the other DRAM. Similarly, when returning to operations in the subjeα DRAM after accessing data from or storing data into the other DRAM that is in another block of address space; it may not be necessary to re-address the subjeα DRAM for continuing DRAM operations in the same block that was addressed before the data was accessed from or stored into the other DRAM. Conversely, when returning to operations in the subjeα DRAM after accessing data from or storing data into the
other DRAM that is in another block of address space; it may be necessary to re- address the subjeα DRAM for continuing operations in a different block in the subjeα DRAM then was addressed before the data was accessed from or stored into the other DRAM. In summary, it may not be necessary to re-address the subjeα DRAM when an intervening operation for another DRAM sharing the memory address register is in a different block then with the prior operation in the subjeα DRAM and the continuing operation in the subjeα DRAM is in the same block as with the prior operation of the subjeα DRAM. Further, it may be necessary to re-address the subjeα DRAM independent of whether there is an intervening operation sharing the memory address register when the continuing operation in the subjeα DRAM is in a different block then with the prior operation of the subjeα DRAM. Multiple memories can be implemented with scanout and re-addressing. Each memory can have its own detector for deteαing a re-addressing condition and each memory can have its own buffer register in the deteαor to store the prior address MSBs for subsequent operations following intervening of another one of the memories (i.e.; Figs 4C to 4E). An example of multiple memory operations will now be discussed in an improved computer embodiment. An ROM can be implemented as a main memory for storing a program and an RAM can be implemented as an operand memory to store operands under control of the program because operands cannot be stored in ROM because ROM is not alterable by the program. The ROM may not have RAS/CAS internal scanout and re-addressing capability but the RAM may have RAS/CAS internal scanout and re-addressing capability. Hence, use of scanout and re-addressing for the RAM can provide important performance enhancement, with or without use of scanout and re-addressing for the ROM. In this configuration, the ROM and the RAM may be considered to be different memories sharing the memory address register. A memory deteαor and delay circuit can be implemented for RAM operand accesses and RAM operand stores under control of the program stored in the ROM to enhance performance of RAM accesses and stores. A memory deteαor and delay circuit can be implemented for ROM instruαion accesses to enhance performance of the ROM in combination with the memory deteαor and delay circuit implemented for RAM operand accesses and RAM operand stores. Alternately, a memory deteαor and delay circuit need not be implemented for ROM instruαion accesses in combination with the memory deteαor and delay circuit implemented for RAM operand accesses and RAM operand stores. Examples of other circuits that can that share an address register with subjeα
memory will now be discussed for a stored program computer application. A memory address register may be used for addressing input and output circuits in addition to addressing RAM, such as with memory mapped input and output circuits that are included in the address space addressed by the computer address register. Further, a memory address register may be used for addressing ROM in addition to addressing RAM, such as with the computers having a ROM included in the address space addressed by the microprocessor address register. Also, a memory address register may be used for addressing a display image memory in addition to addressing RAM, such as with computers having a display image memory included in the address space addressed by the microprocessor address register. Also, a memory address register may be used for addressing a plurality of banks of memory each having a separate RAS addressing struαure and hence may be considered to be different memory. Examples of other devices and circuits that can share an address register with memory will now be discussed for a special purpose processor; such as a display processor, array processor, filter processor, signal processor, cache memory processor, artificial intelligence processor, or other application. A memory address register may be time shared for addressing input and output circuits in addition to addressing RAM. A memory address register may be used for addressing a ROM in addition to addressing main memory RAM. An address deteαor 432J (Fig 4E) for the subjeα memory can be implemented to generate an address deteαor signal 432 H for the subjeα memory (a) to enable scanout and re-addressing of the subjeα memory when an address of the subjeα memory that is inside the address space of the subjeα memory is generated by the address register and (b) to disable scanout and re- addressing of the subjeα memory when another address that is outside the address space of the subjeα memory is generated by the address register. For operations inside of the address space of the subjeα memory, scanout and re- addressing operations for the subjeα memory proceed as if the memory address register were not shared. For operations outside of the address space of the subjeα memory, scanout and re-addressing operations for the subjeα memory are disabled. For changes in operations from the address space of the subjeα memory to the address space of the other circuits, scanout and re-addressing operations for the subjeα memory are disabled. For changes in operations from the address space of the other circuits to the address space of the subjeα memory, scanout and re-addressing operations for the subjeα memory commence from where they were disabled when the memory operations changed from the address space of the subjeα memory to the address space of
the other circuits as if the operations of the subjeα memory had not been exited and as if the memory address register were not shared. For this latter example of changes in operations from the address space of the other circuits to the address space of the subjeα memory, (a) if the first continuing address in the address space of the subjeα memory is in the same block as the prior address stored in the buffer register representing the last block of operations before exiting the address space of the subjeα memory; then a scanout operation is invoked to maintain the same block of operations in the subjeα memory; and (b) if the first continuing address in the address space of the subjeα memory is in a different block compared to the prior address stored in the buffer register representing the last block of operations before exiting the address space of the subjeα memory; then a re-addressing operation is invoked to change blocks of the subjeα memory. If a shared memory address register configuration is implemented in accordance with the above, such as shown in Fig 4E; then operations in the subjeα memory will proceed as if the memory address register is not shared and without invoking extra re-addressing operations notwithstanding intervening operations outside the address space of the subjeα memory. For simplicity of discussion herein, the address space of the subjeα memory having scanout and re-addressing may be discussed as the subjeα memory address space, the subjeα memory addresses, and terms related thereto and the address space of the other circuits not having the subjeα memory scanout and re-addressing may be discussed as other memory address space, other memory addresses, and terms related thereto. Although other circuits may share the address register and the address space with the subjeα memory, such other circuits may not need to be implemented to share the subjeα memory and hence may not need to re-address the subjeα memory when the address register MSBs are changed to exit the address space of the subjeα memory in order to enter the address space of another circuit or when the address register MSBs are changed to exit the address space of another circuit in order to enter the address space of the subjeα memory or when the address register MSBs are changed between blocks of address space dedicated to other circuits. In such configurations, it may be desirable to disable the deteαor when addressing other circuits (including other memory circuits) that share the address space and the address register with the subjeα memory and to enable the deteαor when addressing the subjeα memory. Various deteαor enabling and disabling control circuits can be configured for enabling and disabling an overflow deteαor, a comparitor deteαor, an anticipatory deteαor, a modal deteαor, a time available deteαor, and other
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deteαors. Alternately, re-addressing circuitry, such as associated with the deteαor or the re-addressing invoking funαion, can be controlled for enabling and disabling of re-addressing operations. For example, in an overflow deteαor configuration (i.e., Fig 6C and 6W), an enable and disable control signal can be used to control overflow deteαion gates U16A-3, U16A-6, U17A-3, and U17A- 6; or to control flip-flop U23C-10; or to otherwise control the overflow deteαor and re-addressing circuitry. Similarly, in a modal deteαor configuration, a time available deteαor configuration, or an anticipatory deteαor configuration (i.e., Fig 6C and 6W), an enable and disable control signal (i.e., the RUN signal) can be used to control overflow deteαion gates U16A-3, U16A-6, U17A-3, and U17A-6 (not shown in Figs 6C and Fig 6W); or to control flip-flop K1 (i.e., Fig 6W); or to control flip-flops K2 and K3 (i.e.. Fig 6W); or to otherwise control a modal deteαor, a time available deteαor, or an anticipatory deteαor and re- addressing circuitry. Similarly, in a comparitor deteαor configuration (i.e., Figs 4D and 4E), an enable and disable control signal can be used to control comparitor 422 or to otherwise control the comparitor deteαor and re- addressing circuitry; as further discussed in the comparitor seαion herein. For example, as shown in Fig 4E; control signal 432H can be generated by logic 432J deteαing whether address signals 421 B are within the RAM address space or are outside of the RAM address space. Logic 432J can be implemented to generate address deteαor signal 432H to deteα when the address MSBs pertain to the RAM address space. Control signal 432H can be used to gate the 02 clock 432E with gate 432F to generate gated 02 clock 432G to seleαively control buffer register 414A. Also, control signal 432H can be used to control comparitor 422, such as to enable and disable comparitor ^ signal 423 for enabling auxiliary memory operations when in the RAM address space and for disabling auxiliary memory operations when not in the RAM address space. Other control circuits can readily be implemented; such as clock gating circuits, logical gates for enabling and disabling signals, and other control circuits. A re-addressing strategy will now be discussed with reference to Fig 4E. This re-addressing strategy can readily be implemented with circuitry in a hardware configuration (i.e., Fig 4E) and alternately with program instruαions in software or firmware configurations. A processor is implemented to share an address register having operations in the subjeα memory needing re-addressing and having operations in other circuits not needing re-addressing. An address deteαor 432J (Fig 4E) for the subjeα memory can be implemented to generate an address deteαor signal 432 H for the subjeα memory (a) to enable scanout and re-addressing of the
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subjeα memory when an address of the subjeα memory that is inside the address space of the subjeα memory is generated by the address register and (b) to disable scanout and re-addressing of the subjeα memory when another address that is outside the address space of the subjeα memory is generated by the address register. For operations inside of the address space of the subjeα memory, scanout and re-addressing operations for the subjeα memory proceed as if the memory address register were not shared. For operations outside of the address space of the subjeα memory, scanout and re-addressing operations for the subjeα memory are disabled. For changes in operations from the address space of the subjeα memory to the address space of the other circuits, scanout and re-addressing operations for the subjeα memory are disabled. For changes in operations from the address space of the other circuits to the address space of the subjeα memory, scanout and re-addressing operations for the subjeα memory commence from where they were disabled when the memory operation changed from the address space of the subjeα memory to the address space of the other circuits as if the operations of the subjeα memory had not been exited and as if the memory address register were not shared. For this latter example of changes in operations from the address space of the other circuits to the address space of the subjeα memory, (a) if the first continuing address in the address space of the subjeα memory is in the same block as the prior address stored in the buffer register representing the last block of operations before exiting the address space of the subject memory; then a scanout operation is invoked to maintain the same block of operations in the subjeα memory; and (b) if the first continuing address in the address space of the subjeα memory is in a different block compared to the prior address stored in the buffer register representing the last block of operations before exiting the address space of the subjeα memory; then a re-addressing operation is invoked to change blocks of the subjeα memory. If a shared memory address register configuration is implemented in accordance with the above, such as shown in Fig 4E; then operations in the subjeα memory will proceed as if the memory address register is not shared and without invoking extra re-addressing operations notwithstanding intervening operations outside the address space of the subjeα memory. The above discussed configuration will now be discussed for the case where the other circuits include a second memory having scanout and re-addressing operations. A processor is implemented to share an address register having operations in a first memory (the subjeα memory) needing re-addressing and having operations in a second memory (the other circuits) needing re-addressing. in this configuration; the first memory and the second memory each have
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dedicated comparitor deteαors that are the same as the comparitor deteαor shown in Fig 4E being replicated for each of the two memories except that the address detector logic 432J is different for each of the two replicated comparitor deteαors. The address 421 B from register 414 is fanned out to two comparitor deteαor circuits each deteαor circuit having a buffer register 414A generating prior address signals 421 C in response to next address signals 414A and in response to gated clock signal 432G generated by gate 432 F under control of address deteαor signal 432H and clock 432E; an address deteαor 432J generating address signal 432H in response to address signals 421 B; and comparitor 422 generating deteαor signal 423 in response to address signals 421C. The address deteαor logic 432J for each of the two memories is configured to deteα the address space of the memory to which it is dedicated. Hence, as operations change back and forth between the two memories, the Fig 4E deteαor dedicated to the memory whose address space is addressed by the memory address register is enabled by the address deteαor 432J therein to generate scanout and re-addressing operations and the Fig 4E deteαors dedicated to the memory whose memory space is not addressed by the memory address register is disabled by the address deteαor 432j therein and hence does not generate scanout and re-addressing operations. For example, as operations change from the first memory to the second memory; the Fig 4E deteαor dedicated to the first memory detects the exiting of the address space of the first memory with address logic 432J to cease memory operations for the first memory and the Fig 4E deteαor dedicated to the second memory detects the entering of the address space of the second memory with address logic 432J to commence memory operations for the second memory. Then, as operations change from the second memory back to the first memory; the Fig 4E deteαor dedicated to the second memory detects the exiting of the address space of the second memory with address logic 432j to cease memory operations for the second memory and the Fig 4E deteαor dedicated to the first memory detects the entering of the address space of the first memory with address logic 432J to commence memory operations for the first memory. The above discussed configuration will now be discussed for the case where the other circuits include a second memory and a third memory each having scanout and re-addressing operations. A processor is implemented to share an address register having operations in a first memory (the subjeα memory) needing re-addressing and having operations in a second memory and in a third memory (the other circuits) each needing re-addressing. In this configuration; the first memory, the second memory, and the third memory each have
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dedicated comparitor deteαors that are the same as the comparitor deteαor shown in Fig 4E being replicated for each of the three memories except that the address deteαor logic 432J is different for each of the three replicated comparitor deteαors. The address 421 B from register 414 is fanned out to three' comparitor deteαor circuits each deteαor circuit having a buffer register 414A generating prior address signals 42 I C in response to next address signals 414A and in response to gated clock signal 432G generated by gate 432 F under control of address deteαor signal 432 H and clock 432 E; an address deteαor 432J generating address signal 432H in response to address signals 42 I B; and comparitor 422 generating deteαor signal 423 in response to address signals 421C. The address deteαor logic 432J for each of the three memories is configured to deteα the address space of the memory to which it is dedicated. Hence, as operations change back and forth between the three memories, the Fig 4E deteαor dedicated to the memory whose address space is addressed by the memory address register is enabled by the address deteαor 432J therein to generate scanout and re-addressing operations and the Fig 4E deteαors dedicated to the two memories whose memory space is not addressed by the memory address register are disabled by the address deteαors 432J therein and hence do not generate scanout and re-addressing operations. For example, as operations change from the first memory to the second memory; the Fig 4E deteαor dedicated to the first memory detects the exiting of the address space of the first memory with address logic 432J to cease memory operations for the first memory, the Fig 4E deteαor dedicated to the second memory detects the entering of the address space of the second memory with address logic 432J to commence memory operations for the second memory, and theflg 4E deteαor dedicated to the third memory detects the address space of the second memory with address logic 432J to continue to disable memory operations for the third memory. Then, as operations change from the second memory back to the first memory; the Fig 4E deteαor dedicated to the second memory detects the exiting of the address space of the second memory with address logic 432J to cease memory operations for the second memory, the Fig 4E detector dedicated to the first memory detects the entering of the address space of the first memory with address logic 432J to commence memory operations for the first memory, and the Fig 4E deteαor dedicated to the third memory detects the address space of the second memory with address logic 432J to continue to disable memory operations for the third memory. Then, as operations change from the first memory to the third memory; the Fig 4E deteαor dedicated to the first memory detects the exiting of the address space of the first memory with address logic
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432J to cease memory operations for the first memory, the Fig 4E deteαor dedicated to the third memory detects the entering of the address space of the third memory with address logic 432J to commence memory operations for the third memory, and the Fig 4E deteαor dedicated to the second memory detects the address space of the third memory with address logic 432J to continue to disable memory operations for the second memory. Then, as operations change from the third memory to the second memory; the Fig 4E deteαor dedicated to the third memory detects the exiting of the address space of the third memory with address logic 432J to cease memory operations for the third memory, the Fig 4E deteαor dedicated to the second memory detects the entering of the address space of the second memory with address logic 432j to commence memory operations for the second memory, and the Fig 4E deteαor dedicated to the first memory detects the address space of the second memory with address logic 432J to continue to disable memory operations for the first memory. The above discussed shared address register configuration can readily have a single memory and one or more other circuits sharing the memory address register, a plurality of memories sharing the memory address register, a plurality of memories and one or more other circuits sharing the memory address register, or other such configuration. The shared address register configuration is discussed herein in the context of the Fig 4E deteαor configuration for simplicity of discussion. However, it will be readily recognized that multitudes of different types of memory deteαors, such as the memory deteαors disclosed herein, can be used to implement this shared address configuration. For example, the same type of deteαors can be used for a plurality of different memories and circuits sharing the same address register. Alternately, different types of deteαors can be used for each of a plurality of different memories and circuits sharing the same address register. Also, combinations of the same types of deteαors and different types of deteαors can be used for different memories and circuits sharing the same address register. The shared address register configuration is discussed herein without specifically addressing delay circuits for simplicity of discussion. However, will be readily recognized that multitudes of different types of different types of delay circuits, such as the delay circuits disclosed herein, can be used to implement this shared address configuration. For example, the same type of delay circuits can be used for a plurality of different memories and circuits sharing the same address register. Alternately, different types of delay circuits can be used for each of a plurality of different memories and circuits sharing the same address register. Also, combinations of the same types of delay circuits and different
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types of delay circuits can be used for different memories and circuits sharing the same address register. Further, it will be readily recognized that multitudes of different types of memory deteαors and multitudes of different types of delay circuits can be used to implement this shared address configuration. For example, the same type of deteαors and the same type of delay circuits can be used for a plurality of different memories and circuits sharing the same address register. Alternately, different types of deteαors and different types of delay circuits can be used for each of a plurality of different memories and circuits sharing the same address register. Also, combinations of the same type of deteαors and the same type of delay circuits and different types of deteαors and different types of delay circuits can be used in various combinations and permutations for different memories and circuits sharing the same address register. For example; a first type of deteαor and a first type of delay circuit can be used with a first memory, the first type of deteαor and the first type of delay circuit can be used with a second memory, a second type of deteαor and a first type of delay circuit can be used with a third memory, and the second type of deteαor and a second type of delay circuit can be used with a forth memory.
DELAYING CIRCUITS Introduαion Disabling and delaying circuits can be used in accordance with the present invention, such as in conjunαion with deteαor circuits (i.e.; rigs 4-B and 4Q. A clock gating arrangement for disabling or delaying memory operations is disclosed in detail with reference to Fig 6C that is appropriate to a specially designed or custom processor that has a clock gating capability. Other arrangements for disabling or delaying memory operations can also be provided that are appropriate to non-custom processors and are appropriate to standard processors. For example, various standard processors, such as microprocessors, have circuits that provide for disabling or delaying processor operations; which disabling or delaying processor circuits are also appropriate for use in disabling or delaying processor and memory operations in accordance with re-addressing operations, as disclosed herein. These disabling and delaying circuits include wait, hold, DTACK, and other microprocessor-related circuits infra. Various control circuits can be used to control such wait, hold, DTACK, and other circuits. In addition, custom processors can be designed to optimize uses of the features of the present invention. For example, a custom processor can be designed to operate at a higher speed scanout rate until a change is deteαed in address MSBs at which time the system can be disabled, slowed down, or otherwise adjusted for the re-addressing operation. Also, a custom microprocessor can be designed to generate instruαion execution signals that are specific to scanout, re-addressing, and refresh mode operations. Disabling and timing operations; such as the DTACK, READY, HOLD, etc. circuits of microprocessors; are well known in the art and are conventionally used for disabling and delaying for slow peripherals, slow memories, etc. However, these prior art uses are significantly different from the features of the present invention. For example, prior art devices invoke a fixed delay when they are seleαed. This can be illustrated with the IBM PC ® XT memory circuits which generate a fixed RAS and CAS cycle for every DRAM access and invoke a wait state delay, such as a one wait state delay or a two wait state delay, for each RAS and CAS cycle. The IBM PC ® XT does not have a memory address deteαor and certainly not a memory address deteαor to deteα the state of the address MSBs, nor to deteα a change in the address MSBs, nor to invoke a delay in response to deteαion of a change in the address MSBs, nor to inhibit a delay in response to deteαion of static (non-changed) address MSBs; as is disclosed in accordance with the system of the present invention. However, an upgrade of
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the IBM PC circuitry may be provided in accordance with the teachings of the present invention.
Clock Gating Delaying Circuits Clock gating circuits have been found to be particularly useful for disabling or delaying memory operations. Clock gating hazards; such as shaving clock pulses, causing "glitches", and other hazards; have been considered in the previously described clock gating circuits shown in Figs 6C and 6D. Synchronous devices operate in response to clock pulse signals, strobes, or other synchronizing signals. Gating of a clock signal in a hazard free manner, as previously described, can provide a disabling or delaying operation. Clock gating logic can be implemented internal to a processor IC chip, such as being embedded in the IC processor logic; external to a processor IC chip, such as gating of a clock signal before the clock signal is input to a processor IC chip; and in other forms.
Wait State Delaying Circuits Conventional microprocessors have circuits for disabling or delaying operations, sometimes implemented by introducing "wait states" supra. Such circuits can also be used for other types of processors. The 8086 family of microprocessors provided by Intel Corp.; i.e. the 8086, 8088, and 80286 microprocessors; implement wait states that can be controlled by a READY input signal to the microprocessor IC chips. The READY signal can be generated by digital logic, such as implemented by Clock Generator IC chips that are available from Intel Corp.; i.e. the 8284 family including the 8284 and 82284 Clock Generator IC chips; that operate under control of a RDY input signal. See the 8086 Family User's Manual (Oαober 1979) by Intel Corp.; such as at pages 4-10, A-23 to A-25, B-9, B-69, B-70. Also see the TECHNICAL REFERENCE (September 1985) by IBM Corp., such as at pages 1-76 and 1-82. The 8085 microprocessor provided by Intel Corp. also implements wait states that can be controlled by a READY input signal to the microprocessor IC chip. See the MCS-85 USER'S MANUAL (September 1978), such as at pages 5-2 and 5-6. The READY signal can be generated by digital logic, such as implemented with the Intel 8284 and 82284 Clock Generator IC chips for the 8086 family of microprocessors supra. The 68000 family of microprocessors provided by Motorola inc.; i.e. the 68000, 68020, and 68030 microprocessors; implement a form of wait states that can be controlled by a DSACK input signal to the microprocessor IC chips. See
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the MC68020 User's Manual (1984) by Motorola Inc., such as at page 4-3. The DSACK signal can be generated by well known digital logic.
Other Delaying Circuits Conventional computers have circuits other than "wait state" circuits for disabling or delaying operations. For example, processor operation can be disabled by a HOLD input signal to microprocessor IC chips that are available from Intel Corp.; i.e. the 8086 microprocessor family including the 8086 and 8088 microprocessors and the 8085 microprocessor. See the 8086 Family User's Manual (Oαober 1979) by Intel Corp., such as at page B-11. Also see the MCS-85 USER'S MANUAL (September 1978), such as at pages 5-2 and 5-6. Also, processor operation can be disabled by a DTACK input signal to microprocessor IC chips that are available from Motorola Inc.; i.e. the 68000 family of microprocessors. Also, processor operation can be disabled by a HALT input signal to microprocessor IC chips that are available from Motorola Inc.; i.e. the 68020 and 6800 microprocessors. See the MC68020 User's Manual (1984) by Motorola Inc., such as at page 4-5. Also see the 8-BIT MICROPROCESSOR & PERIPHERAL DATA manual (1983) by Motorola Inc., such as at page 3-157. In certain applications, it may be desirable to disable transferring of data rather than stopping the processor. For example, data can be stored in a register and, upon invoking of a delay or disabling operation, the data can be enabled to pass from the output of the register to the input of the register. Consequently, continued clocking of the register will result in the data stored in the register being preserved. This is an alternate to gating of the clock to preserving of the data in the register. In configurations, such as micro-programmable computers and state machines discussed herein; disabling and delaying operations can be implemented by disabling or delaying micro-operations or states. Such micro-operations or states can hold for a period of time, loop for a period of time, or otherwise disable or delay operations. An auxiliary timer can be used to determine when the time is up for the disabling or timing operation.
MULTIPLE DETECTOR AND DELAY CIRCUITS Multiple deteαor and delay circuits can be implemented in accordance with the present invention. For example, a shared memory address configuration supra can be implemented having a plurality of deteαor and delay circuits, such as in a shared memory address configuration having a plurality of memory circuits each with scanout and re-addressing capability. Also, a deteαor circuit
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can have multiple deteαors contained therewith, such as in a shared memory address configuration having an address space deteαor 432J to deteα if the address register is addressing the address space of the subjeα memory and having a comparitor deteαor 422 to deteα if the MSBs of the address register have been changed (Fig 4E). Also, one or more memories may each have a plurality of deteαor and delay circuits, such as for multiple scanout modes (i.e., an internal scanout mode and an external scanout mode) each having its own deteαor and delay circuit for providing different delays. Multiple deteαor configurations for sharing a memory address register with multiple memories are discussed in detail in the seαion entitled Shared Address Register herein. A deteαor circuit having multiple deteαors included therein is discussed in detail in the seαion entitled Shared Address Register herein. Multiple deteαor configurations for a particular memory are discussed in detail below. Multiple deteαors can be used for a single memory and for a plurality of memories to deteα appropriate conditions and to invoke a time delay in response thereto. The deteαed condition may be either the same or different for each deteαor circuit and the time delay may be either the same of different for each time delay circuit. A first multiple detector and delay example will now be discussed for the Second Fig 4H Configuration herein. This configuration has internal scanout and external scanout with the internal scanout bits implemented as the least significant bits and the external scanout bits implemented as the middle significant bits. For this first multiple deteαor and delay example, it will be assumed that the internal scanout propagation delays are shorter than the external scanout propagation delays and hence the internal scanout operations can be implemented to be faster than the external scanout operations. The memory can be implemented with two deteαors (i.e., Figs 4B and 4Q, a first deteαor generating a first deteαor signal that is indicative of a memory address change in the middle significant bits and a second deteαor generating a second deteαor signal that is indicative of a memory address change in the most significant bits. For the condition that neither the first deteαor deteOs a memory address change in the middle significant bits nor the second deteαor deteOs a memory address change in the most significant bits; internal scanout can be controlled to proceed at the highest memory rate within the block of least significant bits. For the condition that the first deteαor deteOs a memory address change in the middle significant bits and the second deteαor does not deteα a memory address change in the most significant bits; internal scanout can be disabled and external scanout can be controlled to proceed at the medium
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memory rate within the block of middle significant bits. For the condition that the second deteαor deteOs a memory address change in the most significant bits, independent of the condition deteαed by the first deteOor in the middle significant bits; internal scanout and external scanout can both be disabled and re-addressing can be controlled to proceed at the lowest memory rate within the block of most significant bits. A second multiple deteαor and delay example will now be discussed for the Third Fig 4H Configuration herein. This configuration has internal scanout and external scanout with the external scanout bits implemented as the least significant bits and the internal scanout bits implemented as the middle significant bits. For this second multiple deteOor and delay example, it will be assumed that the external scanout propagation delays are shorter than the internal scanout propagation delays and hence the external scanout operations can be implemented to be faster than the internal scanout operations. The memory can be implemented with two deteαors, a first deteOor generating a first deteOor signal that is indicative of a memory address change in the middle significant bits and a second deteOor generating a second deteOor signal that is indicative of a memory address change in the most significant bits. For the condition that neither the first deteOor deteOs a memory address change in the middle significant bits nor the second deteαor deteOs a memory address change in the most significant bits; external scanout can be controlled to proceed at the highest memory rate within the block of least significant bits. For the condition that the first deteαor deteOs a memory address change in the middle significant bits and the second deteOor does not deteα a memory address change in the most significant bits; external scanout can be disabled and internal scanout can be controlled to proceed at the medium memory rate within the block of middle significant bits. For the condition that the second deteαor deteOs a memory address change in the most significant bits, independent of the condition deteαed by the first deteαor in the middle significant bits; internal scanout and external scanout can both be disabled and re-addressing can be controlled to proceed at the lowest memory rate within the block of most significant bits. A third multiple deteOor and delay example will now be discussed for a general configuration having more than two deteαors and the related delay circuits. This configuration has more than three modes of operation having different data rates for each mode of operation. Each mode of operation is assigned to a different group of address bits. The memory can be implemented with more than two deteαors; a first deteOor generating a first deteOor signal that is indicative of a memory address change in a first group of address bits, a
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second deteOor generating a second deteOor signal that is indicative of a memory address change in a second group of address bits, a third deteOor generating a third deteOor signal that is indicative of a memory address change in a third group of address bits, and so forth. For the condition that none of the deteOors deteO a memory address change in the more significant bits, memory operations can be controlled to proceed at the highest memory rate within the block of least significant bits; for the condition that the first deteOor deteOs a memory address change and the higher order , deteOors do not deteO higher order memory address changes, memory operations can be controlled to proceed at a lower memory rate within the block of next more significant bits; for the condition that the second detector detects a memory address change and the higher order detectors do not deteα higher order memory address changes, memory operations can be controlled to proceed at a still lower memory rate within the block of next more significant bits; for the condition that the third deteOor deteOs a memory address change and the higher order deteOors do not deteO higher order memory address changes, memory operations can be controlled to proceed at a still lower memory rate within the block of next more significant bits; and so forth. Multiple deteOors can be implemented for the same memory (as an alternate to multiple deteαors for multiple memories discussed herein or in combinations with multiple deteOors for multiple memories discussed herein). These multiple deteOors can be the same type of deteOor (i.e., all overflow deteOors or all comparitor deteOors); can be the combinations of the same type of deteOor (i.e., two overflow detectors and three comparitor deteOors); can be combinations of the same type of deteOor and single type of deteOors (i.e., one overflow deteOors and three comparitor detectors); etc. The multiple deteOors can be configured to have different address deteαion magnitudes; such as to deteO a change in internal scanout address bits, a change in external address bits, and a change in re-addressing address bits to facilitate addressing mode control. Multiple deteOors for the same memory to deteα different memory speed conditions will now be described with reference to Figs 4Q and 4R. For simplicity of discussion, these multiple deteOors will be discussed as the same type of deteOor; i.e., all overflow deteOors (Fig 4Q) or all comparitor deteOors (Fig 4R). These multiple deteOors are shown configured to have different address deteαion magnitudes; different magnitude overflow bits (Fig 4Q) and different magnitude input address bits (Fig 4R). Alternately, different types of comparitors can be intermixed and address deteαion magnitudes can be seleOed to be combinations of the same address deteOion magnitude and
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different address deteOion magnitudes. Fig 4Q shows a plurality of address adder stages 453A (i.e., 74F283 chips in Figs 60 to 6R) having a plurality of overflow signals 453B (i.e., carry signals from the C4 pin from the 74F283 chips in Figs 60 to 6R) to a plurality of overflow circuits 453C (i.e., the overflow circuits shown in Fig 6C having C1 and C2 carry inputs). The overflow circuit (Fig 6Q can be expanded to accommodate additional carry inputs (i.e., Fig 6W) or can be replicated to provide multiple separate overflow deteOors for controlling different memory operations (i.e.; internal scanout, external scanout, and re-addressing). The break symbol in the signal line inbetween the adders illustrate that additional overflow deteOor channels can also be implemented in the combination. Fig 4R shows a plurality of comparitor stages 422A to 422B (i.e., comparitor 422 in Figs 4D and 4E) having a plurality of output signals 423A to 423 B respeαively (i.e., comparitor output signals 423 in Figs 4D and 4E) to control memory operations. Seleαed groupings of prior address bits 421 C and next address bits 421 B are shown compared with comparitors 422A to 422B. For example, a first grouping of prior address bits 454D and a first grouping of next address bits 454B are shown compared with comparitor 422A; a second grouping of prior address bits 454C and a second grouping of next address bits 454A are shown compared with comparitor 422 B to generate deteOor signals 423A and 423B respeOively. The break symbols in the signal lines inbetween comparitor 422A and comparitor 422B illustrate that additional comparitor deteOor channels can also be implemented in the combination. The signal line from deteOor signal 423 B to comparitor 422A is illustrative of a disable of comparitor 422A and deteOor signal423A when comparitor 422 B generates a deteOor signal 423A. Multiple time delay circuits for the same memory to control different memory speed conditions will now be discussed. In accordance with various configurations discussed herein, a deteOor circuit may have a delay circuit associated therewith, such as for controlling the rate of memory operations. Different deteαors can have delay circuits with different delay charaOeristics associated therewith associated therewith. For example; an internal scanout deteOor may have a short delay charaOeristic associated therewith to provide a short delay for internal scanout operations, an external scanout deteOor may have a longer delay charaOeristic associated therewith to provide a longer delay for external scanout operations, and a re-addressing deteOor may have a still longer delay charaOeristic associated therewith to provide a still longer delay for re-addressing operations. The delay circuits may be the same type of delay
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circuit for each detector, may be different types of delay circuits for each deteOor, or may be combinations of the same type of delay circuit and different types of delay circuits for the various deteOors. The delay circuit shown in Fig 6C (i.e.; flip-flops U21 B-5 and U21 B-2) can be adapted for different time delay magnitudes. For example, the use of two flip-flops (U21 B-5 and U21 B-2) provides a time delay suitable for the Fig 6C configuration. Alternately, removal of one of the two flip-flops (U21 B-5 or U21 B-2) and the gate (U20E-1 1 or U15A- 1 1) associated with the removed flip-flop (i.e., removal of flip-flop U21 B-2 and gate U15A-1 1) will reduce the magnitude of the time delay. Similarly, addition of another flip-flop and gate pair or multiple flip-flop and gate pairs will increase the time delay as a function of the number of flip-flop and gate pairs added. Other delay circuits, such as other time delay circuits disclosed herein, can be provided having suitable time delays to facilitate the multiple deteαor and time delay channel implementation disclosed herein. Multiple deteαor configurations have been discussed for deteOors in general for simplicity of discussion. However, it will be readily recognized that multitudes of different types of memory deteOors, such as the memory deteOors disclosed herein, can be used to implement this multiple deteαor configuration. For example, the same type of deteOors can be used for a plurality of different deteOors for the same memory. Alternately, different types of deteαors can be used for each of a plurality of different deteαors for the same memory. Also, combinations of the same types of deteOors and different types of deteOors can be used for each of a plurality of different deteαors for the same memory. Multiple delay circuit configurations have been discussed for delay circuits in general for simplicity of discussion. However, it will be readily recognized that multitudes of different types of memory delay circuits, such as the memory deteOors disclosed herein, can be used to implement this multiple delay circuit configuration. For example, the same type of delay circuit can be used for a plurality of different delay circuits for the same memory. Alternately, different types of delay circuits can be used for each of a plurality of different delay circuits for the same memory. Also, combinations of the same types of delay circuit and different types of delay circuits can be used for each of a plurality of different delay circuits for the same memory. Further, it will be readily recognized that multitudes of different types of memory deteOors and multitudes of different types of delay circuits can be used to implement this multiple deteOor and delay circuit configuration. For example, the same type of deteOors and the same type of delay circuits can be used for a plurality of different conditions for the same memory. Alternately,
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different types of deteOors and different types of delay circuits can be used for each of a plurality of different conditions for the same memory. Also, combinations of the same type of deteαors and the same type of delay circuits and different types of deteOors and different types of delay circuits can be used in various combinations and permutations for different conditions with the same memory and for different memories. For example; a first type of deteOor and a first type of delay circuit can be used for a first condition with a first memory, the first type of deteOor and the first type of delay circuit can be used for a second condition with the first memory, a second type of deteOor and a first type of delay circuit can be used for a third condition with the first memory, the second type of deteOor and a second type of delay circuit can be used for a forth condition with the first memory, the first type of deteOor and the first type of delay circuit can be used for a first condition with a second memory, the first type of deteOor and the first type of delay circuit can be used for a second condition with the second memory, a third type of deteOor and the second type of delay circuit can be used for a third condition with the second memory, a forth type of deteαor and a third type of delay circuit can be used for a first condition with a third memory, and the first type of deteαor and the third type of delay circuit can be used for a second condition with the third memory. A multiple deteOor configuration will now be discussed with reference to Figs 4B and 4S. A plurality of deteOors 220B can include a plurality of channels each containing a deteOor 455A generating a deteOor signal 455 B to invoke a delay with a delay circuit 455C to generate a delay signal 455D. For example, a first channel may include a first overflow deteOor 455A generating a first deteOor signal 455B to invoke a first delay with a first delay circuit 455C to generate a first delay signal 455D (Fig 6C), a second channel may include a second overflow deteαor 455A generating a second deteαor signal 455B to invoke a second longer delay with a second delay circuit 455C to generate a second longer delay signal 455D (Fig 6Q, a third channel may include a first comparitor deteOor 455A generating a third deteOor signal 455 B to invoke a third delay with a first one shot delay circuit 455C to generate a third delay signal 455D, a forth channel may include a first modal deteOor 455A generating a first modal deteαor signal 455B to invoke a forth delay with a forth delay circuit 455C to generate a forth delay signal 455D, and so forth. The delay signals 455D can be combined; such as with a logical OR gate 455E, a wired OR circuit, a tristate circuit, a logical NAND gate, or other circuit; to generate combined delay deteOor signal 221 B to invoke memory control signals and processor delay signals. Other arrangements for combining multiple deteOor
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signals can be readily provided from the teachings herein.
MEMORY REFRESH IntroduOion DRAMs need to be refreshed within a specified refresh period in order to insure that the stored information is preserved. A typical DRAM refresh period is 8-ms, but long 64-ms DRAM refresh periods are also available. A typical RAS only refresh cycle for the Toshiba TC514256P DRAMs takes about 0.19-us per row or a minimum of about 100-us for 512 rows during each DRAM refresh period (each 8-ms or each 64-ms). This represents a refresh duty cycle of about 0.0125 for the 8-ms DRAMs and a refresh duty cycle of about 0.0016 for the 64- ms DRAMs. Memory refresh, such as refreshing the Toshiba TC514256P DRAMs, can be implemented using on-the-chip refresh circuitry invoked by external signals, such as RAS and CAS signals. For example, Toshiba one-megabit DRAMs have 512-row addresses for the one-bit DRAMs, where refreshing can be commanded through the internal refresh counter by RAS-accessing each of the rows for each DRAM refresh period. Several forms of automatic refreshing include a RAS only refresh cycle where CAS* is maintained high and RAS* is cycled to invoke refresh operations, a CAS before RAS refresh cycle where CAS* goes low before RAS* goes low to invoke a refresh operation, and a hidden refresh cycle. See the MOS MEMORY PRODUCTS DATA BOOK by Toshiba at pages 127, 127, and 128 respeαively A DRAM refresh controller can be implemented with a DRAM refresh address counter for generating refresh addresses and a refresh control signal generator for generating refresh control signals (i.e., RAS* signals). For refreshing, the DRAM refresh address and the refresh signals (i.e., RAS* signals) are applied to the DRAMs; disabling normal memory operations and enabling refreshing. For normal memory operations, addresses generated by a processor address register and RASVCAS* processor control signals are applied to the DRAMs; disabling refreshing and enabling processing operations. Available DRAMs, such as the Toshiba TC514256P DRAMs, have a refresh address counter and a refresh control signal generator on the DRAM chip. Various examples are provided herein in the form of sync pulse related memory refreshing. For simplicity of discussion; an interlaced scan configuration will be discussed, such as having a 17-ms field sync period, a 34- ms frame sync period, and a 64-us line sync period. Other scan configurations can also be provided; such as a progressive scan configuration having a 1 7-ms
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frame sync period and a 32-us line sync period. Various memory refresh configurations are discussed below. Refreshing is discussed in the context of deteOing a time available period (i.e.; a horizontal sync pulse period or a vertical sync period in a display system, a suitable instruαion execution period in a computer, etc) and invoking memory refreshing during this time available period. Alternately, memory refreshing may be performed on a cycle stealing basis by disabling processor memory operations and invoking one or more memory refresh operations periodically, or upon occurrence of a system condition, or otherwise. Alternately, memory refreshing may be performed concurrently with processor memory operations by partitioning the memory into multiple parts and invoking memory refreshing operations in one part while performing processor memory operations in another part. Various implementations of memory re-addressing are discussed herein using overflow deteαors, comparitor deteαors, anticipatory deteOors, modal deteOors, time available deteOors, and other deteOors; which may also be used to implement memory refreshing. For example; a memory refresh operation can often be invoked concurrently with a memory re-addressing operation because the memory-related processing is often not being performed during a memory re- addressing operations. Alternately; a memory refresh operation can often be invoked in place of a memory re-addressing operation, such as during what is discussed in the context of a memory re-addressing operation condition, because the memory-related processing is often not being performed during such memory re-addressing related conditions, whether or not a re-addressing operation is invoked, and hence a memory refresh operation can be invoked in place of a memory re-addressing operation. Other memory refreshing configurations can also be implemented. The memory refresh configuration that uses a memory refresh deteOor to deteO a suitable memory refresh period and that invokes a memory refresh operation in response thereto may be considered to be an adaptive memory refresh configuration. This is because it adapts to the operations of the memory and processor to provide memory refresh operations rather than having a fixed memory refresh cycle; which can result in advantages such as increased performance and reduced contention. The memory architeαures disclosed herein may be used with a range of memory controllers. For example, the memory architeαures disclosed herein can be used with various scanout and re-addressing deteOor circuits, various delay circuits, and various refresh circuits, and others. Memory controller
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configuration-1 disclosed herein is one of many -controllers- that- can be implemented to operate in conjunαion with the memory architeαures disclosed herein. Various types of refreshing are known in the art. DRAM refreshing is well known in the art and is further discussed in detail herein. CCD refreshing, disclosed in detail in the related applications, involves shifting stored signals through a refresh circuit to reduce degradation of the stored information. Display refreshing involves iteratively or repetitively tracing the image over the display medium to reduce degradation of the displayed information. These different types of refreshing are herein charaOerized as DRAM refreshing, CCD refreshing, and display refreshing or terminology related thereto. For simplicity of discussion of various embodiments herein, refreshing may not expressly be shown in the figures nor discussed in the specification herein. However, it is intended that refreshing be implicit in these embodiments as needed.
Memory Refresh DeteOor Circuits IntroduOion Memory refresh detector circuits include circuits for deteαing conditions that are suitable for memory refreshing; such as time available conditions and cycle stealing conditions; for invoking memory refresh operations. Invoking of memory refresh operations can include invoking of a single memory refresh operation for each deteαion or invoking of a plurality of memory refresh operations for each deteαion. For example, the vertical sync deteOor circuits and the line sync deteOor circuits discussed herein provide for deteαing a sync signal condition that is suitable for invoking a plurality of memory refresh operations jnfra.
Time Available Refresh DeteOor Circuits Time available memory refresh deteOors can be implemented to generate a refresh time available signal in response to deteαion of time being available for one or more memory refresh operations. For example; the image memory line sync pulse deteOors, image memory field sync pulse deteOors, and suitable computer instruOion detectors; are time available memory refresh deteαors. The image memory line sync pulse memory refresh deteαors and the image memory field sync pulse memory refresh deteOors are discussed herein. Also discussed herein is a line sync memory refresh deteOor that deteOs a seleαed portion of a line sync pulse, the leading portion of a line sync pulse in this illustration.
The vertical sync memory refresh detector circuits and the line sync memorγ refresh deteOor circuits are discussed here for deteOing a condition that is suitable for invoking a plurality of memory refresh operations for each deteαion. For DRAMs needing 200-ns for each memory refresh operation, a 1-ms vertical sync pulse permits 5,000 DRAM refresh operations to be performed. (1-ms)/(0.20-us) - 5,000 The leading edge of a line sync pulse permits four or eight or other relatively small quantity of DRAM refresh operations to be performed, as discussed herein. For DRAMs needing 200-ns for each memory refresh operation, a full 6-us line sync pulse permits 30 DRAM refresh operations to be performed. (6-us)/(0.20-us) - 30 A stored program computer time available memory refresh deteOor can be implemented to perform memory refresh operations, such as on a time share basis with program operations. For example, an instruOion deteOor can be used to deteO instruαions or portions of instruαions that are suitable for memory refresh operations. In a micro-programmable computer, micro-instruαions can be implemented to generate memory refresh deteOor signals to invoke a memory refresh operation at times suitable for memory refreshing. In state machines (including types of computers), states can be implemented to generate memory refresh deteOor signals to invoke a memory refresh operation at times suitable for memory refreshing. Time available memory refresh deteOors that are responsive to execution of a computer instruOion can be implemented by deteOing a suitable portion of an instruαion execution period, such as deteαing seleαed micro-operations of an instruOion, that are indicative of computer operations which do not use main memory for an appropriate period of time in order to invoke refresh operations during that period of time. For example, an instruOion that processes a register operand, such as an instruOion that adds a register operand to the accumulator, may have to access an instruOion from main memory (as with an instruOion that adds a memory operand to the accumulator) but may not have to access an operand from main memory. Hence, an instruαion that processes a register operand may have time to invoke a memory refresh cycle in place of the memory operand access that is not needed for such an instruαion. Other instruαions may have an instruOion execution micro-operation that does not access main memory and hence leaves time available for memory refreshing. For example, an add instruOion may have an add instruOion execution micro- operation that does not access main memory and hence leaves time available for memory refreshing. Also, certain instruOions may have significantly longer
instruOion execution micro-operations, such as multiply and divide instruαions which may have eight instruOion execution micro-operations (such as fT^n eight bit computer), or 16 instruOion execution micro-operations (such as in a 16-bit computer), or 32 instruOion execution micro-operations (such as in a 32- bit computer) that do not access main memory and hence leaves time available for memory refreshing. See related patent application Serial No. 101,881 and see related Patent No. 4,371 ,923 for computer micro-operation disclosures; such as at Figs 5A and 5B therein and the discussion related thereto. For example, these disclosures discuss main memory-resident operand instruOions, discuss scratch pad register-resident operand instruαions, and discuss micro-operations related thereto. Time available memory refresh detectors that are associated with computer operations can be implemented by deteOing a suitable computer operation that is indicative of a condition that does not use main memory for an appropriate period of time in order to invoke refresh operations during that period of time. For example, in a computer that operates out of cache memory; a main memory refresh deteOor can invoke memory refresh operations when the computer is operating out of a cache memory that has sufficient information stored therein and hence does not require main memory accesses at that time. The Motorola 68020 microprocessor is an example of a computer having a cache memory. Other cache memory computers are well known in the art. For another example, in a computer that is delayed by external operations, such as by DTACK and READY circuits and wait state circuits; a memory refresh deteOor can invoke memory refresh operations when computer is delayed by an external operation. A direO memory access (DMA) memory refresh deteOor can be implemented to invoke memory refreshing on a time available basis in a DMA configuration that is suitable for time available memory refreshing. For example, if the DMA operations are associated with one of a plurality of memories; then one of the memories not having DMA operations at a particular time can be refreshed at that time. Also, if the DMA operations are relatively slower than memory speed; then a DMA refresh deteOor can be implemented to deteα the time available inbetween DMA operations to invoke refresh operations. For example, DMA loading of information from a hard disk may transfer one 16-bit word each microsecond, being limited by disk memory rates. However, the above- described Toshiba DRAM may be able to load that word in 50-ns using the fast page scanout addressing mode. Hence, 950-ns may be available for DRAM refreshing. For DRAMs needing 200-ns for each memory refresh operation,
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about four memory refresh operations can be invoked in the 950-ns time available. A cache memory refresh deteαor can be implemented to invoke memory refreshing on a time available basis in a cache memory configuration that is suitable for time available memory refreshing. For example, if the cache memory operations are associated with one of a plurality of memories; then one of the memories not having cache memory operations at a particular time can be refreshed at that time. Also, if the cache memory operations are relatively slower than memory speed; then a cache memory refresh deteOor can be implemented to deteα the time available inbetween cache memory operations to invoke refresh operations. For example, cache memory loading of information from a hard disk may transfer one 16-bit word each microsecond. However, the above-described Toshiba DRAM may be able to load that word in 50-ns using the fast page scanout addressing mode. Hence, 950-ns may be available for DRAM refreshing. For DRAMs needing 200-ns for each memory refresh operation, about four memory refresh operations can be invoked in the 950-ns time available. A filter processor, signal processor, or array processor memory refresh deteOor can be implemented to invoke memory refreshing on a time available basis in a filter processor, signal processor, or array processor configuration that is suitable for time available memory refreshing. For example, if the processing operations are associated with one of a plurality of memories; then one of the memories not having processing operations at a particular time can be refreshed at that time. Also, if the processing operations are relatively slower than memory speed; then a filter processing, signal processing, or array processing refresh deteOor can be implemented to deteα the time available inbetween processing operations to invoke refresh operations. For example; filter processing, signal processing, or array processing of input information may receive and process and store one input sample each microsecond. However, the above-described Toshiba DRAM may be able to store that input sample in 50-ns using the fast page scanout addressing mode. Hence, 950-ns may be available for DRAM refreshing. For DRAMs needing 200-ns for each memory refresh operation, about four memory refresh operations can be invoked in the 950-ns time available. An artificial intelligence memory processor memory refresh deteOor can be implemented to invoke memory refreshing on a time available basis in an artificial intelligence processor configuration that is suitable for time available memory refreshing. For example, if the processing operations are associated
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with one of a plurality of memories; then one of the memories not having processing operations at a particular time can be refreshed at that time. Also, if the processing operations are relatively slower than memory speed; then an artificial intelligence processing refresh deteOor can be implemented to deteO the time available inbetween processing operations to invoke refresh operations. For example; artificial intelligence processing of inference information may perform one inference operation each microsecond. However, the above- described Toshiba DRAM may be able to store that input sample in 50-ns using the fast page scanout addressing mode. Hence, 950-ns may be available for DRAM refreshing. For DRAMs needing 200-ns for each memory refresh operation, about four memory refresh operations can be invoked in the 950-ns time available. A display processor memory refresh deteαor can be implemented to invoke memory refreshing on a time available basis in a display processor configuration that is suitable for time available memory refreshing. For example, if the processing operations are associated with one of a plurality of memories; then one of the memories not having processing operations at a particular time can be refreshed at that time. Also, if the processing operations are relatively slower than memory speed; then a display processing refresh deteOor can be implemented to deteO the time available inbetween processing operations to invoke refresh operations. For example, display processing of image memory pixels may access and process and store one pixel each microsecond. However, the above-described Toshiba DRAM may be able to access that pixel in 50-ns and to store that pixel in 50-ns using the fast page scanout addressing mode. Hence, 950-ns may be available for DRAM refreshing. For DRAMs needing 200- ns for each memory refresh operation, about four memory refresh operations can be invoked in the 950-ns time available.
Cycle Stealing Refresh Deteαor Circuits Cycle stealing memory refresh deteOors can be implemented to generate a refresh command signal to invoke one or more refresh operations in response to determination of time being appropriate to steal a cycle or to steal multiple cycles from the processor for one or more memory refresh operations. For example; a counter, a one-shot monostable multivibrator, a DMA circuit, or other timing circuit may be used to generate periodic cycle stealing memory refresh command signals. For example, the IBM PC/XT uses a DMA circuit to generate time intervals, to interrupt the computer after each time interval has expired, and to invoke a refresh operation after each time interval has expired.
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Cycle stealing can be implemented by temporarily disabling processing operations and invoking a memory refresh cycle while the processor is disabled. Various types of disabling and delaying circuits are disclosed herein; such as DTAC and READY delaying circuits in a computer, wait state circuits in a computer, clock gating circuits, etc; which can be used to temporarily disable processing to provide time for a refresh cycle. A direα memory access (DMA) memory refresh deteOor can be implemented to invoke memory refreshing on a cycle stealing basis in a DMA configuration that needs cycle stealing memory refreshing. For example, if the DMA operations are about as fast as the DRAM being used; then there may not be sufficient time available for time available refreshing. Hence, a DMA refresh deteOor can be implemented to deteα cycle stealing times for stealing cycles from DMA operations to invoke refresh operations. A cache memory refresh deteαor can be implemented to invoke memory refreshing on a cycle stealing basis in a cache memory configuration that needs cycle stealing memory refreshing. For example, if the cache memory operations are about as fast as the DRAM being used; then there may not be sufficient time available for time available refreshing. Hence, a cache memory refresh deteOor can be implemented to deteα cycle stealing times for stealing cycles from cache memory operations to invoke refresh operations. A filter processor, signal processor, or array processor memory refresh deteαor can be implemented to invoke memory refreshing on a cycle stealing basis in a filter processor, signal processor, or array processor configuration that needs cycle stealing memory refreshing. For example, if the processor operations are about as fast as the DRAM being used; then there may not be sufficient time available for time available refreshing. Hence, a filter processor, signal processor, or array processor refresh deteαor can be implemented to deteO cycle stealing times for stealing cycles from filter processor, signal processor, or array processor operations to invoke refresh operations. An artificial intelligence processor memory refresh deteOor can be implemented to invoke memory refreshing on a cycle stealing basis in an artificial intelligence processor configuration that needs cycle stealing memory refreshing. For example, if the processor operations are about as fast as the DRAM being used; then there may not be sufficient time available for time available refreshing. Hence, an artificial intelligence processor refresh deteOor can be implemented to deteO cycle stealing times for stealing cycles from artificial intelligence processor operations to invoke refresh operations. A stored program computer cycle stealing memory refresh deteOor can be
T
implemented to perform memory refresh operations, such as on a cycle stealing basis with program operations. For example, a counter or other timer can be used to generate a periodic memory refresh deteOor signal to deteO the completion of a period of time between memory refresh operations and hence the need for another memory refresh operation. The computer program operations can be temporarily discontinued under control of the memory refresh deteOor signal to permit one or more memory refresh operations to be performed, followed by resumption of computer program operations. Computer disabling and delaying circuits are disclosed herein; such as DTAC, READY, and wait state circuits. A display processor memory refresh deteOor can be implemented to invoke memory refreshing on a cycle stealing basis in a display processor configuration that needs cycle stealing memory refreshing. For example, if the processor operations are about as fast as the DRAM being used; then there may not be sufficient time available for time available refreshing. Hence, a display processor refresh deteOor can be implemented to deteα cycle stealing times for stealing cycles from display processor operations to invoke refresh operations. A DMA memory refresh deteOor can be implemented to invoke memory refreshing on a cycle stealing basis in a DMA configuration that needs cycle stealing memory refreshing. For example, if the DMA operations are about as fast as the DRAM being used; then there may not be sufficient time available for time available refreshing. Hence, a DMA refresh deteOor can be implemented to deteα cycle stealing times for stealing cycles from DMA operations to invoke refresh operations.
Adaptive Refresh Deteαor Circuits An adaptive refresh controller in accordance with the teachings of the present invention can provide many of the advantages of time available refreshing in a configuration that may not otherwise be able to support time available refreshing. Time available memory refreshing enhances performance because it performs memory refreshing when the memory has time available as an alternate to the performance-reducing cycle stealing memory refreshing. Various time available memory refreshing arrangements are disclosed herein having time available that is a funαion of the mode of operation, the type of processing, etc. However, in some systems; time available refreshing may be permissible for only a portion of the time. in one example, a stored program computer may have time available when a first type of instruαion is executed and may not have time available when a
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second type of instruαion is executed. Consequently, such a system may have sufficient time available for memory refreshing when the processing has a nominal mixture of first instruOion type and second instruOion type executions, the system may have excessive time available for memory refreshing when the processing is first instruOion type intensive, and the system may not have enough time available for memory refreshing when the processing is second instruOion type intensive. In another example, a processor may have extensive time available for auxiliary memory operations, such as re-addressing and refreshing, during periods of low memory contention and may have little time available for auxiliary memory operations during periods of high memory contention; such as contention with external operations, or contention with instruOion execution accesses of memory, or other contention for memory operations. Consequently, such a system may have sufficient time available for memory refreshing for periods of medium contention, the system may have excessive time available for memory refreshing for periods of low contention, and the system may not have enough time available for memory refreshing for periods of high contention. In view of the above, it may be desirable to have an adaptive memory refresh controller that is responsive to the desired refresh conditions and to the aOual refresh conditions for adjusting the refresh conditions. For example, an adaptive memory refresh controller can be implemented to keep track of the aαual refreshing operations on a time available basis and the desired refreshing operations on a time period basis and can command cycle stealing refresh operations whenever the count of aOual refreshing operations becomes less than the count of desired refreshing operations. Hence, as long as the time available refreshing operations satisfies the memory refresh requirements, the adaptive controller need not intercede. However, if the time available refreshing operations do not satisfy the memory refresh requirements, then the adaptive controller intercedes and invokes cycle stealing refresh operations until the memory refresh requirements are met. One such adaptive memory refresh controller is described with reference to Fig 4P infra. An adaptive memory refresh controller can be implemented to keep track of the aOual refreshing operations on a time available basis and the desired refreshing operations on a time period basis and can command cycle stealing refresh operations, such as near the enα of the refresh period or interspersed with time available refresh operations during the refresh period, if the aOual refreshing operations are less than the desired refreshing operations. Hence, as long as the time available refreshing operations satisfies the memory refresh
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requirements or as long as there is suitable time in the refresh period for the quantity of aαual refresh operations to catch up with the quantity of desired refresh operations, the adaptive controller need not intercede. However, if the time available refreshing operations do not satisfy the memory refresh requirements and there is no longer suitable time in the refresh period for the quantity of aOual refresh operations to catch up with the quantity of desired refresh operations, then the adaptive controller intercedes and invokes cycle stealing refresh operations until the memory refresh requirements are met. This alternate configuration may provide a longer period of time for the time available refreshing operations to satisfy the memory refresh requirements, which may be an advantage in certain systems. This alternate configuration may result in invoking a group of stealing refresh operations over a short period of time near the end of the refresh cycle causing a peak contention condition, which may be a disadvantage in certain systems. Other adaptive memory refresh controllers can also be implemented. An adaptive memory refresh arrangement will now be discussed in greater detail with reference to Fig 4P. Period timer 451 A and desired refresh counter 451 D keep track of desired memory refresh operations. AOual refresh counter 451 E keeps track of aOual memory refresh operations. Comparitor 4511 compares the count of desired refresh operations generated by desired refresh counter 45 I D with the count of aOual refresh operations generated by aOual refresh counter 451 E to generate output signal 451J that is indicative of the relationship between the quantity of desired refresh operations and the quantity of aOual refresh operations. Output signal 451J can be used for invoking a cycle stealing refresh operation when the quantity of desired refresh operations exceeds the quantity of aαual refresh operations, or when the quantity of desired refresh operations becomes equal to or exceeds the quantity of aOual refresh operations, or otherwise. In the Fig 4P configuration, an insufficient quantity of aαual refresh operations can be used to force the count in aOual refresh counter 451 E to follow the count in desired refresh counter 451 D in response to the output signal 451J invoking refresh operations. However, an excessive quantity of aOual refresh operations can result in the count in aOual refresh counter 451 E getting far ahead of the count in desired refresh counter 451 D. This latter condition will not cause a problem as long as the high rate of time available refresh operations continues. However, a potential hazard can occur for the condition of a large number of time available refresh operations advancing the count in aOual refresh counter 451 E well beyond the count in desired refresh
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counter 451 D followed by the condition of the number of time available refresh operations being substantially diminished so that the quantity of desired refresh operations are not achieved during this following condition. If the time for the count in desired refresh counter 451 D to catch up with the count in aOual refresh counter 451 E plus the time to invoke an adequate number of cycle stealing refresh operations to complete refreshing of the memory exceeds the refresh period, stored information may be lost. A deteOor can be implemented to deteO this contingency, such as with a subtracter circuit subtraOing the count 451G from desired refresh counter 451 D and the count 451 H from aOual refresh counter 451 E to deteO when the count 451G from desired refresh counter 451 D is less than the count 451 H from aαual refresh counter 451 E by a deteαor threshold. When this condition is deteOed, various correOive operations can be implemented. For example, aαual refresh counter 451 E can be disabled for the duration of time that the deteOor threshold is exceeded to prevent the count 451 G from desired refresh counter 451 D from failing too far behind the count 451 H from aOual refresh counter 451 E. Alternately, desired refresh counter 451 D can be advanced to track aOual refresh counter within a suitable threshold distance. Other correOive operations can also be implemented. Period timer 451 A can be implemented to generate a time interval output signal 451 C to establish the desired time interval for a memory refresh operation to occur. For example, a DRAM having 512 rows and needing 512 refresh operations each 8-ms period may need a refresh operation each 15-us on the average. (8000-us)/(512) * 15.6-us/refresh operation Hence, period timer 451 A can be implemented to generate a period signal 45 IC each 15-us period. Period timer 451 A can be implemented with various circuits; such as a 74LS161 counter for generating a counter overflow signal 451 C, a rate multiplier for generating a rate multiplier output signal 451 C, an astable multivibrator for generating as astable multivibrator cycle signal 451C, or a well known DMA arrangement. Desired refresh counter 451 D can be implemented to count period signals 45 IC to generate a count of desired refresh signals 451G as being indicative of the number of refresh operations that should have been performed. It can be implemented with a 74LS161 counter. AOual refresh counter 451 E can be implemented to count the aOual refresh signals 45 IF to generate a count of aαual refresh signals 451 H as being indicative of the number of refresh operations that have aOually been
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performed. It can be implemented with a 74LS 161 counter. The desired refresh signals 451G generated by desired refresh counter 451 D can be compared with the aOual refresh signals 451 F generated by aOual refresh counter 451 E by comparitor 4511 to generate output signals 451 j that are indicative of the relationship therebetween. Comparitor 4511 can be implemented with a 74LS85 comparitor. For example, if the desired refresh signals 451G are input to the A-inputs of comparitor 4511 and the aOual refresh signals 451 F are input to the B-inputs of comparitor 4511, then output signal 0^ β 451J is indicative of the quantity of aOual refresh operations falling behind the quantity of desired refresh operations and hence can be used to invoke a cycle stealing memory refresh operation. Alternately, output signal 0^<3 451J is indicative of the quantity of aOual refresh operations getting ahead of the quantity of desired refresh operations and hence can be used to disable cycle stealing memory refresh operations. The arrangement shown in Fig 4P can be implemented with long counters 451 D and 451 E to reduce the occurrence of counter overflow. However, when a counter overflows; the comparitor output signals 451J can change meaning. For example, when the aOual refresh counter 45 I E overflows as a result of counting of aOual refresh operations, the aOual refresh count will traverse from being larger than the desired refresh count to being smaller than the desired refresh count, which may be undesirable. However, various circuit configurations can be implemented to compensate for this condition. For example, counter conditions can be deteαed and can be used to reset, to preset, or to preload one or both of the counters, the aOual refresh counter 451 E and/or the desired refresh counter 451 D. Counter conditions can be deteOed by logical gates, decoders, overflow deteOors, etc. Well known counters have reset circuits for resetting the counter (i.e., the 74LS161 counter and the 74LS90 counter), have preset circuits for presetting the counter (i.e., the 74LS90 counter), and have preloading circuits for preloading a predetermined number into the counter (i.e., the 74LS161 counter). In one configuration, both counters, the aOual refresh counter 451 E and the desired refresh counter 451 D, can be reset when the desired refresh counter 451 D passes through a threshold. In another configuration, both counters, the aOual refresh counter 451 E and the desired refresh counter 451 D, can be reset when the aOual refresh counter 451 E passes through a threshold. In another configuration, the aOual refresh counter 451E can be preloaded to the condition of the desired refresh counter 451 D when the desired refresh counter 451 D passes through a threshold. In another configuration, both counters, the aOual refresh counter 451 E and the desired
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refresh counter 45 I D, can be preset or preloaded to predetermined conditions when the desired refresh counter 45 I D passes through a threshold. In another configuration, both counters, the actual refresh counter 451£ and the desirett refresh counter 45 I D, can be preloaded to predetermined conditions when the aαual refresh counter 451 E passes through a threshold. Also, these configurations can be used in combinations. For example; both counters, the aOual refresh counter 451 E and the desired refresh counter 451 D, can be reset when the desired refresh counter 451 D passes through a threshold and the aOual refresh counter 451 E can be preloaded to the condition of the desired refresh counter 451 D when the desired refresh counter 451 D passes through a threshold or overflows. Many other configurations can be implemented to overcome the overflow condition. The adaptive memory refresh controller disclosed with reference to Fig 4P can be implemented in various other ways and with various other components. Also, the components can be expanded to achieve greater dynamic range. For example, the 74LS161 counters can be expanded by conneOing the terminal count TC* overflow bit of a prior stage to the count enable trickle CET carry input bit of a subsequent stage. Also, the 74LS85 comparitor can be expanded by conneOing the three output condition circuit pins of a prior stage to the three input condition circuit pins of a subsequent stage.
Other Refresh DeteOor Circuits Other memory refresh deteOors, other than time available memory refresh deteOors and cycle stealing memory refresh deteOors, can be implemented to generate refresh command signals to invoke one or more refresh operations. A memory refresh deteOor may be a combination of a time available memory refresh deteOor and a cycle stealing memory refresh deteOor. In one such a combination deteOor, a time available deteOor may initiate memory refresh operations and, when the time available deteOor terminates the time available period, a cycle stealing deteαor can steal one cycle or more than one cycle to permit any memory refresh operation that is in process when the time available deteOor terminates the time available period. In another such a combination deteOor, a time available deteOor may initiate memory refresh operations when time is available and a cycle stealing deteOor may initiate refresh operations when time is not available. A counter may be employed to keep track of the rate of refresh operations or the number of refresh operations and to invoke cycle stealing refresh operations when the time available refresh operations do not meet the minimum refresh requirements.
Sync Pulse Controlled Memory Refreshing IntroduOion Sync pulse memory refreshing is particularly advantageous in display systems; such as in a graphics display system, in an image processing display system, and in a television display system; where the display system may not need to perform memory intensive display processing operations during the sync pulse period. Such sync pulse memory refreshing can provide advantages, such as improved performance and reduced cycle stealing and contention. A display system may have to perform image memory intensive display operations, such as display refreshing, during the period inbetween sync pulses and the display system may not have to perform image memory-related display operations during the sync pulse period. Hence, the display system can perform image memory refreshing operations during the sync pulse period. Also, in this example; the display system may perform display processing operations during the sync pulse period, such as concurrently with the DRAM refresh operations or on a time shared basis with memory refresh operations.
Vertical Sync Pulse Memory Refreshing Vertical sync pulse memory refreshing will now be discussed for DRAM refreshing. Vertical sync pulse DRAM refreshing can be implemented for longer refresh period DRAMs that are tolerant to the vertical or field sync (FS) pulse period. Shorter refresh period DRAMs, such as 8-ms refresh period DRAMs, may not operate properly if refreshed on each vertical sync pulse, each 17-ms period. However, longer refresh period DRAMs, such as 64-ms refresh period DRAMs, should operate properly if refreshed on each vertical sync pulse. For example, the 64-ms period DRAMs can be refreshed during each vertical field pulse period, about each 17-ms period, or during each vertical frame pulse period, about each 34-ms period. The vertical sync pulse width is typically more than one-ms, which is 10-times more than required to perform the 100-us RAS- accessed refresh i ng of the D RAM 512-rows. The vertical sync pulse period has more than enough time to perform refreshing for conventional DRAMs, assuming that the 17-ms period inbetween vertical sync pulses is not too long to meet the DRAM refreshing requirements. For example, the above calculations show that about 100-us per refresh period is needed for refreshing of the Toshiba TC514256P DRAMs. However, the vertical sync pulse has about 10-times the 100-us refresh time needed for DRAM refreshing per field sync period (based upon an 8-ms refresh period, a 1 -ms
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field sync period, and a 1-ms field sync pulse width). (1 OOO-us 17-ms) (8-ms refresh) - 470-us
Horizontal 5ync Pulse Memory Refreshing Horizontal sync pulse, also called line sync (LS) pulse, memory refreshing can be implemented for more frequent refreshing than available with vertical sync pulse memory refreshing, such as for shorter refresh period DRAMs. For example, the 8-ms period DRAMs may not operate properly if refreshed on each vertical sync pulse, each 17-ms period, but should operate properly if refreshed during multiple line sync pulse periods, such as each 63-us period. The line sync pulse periods have more than enough time to perform refreshing for conventional DRAMs. For example, the above calculations show that about 100-us per refresh period is needed for refreshing of the Toshiba TC514256P DRAMs. However, the line sync pulses have over seven times the 100-us refresh time needed for DRAM refreshing per field sync (FS) period (based upon an 8-ms refresh period, a 63-us line sync period, and a 6-us line sync pulse width). (8000-us/63-us) (6-us/line) - 761 -us In the display system disclosed relative to Figs 6A et seq herein; the display system performs image memory intensive display refreshing during the period inbetween line sync pulses and the display system need not perform any image memory-related display operations during the line sync pulse period. This display system can readily be adapted to performing image memory refreshing operations during the line sync pulse period infra, such as concurrently with the display processing operations or on a time shared basis with the display processing operations. In this display system, an enhancement has been made to perform the display processing operations during a portion of the line sync pulse period infra, which can be called a shortened line sync pulse period for display processing purposes. A portion of the line sync pulse period can be used for performing display processing to load up a display buffer memory, which is located inbetween the display processor and the video DACs, with display information. This display configuration can be adapted to performing image memory refresh operations during the shortened line sync pulse period. For example, during the portion of the line sync period having display processing operations, refresh operations can be disabled, and during the portion of the line sync period not having display processing operations, refresh operations can be enabled. Alternately, in a display system not having the above discussed enhancement,
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the DRAM image memory refresh operations can be performed during the whole line sync pulse period. Many other alternate configurations can also be provided. In one configuration, DRAM refresh can be performed for the whole line sync pulse period. For example, for a display system having a line sync pulse width of about 6-us; about 17 line sync pulses are needed to perform the 100-us RAS-accessed refreshing of the DRAM 512-rows based upon a 0.19-us per row refresh period. [(0.19-us)/(DRAM row)][(512 DRAM rows)/(6-us)]/[sync pulse] - 16.2 line sync pulses In another configuration, DRAM refresh can be performed for a portion of each line sync pulse period for multiple line sync pulses. DRAM refresh that is performed for a portion of each line sync pulse period is particularly efficient, such as in a configuration that loads display information into a display buffer. For example, a configuration using a display buffer (i.e., a line buffer) inbetween the image memory and the video DACs can use a portion of the line sync pulse period for DRAM refreshing and can use the balance of the line sync pulse period for loading the display buffer. In such a display buffer configuration, loading the display buffer during the line sync pulse period or during a portion of the line sync pulse period increases the number of pixels per line, such as by almost 10% for the present illustrative example. (6-us/sync pulse)/(63 us/sync pulse period) - 0.095 About four DRAM rows need to be refreshed per line sync pulse in order to achieve refreshing of all 512 rows in each 8-ms refresh period with an 0.19-us row period, a 63-us per horizontal line, a 6-us per line sync pulse and 512-rows per DRAM; (horizontal lines)/(refresh period) - (8000us)/(63us) - 126.98 (DRAM rows)/(horizontal line) - (512 DRAM rows)/(126.98 lines) - 4.03 DRAM rows/line Assuming a safety faαor of about two times (8 DRAM rows/line), about 1.5-us is needed out of each 6-us line sync pulse for DRAM refreshing. (0.19us/row)(8 DRAM rows) - 1.52us This is about 2.4% of the 63-us horizontal line period, which results in a reduαion of about 2.4% of the number of pixels per line to accommodate line sync pulse refreshing in such a display buffer configuration. Some of the line sync pulse period may also be used for display processing, such as to initialize
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the next display horizontal scan line. The time for such refresh operations may be performed concurrently with such display processing. A configuration having DRAM refreshing performed for a portion of each line sync pulse period is implemented in the display system shown in Figs 6A et seq herein. Line sync pulse display processing can be performed concurrently with DRAM refreshing because, in this configuration, such display processing does not access DRAM image memory. For alternative implementations of refreshing DRAM image memory during the entire line sync pulse period, the line sync pulse signal can be used as the envelope to enable the refreshing logic. For the alternative implementations of refreshing DRAM image memory during a portion of the sync pulse period, the signal that defines the portion of the sync pulse to be used for the line sync pulse display processing can also be used as the envelope to enable the refreshing logic infra. A first DRAM refreshing configuration will now be discussed with reference to Figs 6A et seq. The front portion of the sync pulse can be used to perform DRAM refreshing operations, as enabled with the RUN* signal, which is generated by complementing the RUN signal U13A-8 (Figs 6W, 6D, 7C, and 7D). The RUN signal has the logical equation (CLSRl * AND CFSR1 *) + (CFSRl * AND CLSR1 AND CLSR4) The RUN signal covers the period of time when the CFSRl signal (vertical sync pulse) is low and either the line sync pulse is low CLSR1 * or the trailing portion of the line sync pulse (CLSR1 AND CLSR4) is true. This covers the whole period when the vertical sync pulse is low except for the leading portion (CLSR1 AND CLSR4*) of the line sync pulse. Similarly, other signals (including the complements of other signals); such as the DOA5, DOA6, and CFSR1 signals infra: can be logically combined (i.e., ANDing, ORing, etc) with the RUN signal by one skilled in the art. The RUN signal is shown being generated by the NANDing of the U13A-13 signal and the U13A-9 signal; the U13A-10,12 signal having no effeα on the RUN signal. The U13A-13 signal defines the condition (CLSR1 * AND CFSR1 *), which is the period inbetween line sync pulses (CLSR1) during the period that the field sync pulse (CFSRl) is low. The U13A-9 signal defines the condition (CFSRl * AND CLSRl AND CLSR4), which is the period in the trailing portion of the line sync pulse. All of the rest of the time, the vertical (field) sync pulse width period and the leading portion of the line sync pulse, is available for DRAM refreshing. A second DRAM refreshing configuration will now be discussed with reference to Figs 6A et seq. Similar to said first DRAM refreshing configuration; the front portion of the sync pulse can be used to perform DRAM refreshing
operations, as enabled with the ELS signal U15A-3 (Figs 6D, 7C, and 7D). The ELS signal has the logical equation (CLSRl AND CLSR4* AND DOA6) + DOA5 The ELS signal covers the period of time when the leading portion of the line sync pulse (CLSR1 AND CLSR4*) is true. The ELS signal is shown being generated by the ANDing of the CLSR1 AND CLSR4* signals with gate U19D-4 to generate the leading portion of the line sync pulse (CLSRl AND CLSR4*). The ANDing and ORing of the DOA6 and DOA5 respeαively is performed with gates U22C-3 and U15A-3. The DOA6 and DOA5 signals are modal signals, such as for controlling the write mode, and are not essential to the present discussion of line sync pulse leading edge refreshing. Similarly, the logical combining (i.e., ANDing, ORing, etc) of other signals (including the complements of other signals); such as the DOA5, DOA6, and CFSR1 signals; with the leading portion signal (CLSRl AND CLSR4*) can readily be performed by one skilled in the art. In the above first and second DRAM refreshing configurations; the leading portion of the line sync pulse, CLSR1 to CLSR4, involves three clock pulse periods of 100-ns each. This period can be increased, such as to the 1.4-us period needed for the eight DRAM refresh operations in the above example, by introducing additional delays. For example, placing 1 1 additional flip-flops inbetween CLSRl and CLSR4 will increase the 3-clock period delay (300-ns) to a 14-clock period delay (1.4-us). Other arrangements can be used, such as a counter or a one-shot monostable multivibrator, to control the duration of the period of the leading edge of the line sync pulse for DRAM refresh operations. Alternately, the whole line sync pulse or the whole field (vertical) sync pulse can be used to invoke DRAM refreshing and display processor updating, such as with the line sync pulse signal CLSR1 or with the field sync pulse signal CFSR1. For example, the whole line sync pulse period can be used for refreshing in said first configuration by removing the U13A-9 signal from the RUN equation by disconneoing the U17A-8 signal therefrom and conneOing the U13A-9 pin to a high (V β iAs or V^) signal and in said second configuration by removing the CFSR4* delayed line sync pulse signal from the ELS equation by disconneoing the CLSR4 signal from UI 9D-5 and conneOing U19D-5 to a ground.
On-The-Chip Memory Refresh An on-the-chip memory refresh configuration will now be described in the context of a DRAM system. Refresh can implemented with an internal or an external refresh counter to
count the rows and to generate row addresses. RAS-only refresh uses an external refresh counter. CAS-before-RAS refresh and hidden refresh use an internal refresh counter which is internal to the DRAM IC chip. All three of these refresh modes permit multiple refresh cycles. For CAS-before-RAS refresh and hidden refresh, the internal refresh counter initiates refreshing when RAS* goes low bracketed by CAS* being low and terminates refreshing when CAS* goes low bracketed by RAS* being low. Refreshing continues for each RAS* cycle until CAS* goes high and then goes low bracketed by RAS* being low. Hence, if RAS* goes low with CAS* being low, then internal refreshing is executed for each cycle of RAS* going low (independent of whether CAS* remains low). If CAS* remains low during refreshing, hidden refresh is performed and data is output. If CAS* remains high during refreshing, CAS-before-RAS refresh is performed and the output lines are at high impedance. The primary difference between CAS-before-RAS refresh and hidden refresh is as follows. For hidden refresh, CAS* is left low while cycling RAS* so that the output is not at high impedance. For CAS-before-RAS refresh, CAS* is placed high while cycling RAS* so that the output is at high impedance. In applications where CAS-before-RAS refresh can be used; the design may be a little simpler and may be a little easier to check-out. In a line sync pulse controlled arrangement, a logical "one" line sync pulse can be implemented to invoke the RAS* DRAM refresh control signals and to generate RAS* pulses to the DRAM for refresh operations and a logical "zero" line sync pulse can be implemented to invoke the scanout and re-addressing display operations. In a vertical sync pulse controlled arrangement, a logical "one" vertical sync pulse could be implemented to invoke the RAS* DRAM refresh control signals and to generate RAS* DRAM refresh control signals and to generate RAS* pulses to the DRAM for refresh operations and a logical "zero" vertical sync pulse could be implemented to invoke the scanout and re- addressing display operations.
Stored Program Computer DRAM Refresh Various memory refresh configurations are discussed herein, which are applicable to refreshing of DRAMs in a stored program computer. Further, DRAM refresh deteαors for a stored program computer are discussed with reference to Fig 4M herein that is particularly suitable to an on-the-chip memory deteOor arrangement. Several additional configurations for refreshing DRAMs used in a computer main memory will now be discussed, supplementing the
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discussion of other configurations herein. One configuration for refreshing DRAMs used in a computer main memory implements a refresh controller circuit to disable the computer; such as with a halt signal, a wait signal, or a cycle stealing control signal; when a refresh operation is necessary. However, this configuration reduces throughput of the computer. A more efficient configuration implements a refresh deteOor to deteα when the computer is performing a refresh-tolerant operation, such as execution of a time consuming instruOion, that does not need to access main memory for at least a refresh period of time. Then, the refresh deteαor can command a refresh operation on this time available basis instead of on a cycle stealing basis. DeteOion of such a refresh tolerant condition can be enhanced if the computer, such as with its micro-instruOions, generates a refresh enable signal to identify a refresh tolerant condition.
MEMORY ARCHITECTURE IntroduOion Various memory architeαures are disclosed as being implemented with Mitsubishi RAMs and alternately are disclosed as being implemented with Toshiba DRAMs. One skilled in the memory art will readily be able to implement DRAM memories from the Mitsubishi RAM memory teachings and one skilled in the memory art will readily be able to implement Mitsubishi RAM memories from the DRAM memory teachings. Various memory architeOurai embodiments are disclosed herein; such as having addressing arrangements with external scanout, internal scanout, and re- addressing; having RAS and CAS arrangements with fanned-out (not steered) RAS and CAS and with fanned-out (not steered) RAS and steered CAS; having seleαion with and without an output enable; having signal output bit (by-1) DRAMs and four output bit (by-4) DRAMs; and others. These memory architeαures are illustrative of other combinations, permutations, and alternatives of the various features. For example, one skilled in the memory art can readily implement other memories having other addressing arrangements of external scanout, internal scanout, and/or re-addressing; having other RAS and CAS arrangements, such as with steered RAS and steered CAS and with other combinations of fanned-out and steered RAS and CAS; having other configurations of seleαion with and without output enable seleαion; and having bit arrangements other than signal output bit (by-1) DRAMs and four output bit (by-4) DRAMs and other combinations of bit arrangements with other memory
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features. Various memory architeαures are disclosed herein and those skilled in the art will be able to implement many other memory architeαures from the teachings herein. These memory architeαures can be implemented with deteOors, delaying circuits, refresh circuits, address generators, control signal generators, and other circuits. For example, Figs 4B and 4C teach the combination of a processor, an address generator, deteOor circuits, delay circuits, and memories; where memories 222 therein may be implemented with the memory architeαures disclosed herein and implied thereby. Many of the memory signals, such as memory address and memory control signals, are fanned out to a plurality of DRAM chips. Fanout drivers may be needed to meet fanout requirements of a particular configuration. Such drivers are well known in the art. Also, such drivers are disclosed herein (i.e., Fig 6F). For example; Signetics 8T95 to 8T98 circuits can be used in place of or in addition to the 74LS365 to 74LS368 circuits. Also, address bus logic shown in Figs 6E and 6F and data bus logic shown in Figs 6K to 6N are pertinent to the DRAM address bus logic and data bus logic.
Memory Dimensions IntroduOion There are several forms of memory dimensioning disclosed herein. For example, there is the dimensions of the scanout and re-addressing operations, the dimensions of the memory spatial array for external scanout, and the dimensions of the memory address struOure. The scanout and re-addressing operations, discussed in detail herein, may be considered to be a two dimensional configuration (i.e., Figs 6E to 6N). The external scanout arrangement can be partitioned into a multi- dimensional spatial memory array (i.e., Figs 6E to 6N). Multiple spatial scanout dimensions can be used to increase the size of the scanout blocks of memory to maximize scanout operations and to minimize re-addressing operations. For example, a two dimensional (XY) array of DRAM IC chips can be implemented; similar to the Mitsubishi RAM and DRAM alternate configurations (i.e., Figs 6E to 6N); to increase the scanout block size and hence to minimize re-addressing operations, to maximize scanout operations, and to reduce the amount of external scanout logic needed to address the array of DRAMs. The dimensions of the memory address struOure are further illustrated in Figs 4F and 4G. Memory dimensions associated with memory address struOure may be considered to be resident in the memory address struOure. For example, a
two dimensional memory address struOure (i.e., Fig 4F) can be converted to a single dimensional address struOure (i.e., Fig 4G) by changing the address generators from two dimensional address generators to single dimensional address generators. Similarly, a single dimensional memory address structure (i.e., Fig 4G) can be converted to a two dimensional address struOure (i.e., Fig 4F) by changing the address generators from single dimensional address generators to two dimensional address generators. Also, the address generators shown in Fig 4F are partitioned into two independent address generators operating relatively independent of each other to implement a two dimensional memory. Alternately, the address generator shown in Fig 4G is partitioned into a single address generator to implement a single dimensional memory. The address multiplexers and DRAM array are shown having twenty address lines relatively independent of whether the address lines are generated by two relatively independent address generators (Fig 4F) or by a single address generator (Fig 4G). Similarly, the address struOure can be partitioned into a multi-dimensional address struOure having 3-dimensions, 4-dimensions, and 8- dimensions, or more by partitioning the address generators to establish the desired memory dimensions by the number of address generators operating relatively independent of each other. The memory architeαure, illustrated in Figs 4F and 4G, consisting of the address multiplexers and the DRAM array need not be specific to the dimension of the address generators. However, it is desirable to adapt the memory architeαure to the address struOure; such as the number of MSBs, the number of LSBs, the external scanout configuration, and other considerations. A two dimensional memory map display configuration may implicitly be a two dimensional array of pixels and hence may have particular advantages when implemented as an two dimensional address configuration. Such a configuration can be implemented by having two separate and relatively independent address registers, such as an X address register and a Y address register. Alternately, a stored program in a computer may implicitly be a single dimensional array of instruαions and hence may have particular advantages when implemented as an single dimensional address configuration. Such a configuration can be implemented with a single address register instead of multiple relatively independent address registers. Alternately, other configurations may be provided. For example, a display system may be implemented as a single dimensional address configuration and a stored program computer may be implemented as a multi-dimensional address configuration.
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Multi-Dimensional Memory (Fig 4F) A multi-dimensional memory architeαure is disclosed in the embodiment of an image memory (Figs 6E to 6N). An alternate embodiment thereof will now be discussed with reference to the block diagram shown in Fig 4F, which is consistent with the detailed memory schematic diagrams (i.e.. Figs 6E to 6N). Various DRAMs, such as the Toshiba TC514256P DRAMs, implement a fast page mode read cycle and a fast page mode write cycle, which can be used to implement the multi-dimensional memory architeαure. See the Toshiba Corporation MOS MEMORY PRODUCTS DATA BOOK '86-7 at pages 119 et seq and particularly at page 125 therein. The fast page mode read cycle and the fast page mode write cycle can both use the multi-dimensional architeαure of the present invention, where the fast page mode read cycle will be discussed herein as representative of both, read and write cycles. Also, multi-dimensional memory architeαure is disclosed in Figs 6E to 6N showing a configuration of combining both, read and write circuits. A multi-dimensional DRAM image memory architeαure, such as for a display system, is shown in Fig 4F as illustrative of other memory configurations in accordance with the present invention. The five LSBs of each, the X-address and the Y-address, provide the ten column address bits for the DRAMs. The five MSBs of each, the X-address and the Y-address, provide the ten row address bits for the DRAMs. Hence, a high speed fast page memory read cycle DRAM X/Y scanout can be implemented for a 5-bit by 5-bit (32-pixel by 32-pixel) image region; just as the high speed X/Y scanout generates a 3-bit by 3-bit (8-pixel by 8- pixel) image region (Figs 6E to 6N). In the present DRAM configuration; a deteOor, such as an overflow deteOor, can be implemented to monitor the fifth- bit address generator carry control signal to control the RAS* and CAS* fast page memory read cycle signals; just as the overflow deteOor monitors the third-bit address generator carry control signal to control the X/Y scanout and re-address (Figs 6E to 6N). Alternately, other types of deteOors can be implemented. Row and column multiplexers can be used (Fig 4F) to multiplex row and column addresses into each DRAM under control of the deteOor signal, such as the fifth-bit address generator carry control signal in the Fig 4F configuration; just as the third-bit address generator carry control signal generates an overflow signal to control the X Y scanout and re-address modes (Figs 6E to 6N). Decoders and drivers can also be used (i.e., Figs 6F and 4H to 4J), although these circuits are not shown in Fig 4F for simplicity. Operation of this configuration in the context of a display system will now be discussed. The X-address generator 430A and the Y-address generator 430B
generate addresses having X Y scanout (LSB) signals and X Y re-address (MSB) signals associated with geometric processing; just as the X-address generator and the Y-address generator generate addresses having X/Y scanout (LSB) signals and re-address (MSB) signals associated with geometric processing (Figs 6E to 6N). Operating in the fast page mode read cycle with the multiplexer seleαing the column address (LSBs), the DRAMs 430F are accessed by the changing column addresses (LSBs) for a fixed row address (MSBs) as long as the addresses are within a 5-bit by 5-bit (32-pixel by 32-pixel) block; just as the RAMs are accessed by the changing LSB addresses for fixed MSB addresses as long as the addresses are within a 3-bit by 3-bit (8-pixel by 8-pixel) block (Figs 6E to 6N). When the DRAM addresses traverse a boundary of the 5-bit by 5-bit (32-pixel by 32-pixel) block, a row address changes and a fifth-bit overflow is deteαed; just as in said Figs 6E to 6N when the memory addresses traverse a boundary of the 3-bit by 3- bit (8-pixel by 8-pixel) block, an MSB address changes and a third-bit overflow is deteαed. When the overflow control bit in the DRAM address generator is deteαed, a RAS* operation is performed by seleαing the row multiplexer and generating a RAS* strobe to change the row address and then to return to CAS* operations by seleαing the column multiplexer and generating multiple CAS* strobes to scanout pixels in the new address block; just as in Figs 6E to 6N when the overflow bit is deteαed, a re-addressing operation is performed to change the MSB address bits in the DRAM, thereby establishing a new address block, and then to return to scanout operations in order to scanout pixels in the new address block.
Single Dimensional Memory (Fig 4G) A multi-dimensional memory architeαure is disclosed in an embodiment of an image memory (Figs 6E to 6N). An alternate single dimensional embodiment thereof will now be discussed with reference to the block diagram shown in Fig 4G, which is consistent with the detailed memory schematic diagrams (i.e., Figs 6E to 6N). Various DRAMs, such as the Toshiba TC514256P DRAMs, implement a fast page mode read cycle and a fast page mode write cycle, which can be used to implement a single dimensional memory architeαure. See the Toshiba Corporation MOS MEMORY PRODUCTS DATA BOOK '86-7 at pages 119 et seq and particularly at page 125 therein. The fast page mode read cycle and the fast page mode write cycle can both use the multi-dimensional architeαure of the present invention, where the fast page mode read cycle will be discussed as representative of both, read and write cycles. Also, memory architeαure
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disclosed in Figs 6E to 6N shows a configuration combining both, read and write circuits. A single dimensional DRAM main memory architeαure, such as for a computer system, is shown in Fig 4G as illustrative of other memory configurations in accordance with the present invention. The ten LSBs of the address provide the ten column address bits for the DRAMs. The ten MSBs of the address provide the ten row address bits for the DRAMs. Hence, a high speed fast page memory read cycle DRAM scanout can be implemented for a 10- bit (1024-word) main memory region; just as the high speed X/Y scanout generates a 6-bit (64-pixel) two dimensional image region (Figs 6E to 6N). In the present DRAM configuration; a deteαor, such as an overflow deteOor, can be implemented to monitor the tenth-bit address generator carry control signal to control the RAS* and CAS* fast page memory read cycle signals; just as the overflow deteOor monitors the third-bit address generator carry control signal to control the XJY scanout and re-address (Figs 6E to 6N). Alternately, other types of deteOors can be implemented. Row and column multiplexers can be used (Fig 4G) to multiplex row and column addresses into each DRAM under control of the deteOor signal, such as the tenth-bit address generator carry control signal in the Fig 4G configuration; just as the third-bit address generator carry control signal generates an overflow signal to control the X Y scanout and re-address modes (Figs 6E to 6N). Decoders and drivers can also be used (i.e., Figs 4H to 4J), although these circuits are not shown in Fig 4G for simplicity. Operation of this configuration in the context of a microprocessor system will now be discussed. The address generator 431 A generates addresses having scanout (LSB) signals and re-address (MSB) signals associated with stored program processing; just as the X-address generator and the Y-address generator generate addresses having X/Y scanout (LSB) signals and re-address (MSB) signals associated with geometric processing in Figs 6E to 6N. Operating in the fast page mode read cycle with the multiplexer seleαing the column address (LSBs), the DRAMs 43 I F are accessed by the changing column addresses (LSBs) for a fixed row address (MSBs) as long as the addresses are within a 10-bit (1024- word) block; just as the RAMs are accessed by the changing LSB addresses for fixed MSB addresses as long as the addresses are within a 3-bit by 3-bit (8-pixel by 8-pixel) block in Figs 6E to 6N. When the DRAM addresses traverse a boundary of the 10-bit (1024-word) block, a row address changes and a tenth-bit overflow is detected; just as in Figs 6E to 6N when addresses traverse a boundary of the 3-bit by 3-bit (8-pixel by 8-pixel) block, an MSB address changes
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and a third-bit overflow is deteOed. When the overflow control bit in the DRAM address generator is deteOed, a RAS* operation is performed by seleαing the row multiplexer and generating a RAS* strobe to change the row address and then to return to CAS* operations by seleαing the column multiplexer and generating multiple CAS* strobes to scanout pixels in the new address block; just as in Figs 6E to 6N when the overflow control bit address generator is deteOed, a re-addressing operation is performed to change the MSB address bits and then to return to scanout operations to scanout pixels in the new address block.
Fig 4H Architeαure General A memory architeαure is disclosed in Figs 6E to 6N in an embodiment of an image memory. An alternate embodiment thereof will now be discussed with reference to Fig 4H, which is consistent with the detailed memory schematic diagrams in Figs 6E to 6N. The memory architeαure shown in Fig 4H uses fast page mode one megabit by-1 (one output bit) DRAM chips (such as the Toshiba TC51 1000P/J10 DRAMs), having a CAS chip seleα, having a CAS/RAS multiplexer, and not having output enable seleαion on-the-chip. Alternately, it can be implemented with other memory devices: such as with static column mode, nibble mode, or other mode devices; by-4 (four output bits), by-8 (eight output bits), or other output configuration; and other alternatives. It is arranged in an array of 8-columns (each column having 16-chips) by 16-rows (each row having 8-chips) for a total of 128 DRAM chips; providing 8-million words of memory. The 16-chip columns (columns 0 to 15) provide 16-bit words. Each column contains one million words, implicit in the one million addresses per DRAM chip. Hence, the total of 8 columns contain 8-million words. The vertical dashed lines inbetween the first row (at the top) and the last row (at the bottom) indicate 14 additional rows that are not shown for a total of 16 rows. The horizontal dashed lines inbetween the second column (the B column) and the right column (the H column) indicate 5 additional columns that are not shown for a total of 8 columns. Fig 4L is a detailed schematic of one configuration of the peripheral circuitry; the CAS multiplexers, the RAS multiplexers, the DRAM chip pinouts, the address bus, and the data bus; that can be used with the memory architeαure shown in Fig 4H. Many other peripheral circuitry configurations can also be implemented (i.e., Fig 6F).
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The address bits can be allocated, partitioned, and distributed in various ways; such as to the external scanout, the internal scanout, and the re-addressing operations. Also, the address bits can be arranged in accordance with single dimensional configurations and multi-dimensional configurations. For example, address bit assignments for a single dimensional configuration (the ONE column) and for a two dimensional configuration (the TWO column) with the allocation, partitioning, and distribution of address bits between external scanout, internal scanout, and re-addressing operations and the correspondence of address bits between a single dimensional configuration (the ONE column) and a two dimensional configuration (the TWO column) in accordance with the Fig 4H configuration is shown in the various Fig 4H Address Correspondence Tables herein. The CAS address bits and the RAS address bits are shown seleαed by the RAS* signal; implemented by enabling the CAS multiplexer or the RAS multiplexer, respeαively, to place the CAS address bits or the RAS address bits, respeαively, on the 10-bit address bus to be fanned-out to the DRAM chips. Generation of a RAS cycle causes the RAS* signal to seleα the RAS multiplexer for placing the RAS row address bits on the address bus and for strobing the DRAM chips with the RAS* signal. Generation of a CAS cycle causes the RAS* signal to seleα the CAS multiplexer for placing the CAS column address bits on the address bus and for strobing the DRAM chips with the CAS* signal. Multiplexers are readily available, such as the 74LS365 to 74LS368 hex multiplexers and the 8T95 to 8T98 hex multiplexer drivers. Use of such multiplexers are shown in Fig 6F. Alternately, other control signals can be used to seleα the RAS* and CAS* multiplexers and other multiplexer arrangements can be implemented. RAS signal steering is not shown in Fig 4H. However, RAS signal steering could also be used to seleα the column of DRAM chips to receive a RAS* signal strobe, such as in the same way that CAS signal steering is implemented. In this Fig 4H configuration; RAS signal steering is not shown because it is not necessary for RAS steering to seleα the column of DRAM chips. This is because, for this display configuration, it is permissible to load the same RAS address bits into all of the DRAM chips for each RAS cycle. Also, for this Fig 4H external scanout configuration, it is advantageous to load the same RAS address bits into all of the DRAM chips for each RAS cycle because the external scanout may be considered to be an extension of the internal scanout and hence is facilitated by the same block address, the RAS row address bits, being the same for all of the DRAM chips.
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1 WRITE signal steering is not shown in Fig 4H. However, WRITE signal ( w*
2 steering could also be used to seleα the column of DRAM chips for write
3 operations, such as in the same way that CAS signal steering is implemented. In
4 this Fig 4H configuration; write signal steering is not shown because it is not
5 necessary for write signal steering to seleα the column of DRAM chips. This is
6 because, for this Fig 4H configuration, it is permissible to invoke writing for all
7 DRAM chips and to select the particular column of DRAM chips with the steered
8 CAS* signal.
9 The single bit data output signal from each of the DRAM chips in a column
10 are grouped into one 16-bit word per column. Each one of the 16-rows
11 corresponds to a different one of the 16-bits in the data word. The
12 corresponding output data bit in each of the 8-columns (all of the 8-bits in the
13 same row) are ORed together, and the one data bit in each group of ORed row
14 data bits (the output data bit corresponding to the column seleαed by the
15 steered CAS signal) is seleOed and all of the other 7-bits ORed therewith are
16 non-seleOed. This ORing can be implemented by tristate outputs, such as
17 controlled by an output enable signal or by a CAS* signal; by logical AND-OR
18 gates; or by other well known methods. For the Fig 4H configuration, CAS
19 controlled tristate outputs are assumed; where the single column of DRAM chips
20 that are seleαed with the steered CAS* signal are output-enabled while all of the
21 other seven columns of DRAM chips that are non-seleOed with the steered CAS
22 signals are output disabled.
23 The 16-bit output data bus from the columns of DRAM chips can be
24 processed with a bi-direOional buffer, such as the Intel 8216 bi-direαional
25 buffers shown in Figs 6G to 6N. The bi-direOional buffer facilitates sharing of
26 the data bus for both writing (inputting) and reading (outputting) of data.
27 The address input lines 400A to 400Z (Fig 4H) are the input lines to the
28 memory array from the address generators. The address input lines represent
29 address input internal scanout lines 400A to 400j, address input external scanout 30. lines 400V to 400X, and address input re-addressing lines 400K to 400U.
31 Address input lines 400Y and 400Z are unused in this Fig 4H configuration and
32 symbol 400O is not used for the sake of clarity. Single dimensional address
33 signals from the least significant bit address signal A0 to the most significant bit
34 address signal A22 and two dimensional address signals from the X-address least 5 significant bit AX0 to the X-address most significant bit AX10 and from the Y- 6 address least significant bit AYO to the Y-address most significant bit AY1 1 are 7 assigned to the address input lines 400A to 400X. 8
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SUB
First Fig 4H Configuration In the first Fig 4H configuration shown in the FIRST FIG 4H ADDRESS CORRESPONDENCE TABLE, the least significant bits are assigned to internal scanout and the middle significant bits are assigned to external scanout for higher speed operations while the more significant bits are assigned to re- addressing. In addition, the most significant bit, the A22 or AY1 1 bit, is assigned to external scanout for board seleαion, such as for a multi-board configuration; as disclosed with reference to Figs 6E to 6N. This configuration is discussed in more detail below. In a single dimensional addressing configuration (the ONE column), such as used in a computer main memory, the address is divided into ten MSBs (the RAS address bits; A12 to A21) and ten LSBs (the CAS address bits; AO to A9). The A charaOer designates an address bit and the number designates the significance of the bit, with zero being the least significant bit. Also, the addresses are further divided into two CAS-steered external scanout bits (A10 and A1 1) and a board seleα CAS-steered board seleα scanout bit (A22). In a two dimensional addressing configuration (the TWO column), such as used in a display image memory, the addresses are divided into ten MSBs (the RAS address bits; AX6 to AX10 and AY6 to AY10) and ten LSBs (the CAS address bits; AXO to AX4 and AYO to AY4). The A charaOer designates an address bit; the X or Y charaOers designate the X-dimension and the Y-dimension, respeαively; as disclosed with reference to Figs 6E to 6N; and the number designates the significance of the bit, with zero being the least significant bit. Also, the addresses are further divided into two CAS-steered external scanout bits (AX5 and AY5) and a board seleα CAS-steered board seleO scanout bit (AY11 ). CAS signal steering selects the column of DRAM chips to receive a CAS signal strobe. This facilitates external scanout; as disclosed with reference to Figs 6E to 6N; by seleαing different columns of RAM IC chips for different combinations of external scanout address bits. CAS signal steering can be implemented with a decoder, such as a 74AS138 decoder, that is gated with the CAS* signal. In a two dimensional addressing configuration, such as used in a display image memory; the CAS* signal is steered to one of eight outputs with three address bits (AX5, AY5, and AY1 1). Alternately, in a single dimensional addressing configuration, such as used in a computer main memory; the CAS* signal is steered to one of eight outputs with three address bits (A10, A1 1, and A22; respeOively). See the FIRST FIG 4H ADDRESS CORRESPONDENCE TABLE. For a multi-board memory partitioning, one of the three address bits (i.e., A22 or AY1 1) can be provided as an uncomplemented signal for one of the
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memory boards and can be provided as a complemented signal for another one of the memory boards; as discussed with reference to Figs 6E to 6N. The relationship between the groupings of bits will now be discussed for the first single dimensional configuration. The internal scanout bits (A0 to A9) are adjacent therebetween so that aOivity in the least significant bits is within the internal scanout region. The external scanout bits (A10 and A1 1) are adjacent therebetween so that aOivity in the middle significant bits is within the external scanout region and the external scanout bits (Al 0 and A1 1 ) are adjacent to the internal scanout bits so that aOivity in the least significant bits and in the middle significant bits is within the scanout (internal and external) region. The RAS re- addressing bits (A12 to A21) are adjacent therebetween so that aOivity in the most significant bits is within the re-addressing region and the re-addressing bits (A12 to A21) are adjacent to the external scanout bits to facilitate the above internal scanout and external scanout with a minimum of slow down from re- addressing operations. The most significant bit (A22) is assigned to an external scanout conneOion to implement board seleOion. The relationship between the groupings of bits will now be discussed for the first two dimensional configuration. The internal scanout bits (AXO to AX4 and AYO to AY4) are adjacent therebetween so that aOivity in the least significant bits is within the internal scanout region. The external scanout bits (AX5 and AY5) are adjacent therebetween so that aOivity in the middle significant bits is within the external scanout region and the external scanout bits are adjacent to the internal scanout bits so that aOivity in the least significant bits and in the middle significant bits is within the scanout (internal and external) region. The RAS re- addressing bits (AX6 to AX10 and AY6 to AY10) are adjacent therebetween so that aOivity in the most significant bits is within the re-addressing region and the re-addressing bits are adjacent to the external scanout bits to facilitate the above internal scanout and external scanout with a minimum of slowdown from re- addressing operations. The most significant bit (AY1 1) is assigned to an external scanout conneOion, such as to implement board seleOion. For the two dimensional configuration; the internal scanout bits are arranged in a square array having an equal number of least significant X-address bits and Y-address bits; the external scanout bits are arranged in a square array having an equal number of middle significant X-address bits and Y-address bits; the combination of internal scanout bits and external scanout bits (AXO to AX5 and AYO to AY5) are arranged in a square array having an equal number of less significant X-address bits and Y-address bits; and the re-addressing bits are arranged in a square array having an equal number of most significant X-address
bits and Y-address bits. This facilitates a square array for scanout; the internal scanout bits and/or the external scanout bits; to maximize scanout operations and to minimize re-addressing operations for a configuration {i.e., a two dimensional display configuration) that is suitable for such square array enhancements. Alternately, non-square arrays may be provided from the teachings herein to enhance configurations that are suitable for such non-square array enhancements; i.e., a two dimensional configuration having a non-square number of internal scanout bits or a two dimensional configuration having a non-square number of external scanout bits. Alternately, other square and non- square arrays may be provided from the teachings herein to enhance memory performance or other memory charaOeristics.
Second Fig 4H Configuration The second Fig 4H configuration shown in the SECOND FIG 4H ADDRESS CORRESPONDENCE TABLE is similar to the first Fig 4H configuration shown in the FIRST FIG 4H ADDRESS CORRESPONDENCE TABLE except that the external scanout bit 400X has been reassigned to a less significant external scanout bit position. This assigns all of the internal scanout bits to the less significant bit positions, all of the external scanout bits to the middle significant bit positions, and all of the RAS re-addressing bits to the most significant bit positions. The purpose is to increase the scanout page size for enhanced performance. In particular, the external scanout bit 400X is assigned to a middle significant external address bit and the more significant address bits are each moved down to a one bit more significant position in order to make room for bit 400X. ~ For the two dimensional configuration; the external scanout bits, which were arranged in a square array having an equal number of middle significant X- address bits and Y-address bits in said first Fig 4H configuration, are now arranged in a non-square array (AX5, AY5, and AX6) having an unequal number of middle significant X-address bits (2) and Y-address bits (1) in said second Fig 4H configuration. Alternately, other square and non-square arrays may be provided from the teachings herein to enhance memory performance or other memory charaOeristics.
Third Fig 4H Configuration The third Fig 4H configuration shown in the THIRD FIG 4H ADDRESS CORRESPONDENCE TABLE is similar to the second Fig 4H configuration shown in the SECOND FIG 4H ADDRESS CORRESPONDENCE TABLE except that the
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external scanout bits and the internal scanout bits have been interchanged and the less significant two dimensional bits (AX and AY) have been reassigned. This assigns the external scanout bits to the less significant bit positions, the internal scanout bits to the middle significant bit positions, and the RAS re-addressing bits to the most significant bit positions. The purpose is to place the external scanout bits in the more active LSB positions, such as for a three dimensional external scanout configuration and such as for a configuration having higher speed external scanout compared to internal scanout. The relationship between the groupings of bits will now be discussed for the third two dimensional configuration. The external scanout bits (AXO, AX1, and AYO) are adjacent therebetween so that aOivity in the least significant bits is within the external scanout region. The internal scanout bits (AX2 to AX6 and AY1 to AY5) are adjacent therebetween so that aOivity in the middle significant bits is within the internal scanout region and the external scanout bits (AXO, AX1, and AYO) are adjacent to the internal scanout bits so that aOivity in the least significant bits and in the middle significant bits is within the scanout (internal and external) region. The RAS re-addressing bits (AX7 to AX10 and AY6 to AY11) are adjacent therebetween so that aOivity in the most significant bits is within the re-addressing region and the re-addressing bits are adjacent to the external scanout bits to facilitate the above internal scanout and external scanout with a minimum of slow down from re-addressing operations. For the two dimensional configuration; the external scanout bits are arranged in a nearly square array having a nearly equal number of least significant X- address bits and Y-address bits; the internal scanout bits are arranged in a square array having an equal number of middle significant X-address bits and Y-address bits; the combination of internal scanout bits and external scanout bits (AXO to AX6 and AYO to AY5) are arranged in a nearly square array having a nearly equal number of less significant X-address bits and Y-address bits; and the re-addressing bits are arranged in a square array having an equal number of most significant X- address bits and Y-address bits. This facilitates a nearly square array for scanout; the internal scanout bits and/or the external scanout bits; to maximize scanout operations and to minimize re-addressing operations for a configuration (i.e., a two dimensional display configuration) that is suitable for such square or nearly square array enhancements. Alternately, non-square arrays may be provided from the teachings herein to enhance configurations that are suitable for such non-square array enhancements; i.e., a two dimensional configuration having a non-square number of internal scanout bits or a two dimensional configuration having a non-square number of external scanout bits. Alternately, other square
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and non-square arrays may be provided from the teachings herein to enhance memory performance or other memory charaOeristics.
Forth Fig 4H Configuration The forth Fig 4H configuration shown in the FORTH FIG 4H ADDRESS CORRESPONDENCE TABLE is similar to the second Fig 4H configuration shown in the SECOND FIG 4H ADDRESS CORRESPONDENCE TABLE except that the external scanout bits and the internal scanout bits have been intermixed and the two dimensional AX and AY address bits have been reassigned. The purpose is to illustrate another alternate configuration in accordance with the present invention. For example, in a configuration having memory speeds that are comparable for both, internal scanout and for external scanout, internal scanout address bits and external scanout address bits can be intermixed without the need to slow down memory operations when operations traverse between internal scanout and external scanout operations. Other intermixed configurations can be provided, where the internal scanout bits, external scanout bits, and RAS re-addressing bits can be otherwise intermixed; such as by assigning the internal scanout bits to the least significant bit positions and by intermixing the external scanout bits and RAS re-addressing bits in the more significant bit positions; or such as other configurations of address bit intermixing.
Fifth Fig 4H Configuration The fifth Fig 4H configuration shown in the FIFTH FIG 4H ADDRESS CORRESPONDENCE TABLE is similar to the forth Fig 4H configuration shown in the FORTH FIG 4H ADDRESS CORRESPONDENCE TABLE except that the external scanout bits, the internal scanout bits, and the re-addressing bits have been intermixed and the two dimensional AX and AY address bits have been reassigned. The purpose is to illustrate another alternate configuration in accordance with the present invention. However, this intermixed configuration may have reduced performance for a configuration having slower re-addressing operations compared to scanout operations. This is because LSB aOivity can invoke re-addressing operations. However, this configuration is shown for completeness. Other intermixed configurations can be provided, where the internal scanout bits, external scanout bits, and RAS re-addressing bits can be otherwise intermixed; such as by assigning the internal scanout bits to the least significant bit positions and by intermixing the external scanout bits and RAS re- addressing bits in the more significant bit positions; or such as other
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configurations of address bit intermixing.
Sixth Fig 4H Configuration The sixth Fig 4H configuration shown in the SIXTH FIG 4H ADDRESS CORRESPONDENCE TABLE is similar to the third Fig 4H configuration shown in the THIRD FIG 4H ADDRESS CORRESPONDENCE TABLE except that the address lines associated with the external scanout bits have been intermixed therebetween and have been seleOively complemented, the address lines associated with the internal scanout bits have been intermixed therebetween and have been seleOively complemented, and the address lines associated with the re-addressing bits have been intermixed therebetween and have been seleOively complemented. The purpose is to illustrate another alternate configuration in accordance with the present invention where the address lines within a group (i.e.; internal scanout, external scanout, and re-addressing groups) can be interchanged and complemented without affeαing the operation of the memory system. Other intermixed and complemented configurations can be provided, where the internal scanout bits, external scanout bits, and RAS re-addressing bits can be otherwise intermixed and complemented.
Seventh Fig 4H Configuration The seventh Fig 4H configuration shown in the SEVENTH FIG 4H ADDRESS CORRESPONDENCE TABLE is similar to the second Fig 4H configuration shown in the SECOND FIG 4H ADDRESS CORRESPONDENCE TABLE except that, for the two dimensional configuration, the address lines associated with the internal scanout bits, external scanout bits, and re-addressing bits have been changed from square or nearly square arrays to non-square arrays. For example, the address lines associated with the internal scanout bits have been changed to be long in the X-dimension (AXO to AX7) and short in the Y-dimension (AYO and AY1); the address lines associated with the external scanout bits have been changed to be long in the X-dimension (AX8 and AX9) and short in the Y- dimension (AY2); and the address lines associated with the re-addressing bits have been changed to be long in the Y-dimension (AY3 to AY11) and short in the X-dimension (AX10). The purpose is to illustrate another alternate two dimensional configuration in accordance with the present invention where the address lines within a group (i.e.; internal scanout, external scanout, and re- addressing groups) are non-square. For example, such a non-square configuration can be used in conjunOion with processors having a preferred dimension and a non-preferred dimension.
Fig 41 ArchiteOure General The quantity of internal scanout addresses is typically constrained by IC chip complexity, pinouts, and other well known IC constraints. The quantity of external scanout is not as limited because the scanout logic is external to the IC chip, such as on a PC board or on a plurality of PC boards, and hence can be expanded to 64 RAM chips (the Mitsubishi RAM configuration); 128 RAM chips (the Fig 4H to Fig 4K Toshiba RAM configurations); 1024 RAM chips; 16384 RAM chips (the Fig 41 Toshiba RAM configuration); 65536 RAM chips; or other number of RAM chips. For example, the Fig 4H configuration has a 23-bit address register (or registers) with 10 internal scanout bits, 3 external scanout bits, and 10 re-addressing bits. It can be expanded to the Fig 41 configuration having a 30-bit address register (or registers) with 10 internal scanout bits, 10 external scanout bits, and 10 re-addressing bits. The 10 external scanout bits can be decoded in a single dimensional scanout decoder with 10-bit decoder logic to generate 1024 decoded output signals in response to the 10 encoded input address signals. Each of the 1024 decoded output signals can seleα a DRAM column; i.e., a 16 chip column for the Fig 4H configuration (see Fig 41) or a 4-chip column for the Fig 4J configuration. The memory architeαure shown in Fig 4H supra is the same as the memory shown in Fig 41; except that the board seleα bit is grouped with the external scanout bits for simplicity of discussion and except that the external scanout address has been expanded from 3-bits (400V to 400X) to 10-bits (400V to 400AE) to illustrate the extensive memory expansion capability in accordance with the present invention. This address expansion extends the number of DRAM chips from 128 DRAM chips in 8-columns to 16384 DRAM chips in 1024 columns. This also extends the number of words from 8-million words to 1 -billion words. As with the Fig 4H configuration; the memory architeOure shown in Fig 41 uses fast page mode one megabit by-1 (one output bit) DRAM chips (such as the Toshiba TC51 1 O00P/J10 DRAMs), having a CAS chip seleα, having a CAS/RAS multiplexer, and not having output enable seleOion. In contrast to Fig 4H; it is arranged in an array of 1024-columns (each column having 16-chips) by 16-rows (each row having 1024-chips) for a total of 16384 DRAM chips; providing 1- billion words of memory. The 16-chip columns (columns 0 to m) provide 16-bit words. Each column contains one million words, implicit in the one million addresses per DRAM chip. Hence, the total of 1024-coiumns contain 1 -billion
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words. The vertical dashed lines inbetween the first row (at the top) and the last row (at the bottom) indicate 14 additional rows that are not shown for a total of 16 rows. The horizontal dashed lines inbetween the second column (the B column) and the right column (the m column) indicate 1021 additional columns that are not shown for a total of 1024 columns. The address input lines 400A to 400AE (Fig 41) are the input lines to the memory array from the address generators. The address input lines represent address input internal scanout lines 400A to 400J, address input external scanout lines 400V to 400AE, and address input re-addressing lines 400K to 400U. Single dimensional address signals from the least significant bit address signal AO to the most significant bit address signal A29 and two dimensional address signals from the X-address least significant bit AXO to the X-address most significant bit AX15 and from the Y-address least significant bit AYO to the Y- address most significant bit AY15 are assigned to the address input lines 400A to 400AE. The second Fig 41 configuration is disclosed below, similar to the second Fig 4H configuration supra. The first and the third to seventh Fig 41 configurations are not explicitly disclosed because the disclosure of the first and the third to seventh Fig 41 configurations are similar to the first and the third to seventh Fig 4H configurations discussed above and hence the first and the third to seventh Fig 41 configurations can readily be generated by one skilled in the art from the first and the third to seventh Fig 4H configurations discussed above and the second Fig 41 configuration discussed below.
Fig 41 Configuration As in the second Fig 4H configuration; in the second Fig 41 configuration shown in the FIG 41 ADDRESS CORRESPONDENCE TABLE, the least significant bits are assigned to internal scanout and the middle significant bits are assigned to external scanout for higher speed operations while the more significant bits are assigned to re-addressing. in a single dimensional addressing configuration (the ONE column), such as used in a computer main memory, the address is divided into ten MSBs (the RAS address bits; A20 to A29) and ten LSBs (the CAS address bits; AO to A9). The A charaOer designates an address bit and the number designates the significance of the bit, with zero being the least significant bit. Also, the addresses are further divided into ten CAS-steered external scanout bits (Al 0 and Al 9). In a two dimensional addressing configuration (the TWO column), such as used in a display image memory, the addresses are divided into ten MSBs (the
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RAS address bits; AX10 to AX14 and AY10 to AY14) and ten LSBs (the CAS address bits; AXO to AX4 and AYO to AY4). The A charaOer designates an address bit; the X or Y charaOers designate the X-dimension and the Y- dimension, respeOively, as disclosed with reference to Figs 6E to 6N; and the number designates the significance of the bit, with zero being the least significant bit. Also, the addresses are further divided into ten CAS-steered external scanout bits (AX5 to AX9 and AY5 to AY9).
Fi 4l ArchiteOure General A memory architeOure is disclosed in Figs 6E to 6N in an embodiment of an image memory. An alternate embodiment thereof will now be discussed with reference to Fig 4J, which is consistent with the detailed memory schematic diagrams in Figs 6E to 6N. The memory architeOure shown in Fig 4J uses fast page mode one megabit by-4 (four output bits) DRAM chips (such as the Toshiba TC514256P/J10 DRAMs), having an output enable chip seleO, having a CAS/RAS multiplexer, and not having CAS steering. Alternately, it can be implemented with other memory devices: such as with static column mode, nibble mode, or other mode devices; by-1 (one output bit), by-8 (eight output bits), or other output configuration; and other alternatives. It is arranged in an array of 32-columns (each column having 4 chips) by 4 rows (each row having 32 chips) for a total of 128 DRAM chips; providing 8-million words of memory. The 4-chip columns (columns 0 to 3) provide 16-bit words. Each column contains 256K words, implicit in the 256K addresses per DRAM chip. The total of 32 columns hence contain 8-million words. The vertical dashed lines inbetween the first row (at the top) and the last row (at the bottom) indicate two additional rows that are not shown for a total of 4 rows. The horizontal dashed lines inbetween the second column (the B column) and the right column (the AF column) indicate 29 additional columns that are not shown for a total of 32 columns. Fig 4L is a detailed schematic of one configuration of the peripheral circuitry; the CAS multiplexers, the RAS multiplexer, the DRAM chip pinouts, the address bus, and the data bus; that can be used with the memory architeOure shown in Fig 4J. Many other peripheral circuitry configurations can also be implemented (i.e., Fig 6F). The address bits can be allocated, partitioned, and distributed in various ways; such as to the external scanout, the internal scanout, and the re-addressing operations. Also, the address bits can be arranged in accordance with single
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dimensional configurations and multi-dimensional configurations. For example, address bit assignments for a single dimensional configuration (the ONE column) and for a two dimensional configuration (the TWO column) with the allocation, partitioning, and distribution of address bits between external scanout, internal scanout, and re-addressing operations and the correspondence of address bits between a single dimensional configuration (the ONE column) and a two dimensional configuration (the TWO column) in accordance with the Fig 4J configuration is shown in the various Fig 4J Address Correspondence Tables herein. The CAS address bits and the RAS address bits are shown seleOed by the RAS* signal; implemented by enabling the CAS multiplexer or the RAS multiplexer, respeOively, to place the CAS address bits or the RAS address bits, respeOively, on the 9-bit address bus to be fanned-out to the DRAM chips. Generation of a RAS cycle causes the RAS* signal to seleO the RAS multiplexer for placing the RAS row address bits on the address bus and for strobing the DRAM column chips with the RAS signal. Generation of a CAS cycle causes the RAS* signal to seleO the CAS multiplexer for placing the CAS column address bits on the address bus and for strobing the DRAM chips with the CAS* signal. Multiplexers are readily available, such as the 74LS365 to 74LS368 hex multiplexers and the 8T95 to 8T98 hex multiplexers. Use of such multiplexers are shown in Fig 6F. Alternately, other control signals can be used to seleO the RAS* and CAS* multiplexers and other multiplexer arrangements can be implemented. Neither CAS nor RAS signal steering is shown in Fig 4J. However, CAS signal steering and/or RAS signal steering could be used to seleα the column of DRAM chips to receive a CAS* or a RAS* signal strobe, such as in the same way that CAS signal steering is implemented in Fig 4H for external scanout. In this Fig 4J configuration; neither CAS signal steering nor RAS signal steering is shown. RAS signal steering is not shown for the same reasons that RAS signal steering is not shown for the Fig 4H configuration, as discussed with reference to Fig 4H. CAS signal steering is not shown because the output enable signal steering provides a IC chip seleO funαion. Alternately, CAS signal steering can be implemented in place of or in addition to output enable steering, such as discussed with reference to Fig 4H. For example, CAS signal steering can be implemented to provide write seleOion for a configuration where the output enable signal performs a chip seleO funαion for reading but not for writing. WRITE signal steering is not shown in Fig 4]. However, WRITE signal (W) steering could also be used to seleα the column of DRAM chips for write
operations, such as in the same way that CAS signal steering is implemented with reference to Fig 4H. In this Fig 4J configuration; write signal steering is not shown because it is not necessary for write signal steering to seleα the column of DRAM chips. This is because, for this Fig 4J configuration, it is permissible to invoke writing for all DRAM chips and to seleO the particular column of DRAM chips with the steered output enable signal. The four data output signals from each of the DRAM chips in a column are grouped into one 16-bit word per column. Each one of the 4-rows corresponds to a different group of four of the 16-bits in the data word. The corresponding output data bit in each of the 32-columns (all of the 32-bits corresponding in the same row) are ORed together, and the one data bit in each group of ORed row data bits (the output data bit corresponding to the column seleOed by the steered output enable signal) is seleαed and ail of the other 31 -bits ORed therewith are non-seleOed. This ORing can be implemented by tristate outputs, such as controlled by an output enable signal or by a CAS* signal; by logical AND-OR gates; or by other well known methods. For the Fig 4J configuration, output enable (OE) controlled tristate outputs are assumed; where the column of four DRAM chips that are seleαed with the steered output enable signal are output-enabled while all of the other columns of DRAM chips that are non- seleOed with the steered output enable signal are output disabled. The 16-bit output data bus from the columns of DRAM chips can be processed with a bi-direαional buffer, such as the Intel 8216 bi-direαional buffers shown in Figs 6G to 6N. The bi-direOional buffer facilitates the sharing of the data bus for both writing (inputting) and reading (outputting) of data. The address input lines 400A to 400Z (Fig 4J) are the input lines to the memory array from the address generators. The address input lines represent address input internal scanout lines 400A to 400J, address input external scanout lines 400V to 400Z, and address input re-addressing lines 400K to 400U. Symbol 400O is not used for the sake of clarity. Single dimensional address signals from the least significant bit address signal A0 to the most significant bit address signal A22 and two dimensional address signals from the X-address least significant bit AXO to the X-address most significant bit AX11 and from the Y- address least significant bit AYO to the Y-address most significant bit AY10 are assigned to the address input lines 400A to 400Z. The various Fig 4H configurations disclosed herein can be adapted to the Fig 4J architeOure by one skilled in the art from the teachings herein. For example, the Fig 4J configuration can be modified to have a most significant board seleO bit in accordance with the first Fig 4H configuration; can be modified to have
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the external scanout bits input to the least significant bits and the internal scanout bits input to the middle significant bits in accordance with the third Fig 4H configuration; can be modified to have the external scanout bits and the internal scanout bits intermixed in the least significant bits in accordance with the forth Fig 4H configuration; can be modified to have the external scanout bits, the internal scanout bits, and the re-addressing bits all intermixed in accordance with the fifth Fig 4H configuration; can be modified to have the address lines associated with the external scanout bits intermixed therebetween and seleOively complemented, to have the address lines associated with the internal scanout bits intermixed therebetween and selectively complemented, and to have the address lines associated with the re-addressing bits intermixed therebetween and selectively complemented in accordance with the sixth Fig 4H configuration; and can be modified to have the two dimensional address lines associated with the internal scanout bits, external scanout bits, and re-addressing bits implement non-square arrays in accordance with the seventh Fig 4H configuration. The second Fig 4J configuration is disclosed below, similar to the second Fig 4H configuration supra. The first and the third to seventh Fig 4J configurations are not explicitly disclosed because the disclosure of the first and the third to seventh Fig 4j configurations are similar to the first and the third to seventh Fig 4H configurations discussed above and hence the first and the third to seventh Fig 4J configurations can readily be generated by one skilled in the art from the first and the third to seventh Fig 4H configurations discussed above and the second Fig 4J configuration discussed below.
Fig 4J Configuration In the second Fig 4J configuration shown in the FIG 4J ADDRESS CORRESPONDENCE TABLE, the least significant bits are assigned to internal scanout and the middle significant bits are assigned to external scanout for higher speed operations while the more significant bits are assigned to re- addressing. This configuration is discussed in more detail below. In a single dimensional addressing configuration (the ONE column), such as used in a computer main memory, the addresses are divided into nine MSBs (the RAS address bits; A14 to A22) and nine LSBs (the CAS address bits; AO to A8). The A charaOer designates an address bit and the number designates the significance of the bit with zero being the least significant bit. Also, the addresses are further divided into five output enable steered external scanout bits (A9 to A13).
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In a two dimensional addressing configuration (the TWO column), such as used in a display image memory, the addresses are divided into nine MSBs (the RAS address bits; AX7 to AX11 and AY7 to AY10) and nine LSBs (the CAS address bits; AXO to AX4 and AYO to AY3). The A charaOer designates an address bit; the X or Y charaαers designate the X-dimension and the Y- dimension, respeOively, as disclosed with reference to Figs 6E to 6N; and the number designates the significance of the bit with zero being the least significant bit. Also, the addresses are further divided into five output enable steered external scanout bits (AX5, AX6, AY4, AY5, and AY6). Output enable signal steering selects the column of DRAM chips to be enabled with the output enable signal. This facilitates external scanout; as disclosed with reference to Figs 6E to 6N; by seleαing different columns of RAM chips for different combinations of external scanout address bits. Output enable signal steering can be implemented with a decoder, such as a 74AS138 decoder, that decode address bits. In a two dimensional addressing configuration, such as used in a display image memory; the output enable signal is steered to one of 32 outputs with five address bits (AX5, AX6, AY4, AY5, and AY6). Alternately, in a single dimensional addressing configuration, such as used in a computer main memory; the CAS* signal is steered to one of 32 outputs with five address bits (A9 to A13; respeOively). See the FIG 4J ADDRESS CORRESPONDENCE TABLE. In a configuration using 74AS138 decoders, four decoders can be used to decode the five address bits into the 32 output enable signals. This can be implemented by decoding two of the five address bits (i.e., AX5 and AX6) to seleO one of the four decoders and decoding each of the other three of the five address bits with the A, B, and C input ports on each of the four decoders. The relationship between the groupings of bits will now be discussed for the second single dimensional configuration. The internal scanout bits (AO to A8) are adjacent therebetween so that aOivity in the least significant bits is within the internal scanout region. The external scanout bits (A9 and A13) are adjacent therebetween so that aOivity in the middle significant bits is within the external scanout region and the external scanout bits (A9 and A13) are adjacent to the internal scanout bits so that aOivity in the least significant bits and in the middle significant bits is within the scanout (internal and external) region. The RAS re- addressing bits (A14 to A22) are adjacent therebetween so that aOivity in the most significant bits is within the re-addressing region and the re-addressing bits (A14 to A22) are adjacent to the external scanout bits to facilitate the above internal scanout and external scanout with a minimum of slow down from re- addressing operations.
The relationship between the groupings of bits will now be discussed for the second two dimensional configuration. The internal scanout bits (AXO to AX4 and AYO to AY3) are adjacent therebetween so that aOivity in the least significant bits is within the internal scanout region. The external scanout bits (AX5, AX6, AY4, AY5, and AY6) are adjacent therebetween so that aOivity in the middle significant bits is within the external scanout region and the external scanout bits are adjacent to the internal scanout bits so that aOivity in the least significant bits and in the middle significant bits is within the scanout (internal and external) region. The RAS re-addressing bits (AX7 to AX1 1 and AY7 to AY10) are adjacent therebetween so that aOivity in the most significant bits is within the re-addressing region and the re-addressing bits are adjacent to the external scanout bits to facilitate the above internal scanout and external scanout with a minimum of slow down from re-addressing operations. For the two dimensional configuration; the internal scanout bits are arranged in a nearly square array having a nearly equal number of least significant X- address bits and Y-address bits; the external scanout bits are arranged in a nearly square array having a nearly equal number of middle significant X-address bits and Y-address bits; the combination of internal scanout bits and external scanout bits (AXO to AX6 and AYO to AY6) are arranged in a square array having an equal number of less significant X-address bits and Y-address bits; and the re-addressing bits are arranged in a nearly square array having a nearly equal number of most significant X-address bits and Y-address bits. This facilitates a square array for scanout; the internal scanout bits and/or the external scanout bits; to maximize scanout operations and to minimize re-addressing operations for a configuration (i.e., a two dimensional display configuration) that is suitable for . such square array enhancements. Alternately, non-square arrays may be provided from the teachings herein to enhance configurations that are suitable for such non-square array enhancements; i.e., a two dimensional configuration having a non-square number of internal scanout bits or a two dimensional configuration having a non-square number of external scanout bits. Alternately, other square and non- square arrays may be provided from the teachings herein to enhance memory performance or other memory charaOeristics.
Fig 4K ArchiteOure Memory architeOure is disclosed herein for various DRAM applications (Figs 4F to 4]) and in an embodiment of an image memory (Figs 6K to 6N). An alternate embodiment thereof will now be discussed with reference to Fig 4K, which is consistent with the detailed memory schematic diagrams (i.e., Figs 6E to
6N). The memory architeOure shown in Fig 4K uses fast page mode one megabit by-4 DRAM chips (such as the Toshiba TC514256P/J10 DRAMs), having an output enable chip seleα, having a CAS/RAS multiplexer, and not having CAS steering. Alternately, it can be implemented with other memory devices: such as with static column mode, nibble mode, or other mode devices; by-1, by-8, or other output configuration; and other alternatives. It is arranged in an array of m-columns of chips by n-rows rows of chips (m-by-n array of DRAM chips). The rows of chips (rows A to m) define the number of words in the memory and columns of chips (columns 0 to n) define the number of bits per word. The vertical dashed lines inbetween the first row (at the top) and the last row (at the bottom) indicate (n-2) additional rows that are not shown for a total of n-rows. The horizontal dashed lines inbetween the second column (the B column) and the right column (the m-column) indicate (m-3) additional columns that are not shown for a total of m-columns. Fig 4K is shown in a form consistent with Figs 4H, 41, and 4J and the implementation and operation of the Fig 4K configuration can be understood from the discussions provided Figs 4H, 41, and 4J. In particular, the Fig 4] configuration has been updated to provide the Fig 4K configuration by providing steering for the CAS signals, by generalizing the number of data bits and the number of chips per column (n), by generalizing the number of columns of chips and the external scanout size (m), and by generalizing the number of RAS and CAS address bits.
Multiple Memory Configuration A multiple memory configuration 460 will now be discussed with reference to Fig 4T. This configuration illustrates various features of the present invention; including multiple memories, multiple deteαors, multiple delay circuits, address deteOion and memory seleOion, memory address partitioning, internal and external scanout, memory address multiplexing, memory address decoding, comparitor deteOor implementation, delay signal feedback to the address generator, and many other features. It also illustrates a configuration where each of a plurality of memories can be row addressed (or re-addressed) by a row address that is different from the row addresses of other memories and can be externally scanned out across the memory space from memory to memory each having different row addresses. The various teachings discussed for other configurations herein can be used with this Fig 4T configuration and the various teachings of this Fig 4T configuration can be used with the other configurations
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discussed herein. A multiple memory configuration is shown in Fig 4T. The subscript "0" is used to designate the circuits and signals associated with the first memory and the subscript "n" is used to designate the circuits and signals associated with the last memory. Other memories therebetween are indicated by a double headed arrow symbol ■■ -* below the reference numeral. Address generator 460A generates a memory address 460S to address memories 460R. Memory address 460S is composed of the least significant bits (LSBs) 460E, the next more significant bits 460D, the next more significant bits 460C, and the most significant bits (MSBs) 460B. The memory address can be partitioned in various ways. For example; memory address 460S can be implemented with 20 bits having 8 least significant bits (LSBs) 460E, 8 more significant bits 460D, 2 next more significant bits 460C, and 2 most significant bits (MSBs) 460B. Alternately; memory address 460S can be implemented with 28 bits having 10 least significant bits (LSBs) 460E, 10 more significant bits 460D, 5 next more significant bits 460C, and 3 most significant bits (MSBs) 460B. Alternately; memory address 460S can be implemented with 32 bits having 10 least significant bits (LSBs) 460E, 10 more significant bits 460D, 5 next more significant bits 460C, and 7 most significant bits (MSBs) 460B. many other configurations can also be implemented. Also; the memory address 460S can be assigned to various operations, such as shown in Figs 4H-4K and in the correspondence tables related thereto. One configuration will now be discussed with reference to Fig 4T. The least significant bits (LSBs) 460E are decoded by external scanout decoder 460F to generate external scanout decoded address signals 460H which are used to externally scanout one of the memories 460R. External scanout is discussed in detail herein, such as with reference to Figs 4H-4K. A sequence of enabling the output of a plurality of the memories 460R facilitates external scanout. In this configuration, each memory 460R can be implemented by a single memory chip or a plurality of memory chips. The external scanout signals 460H can be used to externally scanout the data in a seleαed one of the memories 460R. For example, when memory-0 is seleαed by memory seleα signal 460l 0 , then external scanout signals 460H will externally scanout memory-0, and when memory-n is seleOed by memory seleO signal 460l n , then external scanout signals 460H will externally scanout memory-n. The next more significant bits 460D are coupled as the column address bits to implement internal scanout operations and the still next more significant bits 460C are coupled as the row address bits to implement re-addressing
operations. Internal scanout and re-addressing operations are discussed in detail herein, such as with reference to Figs 4H-4K. The column address bits 460D and the row address bits 460C are controlled by the RAS or CAS signals with the RAS/CAS multiplexer 460K to multiplex the column address bits 460D and the row address bits 460C to generate the multiplexed RAS/CAS address bits 460T to address memories 460R. The most significant bits (MSBs) 460B are decoded by memory seleO decoder 460G to generate memory seleα decoded address signals 4601 to seleO the related memory 460R, the related deteαor 460J and 460L, and the related delay circuit 460N. The deteOor 460J and 460L and the related delay circuit 460N invoke a delay when appropriate through OR gate 460Q by generating delay command signal 460V to delay updating of address generator 460A. Delay signals 460P are shown gated by AND gates 460W in response to memory seleα signals 4601 so that only the seleαed comparitor 460L and delay circuit 460N are enabled to invoke a delay for re-addressing. Delay circuit 460N can be implemented in various ways, as previously discussed, including a one-shot circuit, a time constant circuit, a counter, a timer circuit, and other circuits. The delay signal 460V to the HOLD input of address generator 460A is schematically representative of various delay implementations, some of which are discussed in greater detail herein. For example, address generator 460A may be an address register in a microprocessor and the HOLD input excited by signal 460V may be the hold, or wait, or other such circuit of the microprocessor. Alternately, address generator 460A may be the address registers in Figs 6O-6R in a display processor and the HOLD input excited by signal 460V may be the clock gating circuit of Figs 6B.1, 6B.2, 6C, and 6D. In this comparitor deteOor implementation, buffer register 460] stores the row address 460C or the necessary portion thereof as the prior row address 460U. For example, buffer register 460J can be implemented to store the row address 460C, or the MSBs of row address 460C, or other appropriate part of row address 460C to facilitate a re-addressing comparison with comparitor 460L. DeteOor circuits are discussed in detail herein, where these deteαor teachings are intended to be usable with the Fig 4T configuration. The prior row address 460U is compared with the next row address 460C by comparitor 460L to generate comparitor signal 460M to aOivate delay circuit 460N to generate delay control signal 460P. The memory data lines can be implemented in various ways, such as in the form of a bidireOional data bus 460Y or with separate data lines from each memory. Various data buses are discussed herein, such as with reference to Figs
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4F-4L herein. For simplicity of discussion, only a single channel buffer register 460J, comparitor 460L, and delay circuit 460N are shown for each memory. Alternately, multiple channels can be implemented for each memory to provide multiple delays: such as a first delay for external scanout, a second delay for column addressing internal scanout, and a third delay for row re-addressing, which is discussed in greater detail herein. Various configurations can be implemented. For example, in a first configuration, the external scanout delay may be shorter and the re-addressing delay may be longer than the internal scanout delay and in a second configuration, the internal scanout delay may be shorter and the re-addressing delay may be longer than the external scanout delay. For simplicity of discussion, separate comparitor circuits 460L and delay circuits 460N are shown for each memory in Fig 4T. However, in various configurations comparitor circuits 460L and delay circuits 460N can be time- shared. For example, in various configurations such as the Fig 4T configuration, each memory is mutually exclusive of other memories and hence only one comparitor circuit 460L and delay circuit 460N is seleOed at a time. This can be implemented with a time shared comparitor circuit 460L and delay circuit 460N having the prior row address 460N and the next row address 460C seleOed by a multiplexer (not shown) to apply these signals to the time shared comparitor 460L and the time shared delay circuit 460N to deteα a re-addressing condition. Alternately, in other configurations, the memories are not mutually exclusive of each other and hence multiple comparitor circuits 460L and delay circuits 460N can be seleαed at a time. Memory seleα decoder 460G generates a plurality of decoded signals 0 to n 4601. Each decoder signal 4601 is used to seleα a different memory grouping of deteαor and delay circuits. The first memory seleO signal 460lø selects the first channel buffer register 460JQ, the first channel comparitor 460L 0 , the first channel delay circuit 460NQ, and the first memory 460RQ. Similarly; the last memory seleO signal 460l n selects the last channel buffer register 460J n , the last channel comparitor 460L n , the last channel delay circuit 460N n , and the last memory 460R n . In a configuration having multiple channels for each memory, memory seleα decoder 460G can be implemented to seleα multiple channels associated with each memory and then external scanout decoder 460F can be implemented to externally scanout the multiple channels associated with the seleOed memory. For simplicity of discussion, external scanout signals 460H are shown
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controlling memories 460R having select circuitry in the memory. However, for memory chips that do not have such external scanout control logic self contained, external scanout logic is implemented. Further, external scanout signals 460H may be combined with seleO signals 4601 for a combined memory seleO and external scanout. In other configurations, address generator 460A can be partitioned in other ways. For example, different address partitioning configurations are shown in Figs 4H-4K and in the correspondence tables related thereto. As discussed above, the memory address in Fig 4T is partitioned with the least significant bits (LSBs) 460E controlling external scanout through external scanout decoder 460F, with the next more significant bits 460D controlling internal scanout through RAS/CAS multiplexer 460K, with the next more significant bits 460C controlling re-addressing through RAS/CAS multiplexer 460K, and with the most significant bits (MSBs) 460B controlling memory seleOion through memory seleα decoder 460G. Alternate partitioning configurations can also be implemented, some of which are discussed with reference to Figs 4H-4K and with reference to the correspondence tables. For example, the memory address in Fig 4T can be alternately be partitioned with the least significant bits (LSBs) 460E controlling internal scanout through RAS/CAS multiplexer 460K, or controlling re-addressing through RAS/CAS multiplexer 460K, or controlling memory seleOion through memory seleO decoder 460G. Also, the memory address in Fig 4T can be alternately be partitioned with the next more significant bits 460D controlling external scanout through external scanout decoder 460E, or controlling re-addressing through RAS/CAS multiplexer 460K, or controlling memory seleOion through memory seleO decoder 460G. Also, the memory address in Fig 4T can be alternately be partitioned with the next more significant bits 460C controlling external scanout through external scanout decoder 460E, or controlling internal scanout through RAS/CAS multiplexer 460K, or controlling memory seleαion through memory seleO decoder 460G. Also, the memory address in Fig 4T can be alternately be partitioned with the most significant bits 460B controlling external scanout through external scanout decoder 460E, or controlling internal scanout through RAS/CAS multiplexer 460K, or controlling re-addressing through RAS/CAS multiplexer 460K. Further, the address groupings can be interspersed together. For example, the external scanout address bits 460E can be interspersed with the column address bits 460D, the row address bits 460C, or the seleα address bits 460B; the column address bits 460D can be interspersed with the external scanout address bits 460E, the row address bits 460C, or the seleα address bits
460B; the row address bits 460C can be interspersed with the external scanout address bits 460E, or the column address bits 460D, or the seleα address bits 460B; and the seleO address bits 460B can be interspersed with the external scanout address bits 460E, the column address bits 460D, or the row address bits 460C. Different combinations of these partitioning and coupling arrangements can readily be implemented with the teachings herein; such as the teachings relative to Fig 4T, Figs 4H-4K, and the correspondence tables. Various figures similar to those shown in Figs 4T and Figs 4H-4K and various tables similar to the correspondence tables can readily be implemented by one skilled in the art from the teachings herein to further illustrate each of these alternate configurations. Multiple memories can be implemented in various ways, such as in a distributed configuration and in an integrated configuration. For example, in a distributed configuration, deteOor logic can be implemented separate from the memory chips, such as on a memory controller chip that is used to control memory chips. This provides flexibility in implementing different memory configurations because standard memory chips can be used which need not be reconfigured for a particular memory controller configuration. In an integrated configuration, deteOor logic can be implemented on each of the memory chips. This provides simplicity of memory controller implementation and makes each memory chip more autonomous. Various integrated configurations will now be discussed. This effeOively implements a distributed memory configuration, makes the memory chips relatively independent and autonomous, and can increase performance. In certain applications it may cause redundancy. For example, with 16 by-1 DRAMs forming a 16 bit memory word all 16 memory chips may contain deteαor circuits although only a single deteαor circuit may be needed. This redundancy may involve only a small part of the chip circuitry. A memory chip having a deteαor (including a deteOor buffer register) can be partially self contained relative to its memory address or memory space. For example, each memory chip can keep track of its own re-addressing. Also, the memory chip can have configuration registers, which can be loaded upon system initialization or upon system configuring, and can have configuration logic to facilitate configuring each chip for its memory space (such as the memory block) and other memory architeOure variables (such as fast page mode, nibble mode, etc.). For a configuration register implementation, loading the first address, or the last address, etc. can define the address space for the chip because the
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addresses in a DRAM are continuous and because the number of addresses for the chip is known. The chip enable signal can be used to configure the address space or can be combined with the deteOor to define the address space because, in a one configuration, the DRAM address space is addressed whenever the DRAM is seleOed; such as when the chip is non-seleOed, the MSB register need not be loaded. Similarly, the deteOor can operate in response to a chip seleα, an output enable, a RAS strobe, etc. and combinations thereof which can also be used for enabling loading of the buffer register. SeleOive loading of the buffer register, whether implemented on-the-chip or off-the-chip, reduces the effeO of the address jumping around between many memory blocks and hence causing many re-addressings. For example, buffer register 460] may be seleOively loaded under control of seleα signal 4601 when the corresponding memory is addressed (Fig 4T). It can be implemented on a memory bank basis because the charaOerization of different memories can include different memory banks in the same memory. In this configuration, operation jumping between different memories (such as external scanout between different memories) having different address spaces and different memory blocks can be as fast as a spatial scanout because it does not have to re- address the memories even though memory blocks or memories are being changed. One criterion is whether the last operation in that memory was in the same block in that memory, not whether the last operation in the whole system was in that memory block. This is an important consideration. In this way, the external scanout can be extended not only to other chips in the same memory block but also to other chips in different memory blocks as long as the row addresses of the memory blocks in the other chips do not change from the previous row addresses in those other chips. As another example, the chips can be implemented to be in different address spaces because they do not have to be re-addressed to the same address MSBs (Fig 4T). A PC embodiment can be implemented having multiple memory banks (such as ten memory banks) using external address space deteOors (such as implemented off-the-chip) to enable loading the buffer registers, one for each memory bank, and using steered RAS signals for loading the buffer register (such as implemented on-the-chip). Alternately, the steered RAS can be implemented off-the-chip. In one configuration; the deteαors, delay circuits, and other related circuits for all of the memory banks can be implemented on a single memory controller chip where the inputs to the memory controller chip are addresses and the outputs from the memory controller chip are chip seleα and deteαor
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output signals to invoke delays and to seleα chips and steer signals. Consequently, the output signals will be a relatively small number of lines per memory bank. Hence, many memory banks can be implemented with a single memory controller chip having an acceptable number of pinouts that facilitates single chip implementation. Because of the scanout in other memory banks of other chips without re- addressing, as discussed elsewhere herein, much of the re-addressing that might be thought to be required for a stored program computer (or other such processor that changes memory addresses alot) is significantly reduced. Hence, even a stored program computer can have a high scanout duty cycle and a low re-addressing duty cycle in accordance with this feature of the present invention. A chip seleO signal (such as signal 432H in Fig 4E) decoded with decoder logic (such as chip seleα decoder logic 432J in Fig 4E) external to the memory chip can be used to seleo the chip deteOor logic (such as buffer 414A and comparitor 422 in Fig 4E). Alternately, the chip seleo decoder logic (such as decoder logic 432J in Fig 4E) can be implemented on the memory chip by a chip seleO configuration register (such as register 435A in Fig 4M and register 450G in Figs 4P and 40) storing a chip seleO configuration and by a comparitor (such as buffer 414A and comparitor 422 in Fig 4E) that compares the chip seleO configuration with the address to generate the seleO signal (such as signal 432H in Fig 4E) to determine when the chip is to be seleOed. DeteOor signals from different memory chips can be free-ORed or wire- ORed or logically ORed or NVL NANDed or otherwise combined to generate a signal to the delay circuit; such as a DTACK signal, or a HOLD signal, or a WAIT signal, or other delay signal. Multiple deteOor and delay circuits can be implemented in various ways. For example, the previously disclosed multi-tap adder can be implemented for multiple overflow deteOors in conjunOion with multiple delay circuit. This can be implemented by replicating the delay circuit in Fig 6C for each tap and by changing the two U21 B delay flip-flops to one, two, three, etc. delay flip-flops for different delays as needed. Alternately, other multiple delay circuits and deteOors can also be implemented.
HARDWARE IMPLEMENTATION IntroduOion Memory related hardware can be implemented in various ways; such with discrete components on a PC board, on a separate memory controller IC chip, together with memory on a memory IC chip, and/or together with a processor on
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a processor IC chip. For example, deteOor circuits are disclosed herein with reference to Figs 4D and 4M for being resident with a stored program computer on a computer chip. Also, a deteOor circuit is disclosed herein with reference to Fig 4E for being implemented off the processor chip, such as with discrete logic or with a custom IC chip. Also, delay circuits are disclosed herein for being resident with a stored program computer on a computer chip. Also, deteαor circuits and delay circuits are disclosed herein with reference to Figs 6C and 6W for being implemented with discrete components on a wire wrap board. Also, deteOor circuits and delay circuits are disclosed herein with reference to Figs 6C and 6W that can be implemented on a separate memory controller custom IC chip or can be implemented together with a processor on the processor IC chip. In view of the above, it is herein intended that the inventions disclosed herein be implementable in various ways; including distributing or partitioning portions of the circuitry or all of the circuitry onto various IC chips that can include a processor IC chip, a memory IC chip, and a memory controller chip and distributing or partitioning portions of the circuitry or all of the circuitry onto a custom IC controller chip. For example; a memory re-addressing and/or refresh deteOor circuit can be implemented on a processor IC chip together with the processor, can be implemented on a memory IC chip together with the memory, can be implemented on an IC chip having an address register together with the address register, can be implemented on a custom memory controller IC chip, can be implemented on a PC board with discrete components, or can be implemented in various other ways. Also; a memory refresh controller circuit can be implemented on a processor IC chip together with the processor, can be implemented on a memory IC chip together with the memory, can be implemented on an IC chip having an address register together with the address register, can be implemented on a custom memory controller IC chip, can be implemented on a PC board with discrete components, or can be implemented in various other ways. Also, a memory scanout and re-addressing controller circuit can be implemented on a processor IC chip together with the processor, can be implemented on a memory IC chip together with the memory, can be implemented on an IC chip having an address register together with the address register, can be implemented on a custom memory controller IC chip, can be implemented on a PC board with discrete components, or can be implemented in various other ways. Also, a memory delay circuit can be implemented on a processor IC chip together with the processor, can be implemented on a memory IC chip together with the memory, can be implemented on an IC chip having an address register together with the address register, can be implemented on a
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custom memory controller IC chip, can be implemented on a PC board with discrete components, or can be implemented in various other ways. Also; a memory deteαor, a memory refresh controller, and a memory scanout and re- addressing controller can be implemented together on a memory controller IC chip.
Custom IC Chip Implementation Various memory control arrangements will now be discussed in the context of custom IC chip implementation. These arrangements are also direOly applicable to other implementations; such as implementations having discrete IC chips on a PC board or wire wrap board. Also; various memory control arrangements are discussed herein without specific discussions of being IC chip implementations. These arrangements are also direOly applicable to IC chip implementations; such as IC chip implementations of stored program computers, filter processors, and other computers and processors disclosed herein. Also; certain memory control arrangements are discussed herein with specific mention of being particularly suitable for IC chip implementation. These arrangements are placed in other sections herein for convenience of organization. Particular advantages can be achieved by configuring IC chips having features indicated by the present invention. For example, various on the chip configurations and off the chip configurations are disclosed herein, showing advantages that can be achieved with on the chip configurations. For example, a deteOor on a processor chip configuration and a deteOor off a processor chip configuration are disclosed herein, showing advantages that can be achieved with the on the chip configuration for a processor IC chip. Also, a deteOor on a memory chip configuration and a deteOor off a memory chip configuration are disclosed herein, showing advantages that can be achieved with the on the chip configuration for a memory IC chip. Other related features that are particularly appropriate for implementing on-the-chip are disclosed below. Particular advantages can be obtained by configuring the LSBs of the address, which are the address bits that are most often changed in sequence or in close proximity to each other, to be implemented in the scanout dimension (the row dimension in the Mitsubishi RAM configuration and the column dimension in the Toshiba DRAM configuration) and by configuring the MSBs of the address to be implemented in the re-addressing dimension (the column dimension in the Mitsubishi RAM configuration and the row dimension in the Toshiba DRAM configuration). Particular advantages can be obtained by configuring computer instruαions
so that they maximize use of the same block of memory to minimize re- addressing operations and to maximize scanout operations. Particular advantages can be obtained if the system of the present invention is utilized in particular forms. For example, performance can be enhanced by executing instruOions that can be scanned out with a minimum of re-addressing, implying maximizing use of instruOions within a block and minimizing memory operations in other blocks. For example, this can be implemented by increasing use of sequential instruOions, by increasing use of instruOions within a block, by reducing use of long transfer instruOions to addresses outside of the current block, by reducing use of operands in other blocks, and other such implementations.
Detepor Circuit? Particular advantages can be obtained by providing deteOor circuits on memory chips. For example, one or more deteOor circuits associated with a memory chip can be readily integrated on the memory chip to operate in conjunαion with the address signals contained thereon. DeteOor signals can be output from the chip and can be combined with deteOor signals from other chips to invoke time delays. Alternately, in configurations where time delay circuits are contained on-the-chip with the related deteαor circuits, time delay signals can be output from the chip and can be combined with time delay signals from other chips to execute time delays. Combining of multiple chip signals can be performed with well known combining circuits, such as the circuits used to combine data output signals. Such combining circuits can be implemented with gates (i.e.; AND, OR, tristate, etc. gates), wired-OR circuits, and other circuits.
Micro-Operation Circuits Particular advantages can be obtained by generating micro-operation signals during instruOion execution that are appropriate for controlling memory scanout and re-addressing operations, CAS and RAS modes, clock gating, etc. For example, a deteOor can be used to deteα scanout and re-addressing conditions to control a clock gating circuit, or a wait state circuit, or a disable circuit, or other such circuit within the processor, on the processor IC chip, or otherwise closely coupled to the processor. Particular advantages can be obtained by generating micro-operation signals during instruOion execution that are appropriate for controlling refreshing. For example, a signal can be generated that identifies a portion of an instruOion that
leaves memory available for refreshing; where this signal can be used to control refreshing of the memory, such as on a time available basis. Also, a refresh address counter can be implemented to count the time available refresh operations to aid in determining that the proper number of refreshes have been performed in the required period of time (i.e., 512 refresh operations in 8- milliseconds). Further, an automatic refresh controller can be provided to determine when the time available refresh operations are not sufficient and to control generation of additional refresh operations, such as cycle stealing refresh operations (Fig 4P). A computer micro-operation, or micro-instruOion, or state arrangement that is particularly suitable for use with a custom IC chip implementation will now be discussed with reference to Fig 4M. A plurality of deteOor signals; such as micro-operation deteOor signals, micro-instruOion deteOor signals, state deteOor signals, or other deteOor signals; which are related to memory operations; such as re-addressing and refresh memory operations; are generated on IC chip 434A for outputting from IC chip 434A through pinouts to be used as memory deteOor signals to invoke memory operations. Output signals can be processed with well known bi-direOional bus circuits 435R; such as 74LS620, 74LS621, 74LS622, and 74LS623 octal bus transceivers; to time share the pins for input and output signals. Various pinout configurations will now be discussed with reference to Fig 4M. These pinout configurations are intended to illustrate the general concepts of generating deteOor signals for a stored program computer, or for an IC chip, or for other applications and are not intended to be limited to the specific implementation shown in Fig 4M. In a first pinout configuration, deteOor signal lines 435K to OR gates 435C, 435E, and 435G (signal lines 435S to gate 435G, signal lines 435T to gate 435E, and signal lines 435U to gate 435C) can be output on pinouts from the IC chip without being processed with OR gates 435C, 435E, and 435G. This can involve a relatively large number of pinouts; such as 5, 10, 20, or more pinouts. In a second pinout configuration, deteOor signal lines 435K discussed for the first pinout configuration above, can be grouped into related signal groups, such as to reduce the number of pinouts; each related signal group being input into a different OR gate; such as OR gates 435C, 435 E, and 435G; and the output signals 435] (including output signals 434B, 434C, and 434D) from OR gates 435C, 435E, and 435G can be output on pinouts from the IC chip. The group of deteαor signals 435S into OR gate 435G may represent the conditions having the longest time available or other such charaOeristic, the group of deteOor signals 435T into Or gate 435E may represent the conditions having a shorter
time available or other such charaOeristic, and the group of deteOor signals 435 U into Or gate 435C may represent the conditions having the shortest time available or other such charaOeristic. Hence, a designer can use external logic to seleO the proper one of deteαor signals 435J to provide the time available needed to implement memory operations in response to deteOor signals 435J. In a third pinout configuration, deteOor signal lines 435J (including signal lines 434B, 434C, and 434D) discussed for the first and second pinout configurations above, can be input to related AND gates 435D, 435F, and 435H respeOively for selecting one of the plurality of detector signals 435] from OR gates 435C, 435E, and 435G for outputting from the IC chip. The deteOor signals 435M; including deteOor signals 435V, 435W, and 435X; output from AND gates 435D, 435F, and 435H respeαively are shown being ORed together with OR gate 4351 and the output signal 435P from OR gate 4351 is shown being output from the IC chip on a single pinout. The enabling signals 435L; including enable signals 434E, 434F, and 434G; used to seleO one of the AND gates 435D, 435F, and 435H respeOively are shown generated by configuration register 435 A; which can be implemented with well known registers, such as a 74LS174 register; used for storing configuration signals for configuring the IC chip. Configuration register 435A may be used to establish a configuration of the device. For example, configuration register 435A can be loaded by the processor, such as a stored program computer under program control during startup or initialization operations. Configuration signals 435N from configuration register 435A are shown being decoded by decoder 435B; which can be implemented with wel- known decoders, such as a 74LS138 decoder; to generate seleOion signals 435L to seleO the proper configuration of output signals on pinout 435P. In a forth pinout configuration, deteOor signal lines 435J discussed for the first and second pinout configurations above, can be input to the next OR gate having a shorter time available. For example, deteOor signal 434D output from the OR gate 435G having the longest time available deteαor signals can be input to the OR gate 435E having the next shortest time available deteOor signals. Similarly, the deteOor signal 434C output from the OR gate 435E having the next-longest time available deteαor signals can be input to the OR gate 435C having next shorte*. time available deteαor signals. Hence, each deteOor signal 435J generated by OR gates 435C, 435E, and 435G can be generated in response to the deteOor signals 435K having related time available conditions and can also be generated in response to the deteαor signals 435K having longer time available conditions.
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In another configuration, feedback signal 435Q can be used to feedback information, such as memory operations completed or memory operations in process, to control operation of the IC chip device.
EXPERIMENTAL SYSTEM ARCHITECTURE General Description An experimental system is configured with a host computer, a display processor, and memory, and a color monitor. The host computer is implemented with an SI 00 bus configuration using SI 00 compatible boards, such as Compupro boards; together with disk drives, printers, and other peripherals. The CRT monitor is a conventional color monitor having an analog RGB input, shown with monitor documentation included herewith. The display processor and memory arrangement is configured with a plurality of wire wrap boards. These boards include a logic board, BL1; 2-memory boards, BM1 and BM2; a rear-end board, BR1 ; and a buffer board, BB1. Operation of hardware and software in the experimental system discussed herein in conjunOion with a color monitor demonstrates operation of the system, meeting of system objeOives, and providing aαual reduαion to praOice. For example, information has been loaded into image memory and has been display processed and displayed to demonstrate operation.
Supervisory Processor Interface The interface between the supervisory processor and the display processor comprises input synchronization signals from the display processor to the supervisory processor to synchronize the supervisory processor with the display processor operations and output commands from the supervisory computer to initialize the display processor. Synchronization signals include a frame synchronization signal and a line synchronization signal. The frame synchronization signal occurs during vertical retrace and vertical blanking of the video signal. The line synchronization signal occurs during horizontal retrace and horizontal blanking of the video signal. An interlaced scan arrangement is used for the experimental system, although other scan arrangements can readily be accommodated. A field identification signal is provided that identifies whether the field is a first field or a second field of the interlaced scan. Communication between the supervisory processor and the display processor is performed with a 3-port parallel interface to a Compupro Interfacer-ll board under program control. Each port has 8-parallel input lines and 8-parallel output
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lines. The port assignments are listed in the COMPUTER PORT TABLE included herein. Output signals are defined as DO signals and input signals are defined as Dl signals. Port identification; A, B, or C; follows the DO or DI symbol. Signal line identification follows the port identification; i.e., DOA7 identifies output line-7 in port-A. Signal DOA5 controls loading in sequential and random access form. Sequential loading is seleOed when DOA5 is high and random access loading is seleOed when DOA5 is low. When DOA5 is high, an output strobe on DOA7 causes the pixel address registers to be updated with the related slope parameters on the falling edge of the strobe. This insures compatibility with the DOA7 strobe used as a write-bar signal to write the previous pixel information into the previously addressed pixel in image memory. Signal DOA6 controls loading and running operations. Running is seleOed when DOA6 is high and loading is seleOed when DOA6 is low. In general, DOA6 is high during displaying of images and DOA6 is low during loading of images into memory. Signal DOA7 strobes the information output with Port-B and Port-C into the destinations. DOA7 is normally low, and DOA7 is pulsed high and then pulsed low under program control to form an output strobe. Signal DIAO inputs the frame sync pulse from the CRT monitor interface. This frame sync pulse is the blanking pulse that blanks the CRT monitor during the vertical retrace period and during a predetermined number of lines prior to and subsequent to the vertical retrace period. This frame sync pulse occurs once per field, twice per frame, in the interlaced scan system as implemented with the demonstration system. The rising edge of the frame sync pulse, deteαed under program control, initiates loading of the parameters for a new field from the supervisory processor into the display processor. Signal DIA2 inputs the line sync signal from the CRT monitor interface, which is implemented for hardware control but not software control in the experimental system. Signal DIA4 inputs the frame identification signal from the CRT monitor interface. DIA4 is high during the field-1 period and low during the field-2 period. Signals DOBO through DOB7 output the information to be loaded into the destination identified with Port-C. This information can be delta information to be loaded into the delta registers, pixel address information to be loaded into the pixel address registers, and pixel data to be loaded into image memory. Signals DOCO through DOC7 output the address of the destination to be
loaded with the Port-B output signals. The various destinations are listed in the TABLE OF DESTINATION SELECT ASSIGNMENTS included herein; including the 4-delta registers each having an MSH and an LSH, 2-address registers each having an MSH and an LSH, data to be written into image memory, and weights to be written into a weight table memory.
Image Loading Loading of an image into memory is performed by loading the XP and YP- address registers with the address of each pixel to be loaded, then outputting the pixel information to be loaded with Port-B, and then strobing the pixel information into image memory with the DOA7 signal. A sequential load feature is provided under control of the DOA5 signal. When the D0A5 signal is high, a veOor can be loaded; where the previously loaded pixel address is incremented with the related delta parameter to obtain the next pixel address to reduce software overhead and thereby speedup loading of image memory. Loading of image memory with the supervisory processor is performed with a 3-port output arrangement having 8-bits per port. The first port, Port-A, communicates control signals between the supervisory processor and the display processor. The second port, Port-B, communicates address and data information to be loaded into the display processor between the supervisory processor and the display processor. The third port, Port-C, selects the register or memory in the display processor for loading. The protocol involves outputting of the destination address on Port-C, outputting of information to be loaded into the display processor on Port-B, and then outputting of a data strobe on Port-A. The data strobe loads the output information into the seleαed destination. A program to load veαors into memory is provided herein as the BASIC PROGRAM LISTING LD.ASC and is briefly discussed in the seαion entitled Software herein.
Software Programs have been developed to operate the experimental system and are included herein in the tables BASIC PROGRAM LISTINGS. These programs are source programs, that are compiled with a Basic compiler and linked with a Basic linker to obtain compiled Basic programs. Compiled Basic programs run significantly faster that interpretive Basic programs, which maintains real time synchronization between the display processor and the supervisory processor. The source listings may be readily compiled and linked by one skilled in the art to provide the compiled Basic programs executed to perform the image loading
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and image processing operations. The programs are programmed to be menu driven, prompting the operator to seleα various operator-seleOable options. The Basic listings included herein have extensive annotation to teach one skilled in the art the features implemented therein. The BASIC PROGRAM LISTING LD.ASC provided herein teaches loading of veOors into memory. The BASIC PROGRAM LISTING GRAPH.ASC provided herein teaches refreshing of a CRT monitor from memory. These listings are clearly coded and amply annotated to teach one skilled in the are how to operate the experimental system disclosed herein under program control.
Circuit Boards The experimental system is implemented with wire wrap circuit boards consisting of 2-Memory Boards (BM1 and BM2), 1 -Logic Board (BL1), 1 -Buffer Board (BB1), and 1-Rear End Board (BR1). Each board is construOed with a VeOor board, manufaOured by Veαor EleOronic Company of Sylmar CA, having 1/1 Oth inch hole spacings on a 17-inch by 8 1/2-inch board. Wire wrap DIP sockets and cable conneOors are inserted into the VeOor board and interconneαed with wire wrap interconneαions. Information on the DIPs plugged-in to the DIP sockets is provided for seleOed boards in the printout of the TABLE OF DIP LAYOUT ON BOARDS included herewith. Information on the cable conneOors is provided for each cable in the printout of the CABLE CONNECTION TABLE included herewith. DIP assignments are provided for seleOed boards in the TABLE OF DIP LAYOUT ON BOARDS included herewith, for each board. DIPs are arranged on the boards as rows identified with alphabetical symbols; i.eT, A to E; and as columns identified with numerical symbols; i.e., 1 to 23. Each DIP position on a board is identified with a U symbol followed by the column and row symbols (i.e., U3A). Logical schematic diagrams showing implementation of the experimental system are provided herewith, such as shown in Fig 6. These logical diagrams show standard commercially available integrated circuits; such as TTL series 7400 ICs, Mitsubishi M58725 RAMs, and 8216 bi-direOional bus drivers, and Signetics 8T97 buffers. Specifications for these integrated circuits are available in catalogs and specification sheets from the abovementioned manufaOurers and are well known in the art. The schematic diagrams show the logical funαion in symbolic form, identify the type of IC, identify the DIP numbers and pin numbers, and show wiring interconneαions between DIP and pin numbers. Device types are often
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shortened, such as shortening the name 74LS02 to LS02. DIP assignments are identified with U numbers, such as U20C representing the DIP at row-20 column-C on the subjeα circuit board. For example, a NOR-gate is shown at the top portion of Fig 6B identified with the designation LS02 as being a 74LS02 quad NOR-gate integrated circuit, identified with the designation U21C as being located on the BL1 circuit board at row-C column-21, and having 2-input signals on pin-T 1 and pin-12 of the DIP and one output signal on pin-13 of the DIP. The input to pin-11 is shown conneαed to the output of DIP U22B pin-3, the input to pin-12 is shown conneαed to the output of DIP U20B pin-12, and the output from pin-13 is shown conneαed to DIP U7D pin-9. For convenience of documentation, interconneαions may be designated by the DIP identification number and pin number separated by a dash; i.e., U21C-13 representing pin-13 of DIP U21C. For convenience of discussion, logical circuits may be designated by the DIP identification number and the output pin number separated by a dash; i.e., U21C-13 representing pin-13 of DIP U21C.
Cable List A cable list is provided in the CABLE CONNECTION TABLE included herewith. This cable list identifies the cables between the various VeOor boards and between the VeOor boards and the supervisory processor. Each cable between display processor boards is implemented with a 50-pin ribbon cable having odd pins conneαed to ground for signal isolation. Each cable between the VeOor boards and the supervisory processor is implemented with an RS-232 type 25-pin ribbon cable, consistent with the signal representations for the Compupro Interfacer-ll board. The cable list identifies the pin associated with a signal, a symbol associated with the signal, a description of the signal, a representative source of the signal and a representative destination of the signal.
S-100 Bus System The experimental system has been implemented with an S-100 bus based system performing supervisory processor funαions in conjunαion with the novel software and hardware, as discussed herein. Two S-100 bus based systems have been configured, the Camille system and the Murphy system. The configuration of the Camille system will be discussed in detail hereinafter. The Camille system comprises a computer, a pair of floppy disk drives, a terminal, and printers as discussed below. The floppy disk drives are implemented with a pair of 8-inch disk drives in an enclosure and operating in conjunOion with a DMA controller in the computer.
The disk drives are manufaOured by Siemens as the FDD 100-8; the drive enclosure is manufaOured by International Instrumentation, Incorporated; and the DMA Controller is manufaOured by CompuPro as the Disk 1 DMA Controller; all described in detail in the referenced manuals. The terminal is manufaOured by Applied Digital Data Systems, Inc. (ADDS) as the Model Viewpoint 3A Plus; described in detail in the referenced manual. The printers include a dot matrix printer manufaOured by Star Micronics, Inc. as the Gemini-10, a dot matrix printer manufaOured by Epson as the FX-100, and a daisywheel printer manufaOured by Smith-Corona as the TP-I; all described in detail in the referenced manuals. The computer is implemented with a cabinet manufaOured by Fulcrum Computer Products as the 18080 Microcomputer System Cabinet and having a backplane S-100 board manufaOured by CPA which is described in detail in the referenced CPA manual. The computer is implemented with various S-100 boards manufaOured by CompuPro including the 8085-8088 CPU board, RAM 16 and RAM 17 memory boards, a System Support board, and a pair of Interfacer 2 boards. One Interfacer 2 board is used to interface to the terminal and printers. The other Interfacer 2 board provides the 3-channel parallel interface to the control logic. These boards are described in detail in the referenced manuals. The joysticks are implemented with the Computer Compatible Joystick; described in the referenced applications notes. The operating system is CP/M 80, which is described in detail in the referenced documents. The applications program runs under Basic, which is described in detail in the referenced documents. The following documents provide supplemental data on the computer system and are herein incorporated by reference. 1. Technical Manual, Siemens, OEM Floppy Disk Drive FDD 100-8, Technical Manual, Model 100-80. 2. Manual, International Instrumentation, Incorporated, Universal Disk Enclosures, General Information/Pricing, 1982. 3. User Manual, CompuPro Division of Godbout EleOronics, Disk 1 Arbitrated 24 Bit DMA Floppy Disk Controller, 1981. 4. User's Manual, Applied Digital Data Systems, Inc., Viewpoint/3A Plus, 518-31100. 5. Operation Manual, Star Micronics, Inc., Gemini-10. 6. Operation Manual, Epson, FX Printer, 1983.
7. Operator's Manual, Smith-Corona, TP-I. 8. FunOional Description, CP-A, Revision 1. 9. Technical Manual, CompuPro Division of Godbout EleOronics, 8085/8088 CPU Dual CPU, 2/83. 10. Technical Manual, CompuPro Division of Godbout EleOronics, RAM 16 Static Memory, 4/82. 1 1. Technical Manual, CompuPro Division of Godbout EleOronics, RAM 17 64K Static Memory, 9/82. 12. User's Manual, CompuPro Division of Godbout EleOronics, System Support 1, 8/81. 13. Technical Manual, CompuPro Division of Godbout EleOronics, Interfacer 2, 4/82. 14. The CP/M Handbook with MP/M, by Rodnay Zaks, published by Sybex, 1980. 15. CP/M Primer, by Stephen Murtha and Mitchell Waite, published by Howard W. Sams & Co., Inc., 1980. 16. An IntroduOion to CP/M Features and Facilities, published by Digital Research, January 1978. 17. Microsoft Basic Reference Book, published by Microsoft, 1979. 18. Microsoft Basic Compiler Documentation, published by Microsoft. 19. The Basic Handbook (2nd Edition), by David Lien, published by Compusoft Publishing, 1981. 20. Microsoft Basic (2nd Edition), by Ken Knecht, published by Dilithium Press, 1983. 21. Basic Basic (2nd Edition), by James Coan, published by Hayden Book Company, Inc., 1978. 22. Computer Compatible Joystick InstruOion, applicable to: Apple-ll.
Logic Board Control Logic Various control arrangements can be provided for controlling operation. For example; counter, ROM, and logical control arrangements of synchronous or asynchronous design can be used. A gated clock arrangement has been implemented for control, which is illustrative of other forms of gated clock control logic and other non-gated clock control logic implementations. This gated clock control arrangement will now be discussed with references to Figs 6B to 6D. The gated clock control logic shown in Figs 6B to 6D controls the clock
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pulses to various logic devices; such as address generators, memories, and other devices; to clock the various operations associated therewith. For example, the write strobe W-bar to the memories is generated with U22C-11 and clocks to various registers are gated with circuits U21C, U20C, U19C, U19D, U18C, U9A, and U10A (Fig 6B). Several different types of clocks are generated at different times and are controlled to be non-conflioing with other clocks. Load clocks are generated under computer control to load computer generated parameters into various registers. Address generator clocks can be generated under control of external sync pulses. High speed clocks can be generated under control of various signals to generate addresses that are not in contention with other signals generating clocks and are not generated at times that such addresses are not needed. The logic composed of U18D-6, U22B-3, U21 E-6, U19B, U20B, and U21 D-6 (Fig 6B) is controlled by the computer for generating strobe signals and control signals for loading computer information into the address generators and for disabling operations during loading of computer information. Logic gates U20C and U21C (Fig 6B) gate the computer strobe to load delta registers. Logic gates U19C, U19D, and U18C (Fig 6B) gate various clock signals to load and update R-registers. Logic gates U9A and U10A (Fig 6B) gate various clock signals to load and update P-registers. Flip-flops U22E and associated logic U20D-4, U22A-4, U18D-8, U21E-4, U15A-3, U22C-3, U20D-13, U18D-2, U21 E-10, U18E-6, U20D-1, U21 E-12, U19D-4, U18E-3, U21D-8, U20E-6, U17A-8, U17A- 11, U22A-2, U13A-8, U21 E-2, U20E-3, and other related elements (Fig 6D) synchronize and process the sync signals CFS and CLS to generate clock and control signals for processor operation. Logic gates and flip-flops U12A, U21D- 8, U18E-3, U14A-2, U14A-4, U16A-3, U17A-3, U16A-6, U17A-6, U13A-6, U23C-10, U14A-6, U20E-11, U21 B-5, U15A-11, U21 B-2, U21 E-8, and related gates (Fig 6Q control the gated clock pulses for address generation operations. The computer interface signals are defined in the tables of computer interface signals; PORT-A, PORT-B, AND PORT-C. Port-A input and output signals are control signals. Port-B output signals are address and data signals to load into the seleαed destination. Port-C output signals are destination seleO signals. Computer load logic will now be discussed with reference to Fig 6B. Computer control signals DOA6 and DOA7 control loading of initial conditions. When DOA6 is 1-set, run operation is commanded and loading of initial conditions from the computer with the load strobe DOA7 is disabled with gate U22B-3. When DOA6 is 0-set, run operation is disabled and load operation is enabled through inverter U18D-6 by enabling gate U22B-3 to pass an inverted
computer strobe DOA7 as signal U22B-3. This gated strobe is used to clock the seleOed register, steered with the register address decoders U19B and U20B to gates U21C, U20C, U19C, and U19D. The inverted DOA6 signal U18D-6 is inverted with U21 E-6 to generate the DIEN-bar signal for memory read and write operations. When DOA6 is high, defining the run mode; DIEN-bar is high establishing the memory read mode. When DOA6 is low, defining the load mode; DIEN-bar is low establishing the memory write mode. DIEN-bar control operations are discussed in detail with reference to Figs 6E to 6N for the memory '~gic. Write signals U22C-6 and U22C-8 control writing into a peripheral RAM by enabling write pulses W2 and W3 when addressed through U19B-10 and U19B- 9 respeOively. Gate U22C-11 is an OR-gate that is enabled with the address of the memory U19B-11 to load data into the memory for steering of the computer strobe U22B-3 to generate a write strobe to load the computer generated parameter into memory. Gates U20C and U21C are NOR-gates that are enabled with the destination register address signals from U19B and U20B to seleα the delta register to be loaded by steering of the computer strobe U22B-3 to clock the appropriate delta register to load the computer generated parameter into the seleOed register. A master clock, shown as CPE-bar (Fig 6D), is fanned-out, gated, and applied to the synchronous elements. The CPE-bar clock is derived from a clock pulse generator and communicated to the logic board on cable C4-6. Alternately, clock CPE-bar can be generated with a self-contained clock generating operating asynchronously with reference to the external clock to permit optimization of clock periods for system operation. For example, the external clock may be constrained to a clock frequency consistent with the requirements of a sync generator for the CRT monitor, which may not be an optimum clock frequency for the address generators. Therefore, a separate clock can be provided having a clock frequency that is optimum for the address generators in place of the external clock. Clock logic will now be discussed with reference to Fig 6D. The clock CPE- bar is logically processed to clock synchronous elements in the address generators at the same time. For convenience of definition, clocking occurs at the rising edge of the delayed clock pulse CPD, which is delayed by 2-gate propagation delays after the early clock CPE-bar and one inversion of the early clock CPE-bar. For example, CPE-bar propagates through inverter U21 E-2 and non-inverting AND-gate U20E-3 to provide one inversion and 2-delays to
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generate delayed clock CPD prior to being used to synchronously ςjoqk. segistef U22E. Similarly, clock CPE-bar is delayed by gating logic U12A-8 and U12A-6 (Fig 6Q, providing one stage of delay and one stage of inversion, and by non- inverting gates U9A-6, U9A-8, U10A-6, and U10A-8 (Fig 6B) to provide the 2- propagation delays and the single inversion from the early clock CPE-bar to the clock signals for registers U8D, U9D, U5D, U8E, U5E, and U9E. In one display configuration, register U22E is used to synchronize operation of the logic with a frame sync signal CFS and a line sync signal CLS. A short synchronous pulse is generated in conjunOion with the line sync signal CLS. CFS is synchronously clocked into flip-flop U22E-10 and CLS is synchronously clocked into flip-flop U22E-12 to latch these signals as CFSR1 and CLSRl respeOively synchronous with the address generator clock. Latched line sync signal CLSRl is then latched in flip-flop U22E-15 one clock period later for a delayed line sync signal CLSR2. The delayed line sync signal CLSR2 U22E-15 is inverted with inverter U21 E-10 and NANDed with the non-delayed line sync signal CLSRl with NAND-gate U18E-6 to generate a short inverted pulse bracketing the first clock period of line sync signal CFSR1. Clock signal CPE-bar (Fig 6D) is gated with NAND-gates UI 2A-8 and U12A-6 (Fig 6Q to generate a gated clock signal for address generation; which is performed with registers U8D, U9D, U5D, U8E, U9E, and U5E. Gating of the clocks to these registers with AND-gates U9A-6, U9A-8, U10A-6, and U10A-8 gates address generator operations. Control logic for a display configuration will now be discussed with reference to Fig 6D. Signal U13A-8 is a clock gate control signal for gating the address generator clock, as described herein with reference to Fig 6C. This gate signal is comprised of three components; U17A-8, U17A-1 1 , and U22A-4. These components cause the clock to be generated at the appropriate time in conjunαion with the display sync signals. Gate U20D-4 ORs together the field sync and frame sync signals to enable the address generator clock through U22A-4 and U13A-8 when neither a frame sync signal CFSRl nor a line sync signal CLSRl is present. Gate U20E-6 ANDs together the inverted frame sync signal CFSR1 through inverter U18D-8 and the line sync signal. Gate U17A-8 NANDs together U20E-6 and the delayed line sync signal CLSR4 to enable the address generator clock through U13A-8. Gate UI 7A-1 1 NANDs together U20E- 6 and the undelayed inverted line sync signal CLSR1 through inverter U22A-2 to enable the address generator clock through UI 3A-8. The ELS signal U15A-3 controls multiplexers U10D, U1 1 D, U12D, U10E, U11 E, and U12E (Fig 6D). During the appropriate portions of the load mode,
U
the address generator P-registers are loaded from the address generator R- registers under control of the ELS signal. During other periods of time, the address generator P-registers are updated from the related delta registers under control of the ELS signal. The ELS signal is disabled by the sequential load control signal DOA5 inverted with U21 E-4. This permits the P-registers to be updated from the delta registers to generate veOors into memory, such as for a display configuration. The ELS signal is strobed with a short pulse U19D-4 during the load mode DOA6 as controlled with U22C-3. During the load mode, the ELS signal is enabled with DOA6 enabling U22C-3 to pass the short pulse U22C-2. The short pulse is generated by the early line sync signal CLSRl U22E- 12 and the thrice delayed line sync signal CLSR4 U22E-7 for a 3-clock period transfer pulse to transfer information from the R-registers to the P-registers. The 3-period pulse U19D-4 is generated when CLSR4 U22E-7 is low and when CLSRl U22E-10 is high, as inverted with U21 E-12 to define the period that the undelayed line sync signal CLSRl has gone high and before the delayed line sync signal CLSR4 has gone high; indicative of the first 3-clock periods at the start of a line sync pulse. The XA3 and XA3-bar signals are shown gated with U19A-1 to disable both the XA3-bar signal and hence memory board-1 and the XA3 signal and hence memory board-2 with gates UI 9C-13 and UI 9C-4 respeαively. This provides for blanking of the display and clearing of the buffer memory by outputting zeros from the disabled memory board when either the frame sync signal CFSRl or the sequential load signal DOA5 are true. U19C-1 disables the memory boards during sequential loading with DOA5 U19A-3 and during the vertical blanking period with the inverted CFSRl signal from inverter U18D-8. Registers U22E and U23C are used to latch signals. U23C-2 and U23C-5 latch signals C2-30 and C2-32 to provide latched signals C4-32 and C4-36 respeαively. U23C-10 is used in the clock gating logic, as discussed with reference to Fig 6C. U22E-10 and U22E-12 latch signals CFS and CLS respeOively. U22E-15, U22E-2, and U22E-7 provide 1-clock delay, 2-clock delays, and 3-clock delays respeαively for the CLSRl signal. Gated clock operations will now be discussed with reference to Fig 6C. Gated clock signals U12A-8 and U12A-6 each gate early clock CPE-bar with DOA6 from U21 E-6 so that address generation will only be performed when the run/load-bar signal DOA6 is high, indicative of run operations. Gated clock signals U12A-8 and U12A-6 also gate early clock CPE-bar with U13A-8, which is composed of 3-gating conditions; U17A-8, U17A-1 1, and U22A-4; discussed in greater detail with reference to Fig 6D. Gated clock signal U12A-8 also gates
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early clock CPE with U14A-6, which enables high clock rate memory scanout operations within a block. Gated clock signal U12A-6 also gates early clock CPE- bar with U21 B-2, which enables low clock rate memory block re-addressing operations. Consequently, when memory operations are proceeding within a block of 64-pixels, the address generator clock is generated as shorter period clock signal U12A-8 and, when memory operations are making a transition between blocks and need additional clock time for re-addressing, the address generator clock is generated as longer period clock signal UI 2A-6. Determination of whether memory scanout or re-addressing is being performed for the particular clock period is determined by deteαing an overflow of an address generator, as indicative of re-addressing, or deteOing of a non- overflow of all address generators, as indicative of scanout. Overflow for this condition is defined as an overflow for a positive delta condition and an underflow for a negative delta condition. Therefore, deteOion of a carry condition for a positive delta or deteOion of a non-carry condition for a negative delta represents an overflow condition for gating a clock. An overflow condition on either the X-address generator or the Y- address generator causes a re- addressing condition. As shown in Fig 6C, a re-addressing condition is deteOed with NAND-gate U13A-6 from any one or combination of the 4-conditions U16A-3, U17A-3, U16A-6, and U17A-6. U16A-3 compares the inverted overflow bit C1-bar U15E-9 of the Y-address generator with the non-inverted sign bit SN1 U14E-6 of the Y-delta register to deteα a Y-negative overflow condition. UI 7A-3 compares the overflow bit Cl U15E-9 of the Y-address generator with the inverted sign bit SN1 U14E-6 of the Y-delta register to deteO a Y-positive overflow condition. U16A-6 compares the inverted overflow bit C2-bar U15D-9 of the X-address generator with the non-inverted sign bit SN2 U14D-6 of the X-delta register to deteα an X-negative overflow condition. UI 7A-6 compares the overflow bit C2 U15D-9 of the X-address generator with the inverted sign bit SN2 U14D-6 of the X-delta register to deteO a X-positive overflow condition. An overflow signal U13A-6 is latched and delayed with flip-flop D23G-10 for enabling of the scanout clock U12A-8 for scanout, in the absence of an overflow condition. Flip-flop U23C-10 provides a one-clock period delay so that an extended re- addressing clock period occurs in the clock period following the overflow condition, which is the clock period during which the re-addressing is performed. Latched overflow signal U23C-10 is inverted with inverter U14A to form a non-overflow signal U14A-6 and used to enable the scanout clock U12A-8. Latched overflow signal U23C-10 is also processed with flip-flops U21 B-5
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and U21 B-2 to provide a triple clock period for an overflow. These flip-flops are clocked with the non-gated delayed clock pulse CPD U20E-3 to control non- gated clock period time delays. If clocked with the gated clock pulse, such as with UI 5A-8; then the gating clock logic could cause the clock signal to lock-up. A triple clock period for re-addressing will now be discussed with reference to Fig 6C. DeteOion of an overflow condition U23C-10 with gate U20E-1 1 sets flip-flop U21 B-5 on the first clock period and sets flip-flop U21 B-2 on the second clock period, which adds 2-clock periods to the basic single clock period; yielding a triple clock period to facilitate re-addressing. At the completion of the third clock period, the 1-set signal U21 B-2 enables a single clock signal U12A-6 and is inverted to a 0-set signal U21 E-8 to reset U21 B-5 through U20E-1 1 and to reset U21 B-2 through UI 5A-1 1 on the next clock to clock flip-flops U21 B-5 and U21 B-2, respeOively. This triple clock period logic is designed to operate for a single overflow condition surrounded by non-overflow conditions, or for two overflow conditions immediately following each other, and for many overflow conditions immediately following each other. For a single overflow condition; scanout clock U12A-8 has a series of single period clocks and has 3-clock periods missing that are coincident with overflow conditions and re-addressing clock U12A-6 has a single clock coincident with the overflow condition. For multiple sequential overflow conditions; scanout clock U12A-8 has a series of single period clocks with a series of triple clock periods missing that are coincident with the multiple sequential overflow conditions and re-addressing clock U12A-6 has multiple sequential clocks each separated by 2-clock periods. The scanout clock UI 2A-8 and the re-addressing clock UI 2A-6 are generated separately for gating purposes. They are ORed together with gate U21 D-8 for loading the buffer memory with signal C3-22 and for clocking register U23C-9. This causes the pipeline from the memory output through the buffer memory to be clocked by an out-of-phase signal, yielding a 1.5 clock period propagation delay time for the memory. The design is carefully configured so that the pipeline propagation delay is greater than the 0.5 clock periods and less than the 1.5 clock periods to facilitate proper clocking of the memory output signal into the buffer memory with a propagation delay that can approach the 1.5 clock period. The clock signals to the address generation registers are implemented as the logical-OR of a plurality of different clock signals. In order to equalize clock delays so that each clock is twice delayed, including the once inverted CPE-bar signal with U12A-8 and U12A-6, the two address generator clocks U12A-8 and U12A-6 are separately ORed together with each of the address generator clock
gates U9A-6, U9A-8, U10A-6, and U10A-8 (Fig 6B) rather than using the pre- ORed clock signal U21 D-8 in order to reduce clock skew. Clock gating logic will now be discussed in greater detail with reference to Fig 6B. Address decoders U20B and U19B decode the destination address DOCO to DOC7 to generate a decoded address signal at the outputs of U19B and U20B to seleα the gated clock channel. This steers the computer load strobe U22B-3 to the addressed register to load that register. The address assignments are set forth in the table entitled DESTINATION SELECT ASSIGNMENTS. The most significant 16-address block is decoded using block decode logic U21 D-6 to enable decoders U19B and U20B when the 4-MSBs DOC4, DOC5, DOC6, and DOC7 are all 1-set. The block enable signal U21 D- 6 enables U19B and U20B with the El-bar inputs. The most significant address signal DOC3 enables U20B when low, indicated by the E2-bar input, and enables U19B when high, indicated by the E3 input. Consequently, U20B generates the LSH addresses and U19B generates the MSH addresses. One of the 8-addresses for the seleαed half is seleαed with the 3-least significant address bits DOCO, DOC1, and DOC2 which go to each address decoder U19B and U20B. The address decoder that has been seleαed with the DOC3 to DOC7 address signals has one of 8-address output lines low, as determined by the DOCO to DOC2 least significant address bits. The low output line enables the register clock gating logic to steer the clock to the addressed register. The clock is the negative going strobe U22B-3 generated under computer control. EffeOively, the decoded address signals steer the computer strobe to the appropriate register clock input to clock the computer output data word into that register. ~~" Control logic for a display configuration will now be discussed with reference to Fig 6D. Signal U20D-1 is a single pulse clock signal occurring at the leading edge of the line sync signal except when a frame sync pulse or a computer load signal is generated. This clock pulse is generated by U18E-6, as previously described. Disabling of this clock pulse during the frame sync pulse and the computer load period is performed by Oring together the computer load signal DOA6-bar U20D-12 and the synchronized frame sync signal CFSRl U20D-11. When either the computer load signal DOA6-bar or the computer frame sync signal CFSRl are high, NOR gate U20D-13 and inverter U18D-2 apply a high signal to U20D-2, which causes U20D-1 to be low independent of the line sync clock pulse. Only when the computer load signal is in the run state (DOA6-bar is low) and the frame sync signal CSFR1 is low can the line sync clock U20D-1 go high to generate a clock pulse.
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The line sync clock U20D-1 is generated from the line sync signal CLS. The CLS signal is latched in flip-flop U22E-12 to generate a resynchronized line sync signal CLSRl . The resynchronized line sync signal CLSR1 is delayed one clock period by latching in flip-flop U22E-15 to generate a delayed resynchronized line sync signal CLSR2. NAND-gate U18E-6 generates a one clock period negative pulse when the resynchronized line sync signal CLSR1 U22E-12 is high and when the delayed resynchronized line sync signal CLSR2 U22E-15 is still low, indicative of the first clock period of the, resynchronized line sync signal. Inverter U21 E-10 inverts the delayed line sync signal CLSR2 U22E-15 for NANDing with the non-delayed line sync signal CFSRl U22E-12 for generation of the one clock period signal U18E-6. Therefore, U20D-1 is a one clock period positive pulse that occurs at the leading edge of each line sync pulse that is disabled by the computer being in the load mode or that is disabled by the frame sync signal. This clock U20D-1 is used to clock the R-registers for updating with the delta parameter at the positive edge and to transfer the updated number in the R-registers to the R-registers at the negative edge. The computer strobe DOA7 is generated under software control. It is a short positive pulse, typically about 3-microseconds in width. It is NANDed with the computer run signal DOA6 using inverter U18D-6 and NAND-gate U22B-3 to generate a short negative pulse when enabled by the DOA6 run/load-bar signal being low, as indicative of a load command. The negative pulse U22B-3 is used to clock the register that is addressed with the computer destination address signal with decoders U19B and U20B to load data from the computer into that seleOed register. Address generator clock gating logic will now be discussed with reference to Fig 6B. This logic is composed of gates U19C, U19D, U18C, U8A, U9A, and U1 OA. This logic comprises 4-channels of clock logic for the address generation registers, where the clock gating logic for each channel is similar to the clock gating logic for the other 3-channels. R-register gating logic will now be discussed with reference to Fig 6B. Gate U19C-1 steers the load strobe U22B-3 to clock the register with the computer generated strobe to load the computer generated parameter into the related register. Steering signal U19C-3 steers the computer pulse UI 9C-2 to the input of gate U18C-1. Gate U18C-3 combines the two mutually exclusive clock signals, the computer strobe and the line sync strobe to clock the XR-register CXRM with signal U18C-3 for the computer strobe and on the rising edge of the line sync pulse. Gate U19C-10 steers the load strobe U22B-3 to clock the register with the
s
computer generated strobe to load the computer generated parameter into the related register. Steering signal UI 9C-9 steers the computer pulse UI 9C-8 to the input of gate UI 8C-9. Gate UI 8C-8 combines the two mutually exclusive clock signals, the computer strobe and the line sync strobe to clock the XR-register CXRL with signal U18C-8 for the computer strobe and on the rising edge of the line sync pulse. Gate U19D-1 steers the load strobe U22B-3 to clock the register with the computer generated strobe to load the computer generated parameter into the related register. Steering signal U19D-3 steers the computer pulse U19D-2 to the input of gate U18C-4 Gate U18C-6 combines the two mutually exclusive clock signals, the computer strobe and the line sync strobe to clock the YR- register CYRM with signal U18C-6 for the computer strobe and on the rising edge of the line sync pulse. Gate U19D-13 steers the load strobe U22B-3 to clock the register with the computer generated strobe to load the computer generated parameter into the related register. Steering signal U19D-12 steers the computer pulse U19D-11 to the input of gate U18C-12. Gate U18C-11 combines the two mutually exclusive clock signals, the computer strobe and the line sync strobe to clock the YR-register CYRL with signal U18C-11 for the computer strobe and on the rising edge of the line sync pulse. P-register clock logic will now be discussed with reference to Fig 6B. The XP-register clock signal U9A-6 to XP-register CXPM is generated from the inverted XR-register clock signal CXRM U8A-2, the gated write signal U18E-11, the re-addressing clock U12A-8, and the scanout clock U12A-6. The inverted R- register clock signal U8A-2 causes the XP-register CXRM to be clocked with the computer strobe and with the trailing edge of the line sync signal, the inverted clock signal from U18C-3. The gated write signal U18E-11 clocks the XP- registers for each write strobe U22C-11 that loads a parameter into memory in order to advance the address generators to the next address. The gated re- addressing clock signal U12A-6 and the gated scanout signal U12A-8 have been discussed above with reference to Fig 6C. The XP-register clock signal U9A-8 to XP-register CXPL is generated from the inverted XR-register clock signal CXRL U8A-4, the gated write signal U18E-11, the re-addressing clock U12A-8, and the scanout clock U12A-6. The inverted R- register clock signal U8A-4 causes the XP-register CXRL to be clocked with the computer strobe and with the trailing edge of the line sync signal, the inverted clock signal from U18C-8. The gated write signal U18E-11 clocks the XP- registers for each write strobe U22C-11 that loads a parameter into memory in
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order to advance the address generators to the next address. The gated re- addressing clock signal U12A-6 and the gated scanout signal U12A-8 have been discussed above with reference to Fig 6C. The YP-register clock signal U10A-6 to YP-register CYPM is generated from the inverted YR-register clock signal CYRM U8A-6, the gated write signal U18E- 1 1, the re-addressing clock U12A-8, and the scanout clock U12A-6. The inverted YR-register clock signal U8A-6 causes the YP-register CYRM to be clocked with the computer strobe and with the trailing edge of the line sync signal, the inverted clock signal from U18C-6. The gated write signal U18E-1 1 clocks the YP-registers for each write strobe U22C-1 1 that loads a parameter into memory in order to advance the address generators to the next address. The gated re-addressing clock signal U12A-6 and the gated scanout signal U12A-8 have been discussed above with reference to Fig 6C. The YP-register clock signal U10A-8 to YP-register CYPL is generated from the inverted YR-register clock signal CYRL U8A-8, the gated write signal U18E-11, the re-addressing clock U12A-8, and the scanout clock U12A-6. The inverted YR-register clock signal U8A-8 causes the YP-register CYRL to be clocked with the computer strobe and with the trailing edge of the line sync signal, the inverted clock signal from U18C-11. The gated write signal U18E-11 clocks the YP-registers for each write strobe U22C-1 1 that loads a parameter into memory in order to advance the address generators to the next address. The gated re- addressing clock signal U12A-6 and the gated scanout signal U12A-8 have been discussed above with reference to Fig 6C. Gates U22C-1 1 , U18D-12, and U18E-1 1 provide a write strobe to clock the address registers to advance the address in the address registers in accordance with the delta parameters loaded in the delta registers. This write clock clocking of the address registers is used for writing a sequence of words into memory without the need to reload the address registers, where the address registers are incremented with the write strobe to advance the address from the initially loaded address in accordance with the delta parameters. This write strobe is gated with the DOA5 signal with gate U18E-1 1 to enable advancing the address generators during the load mode and to disable advancing the address generators during the run mode.
Address Generators Two address generator configurations are shown in Figs 60 to 6R. The address generators shown in Figs 60 to 6R provide for overflow deteOion to gate a clock in accordance with the arrangement shown in Fig 6C. The address
generators shown in Figs 60 to 6R do not provide for such overflow deteαion. In this configuration, overflow deteOion is enhanced by arranging the adder logic so that the overflow from an adder chip coincides with the desired position of overflow deteOion. In order to provide this feature, an extra adder chip is used in the address generators of Figs 60 and 6P. The address generators shown in Figs 6Q and 6R do not have such overflow deteOion and consequently can be implemented with one less adder chip. The XP-address generator will now be discussed with reference to Fig 60. Register U8D, U9D, and U5D store the address parameter. Register U17D and U7D store the delta parameter for updating the address parameter. Adders U13D to U16D and U6D add the delta parameter to the address parameter to obtain an updated address parameter. Multiplexers U10D to U12D provide for loading initial conditions into the address register during the load mode and provide for updating the address parameter in the address register in response to the delta parameter in the delta register in the run mode. The delta parameter initial condition is loaded into the delta register from the computer output port. The 6-LSBs from the computer output byte are applied to the D-inputs of delta register U17D and U7D. The CXPS clock provides a clock pulse at the appropriate time, as described with reference to Fig 6B, to clock the initial conditions into the delta registers. The address parameter initial condition is loaded into the address register from the computer output port. The 6-LSBs from the computer output byte are applied to the D-inputs of address register U8D, U9D, and U5D. The CXPM and CXPL clocks provide clock pulses at the appropriate times, as described with reference to Fig 6B, to clock the initial conditions into the address register. In the run mode, the address register is clocked with the CXPM and CXPL clocks to update the address parameter in response to the delta parameter. The output of the address register; the Q-outputs of the U8D, U9D, and U5D register; are applied to the A-inputs of adder circuits U13D to U16D and U6D. The output of the delta register; the Q-outputs of the U17D and U7D register; are applied to the B-inputs of adder circuits U13D to U16D and U6D. The output of the adder circuits on the summation lines is the binary sum of the A- inputs from the address register and the B-inputs from the delta register, providing an updated address parameter that is input to the address register through the multiplexers to the D-inputs of the address register. Consequently, each time the address register is clocked, the updated address is loaded into the address register and the updated address that is loaded into the address register is output on the Q-lines from the address register to again be added to the delta
SUBSTITUTE SHEET
parameter with the adders to provide the next updated address to the address register. The multiplexers U10D, U1 1 D, and U12D multiplex the updated address parameter from the adders into the address register to load the initial conditions into the address register at the beginning of the load mode and to load the updated address parameter from the adders thereafter. The ELS signal from U15A-3, as described with reference to Fig 6D, controls the multiplexer to load initial conditions at the start of a line sync pulse and to enable updating of the address parameter with the delta parameter thereafter. The adders are conneαed with the carry output from the preceding stage conneαed to the carry input of the next subsequent stage for a rapid carry propagating through the adder. The adders are arranged so that the overflow from U15D-9 coincides with the point that divides the scanout bits and the re- addressing bits, where the scanout bits are the three less significant bits and the re-addressing bits are the six more significant bits. The next most significant bit XA3 for the XP address generator is used as the board control bit instead of a re- addressing bit for the XP-address generator. The overflow signal U15D-9 is input to U16A-5 and UI 7A-5 (Fig 6Q for controlling gating of the clock. The YP-address generator will now be discussed with reference to Fig 6P. Register U8E, U9E, and U5E store the address parameter. Register U17E and U7E store the delta parameter for updating the address parameter. Adders U13E to UI 6E and U6E add the delta parameter to the address parameter to obtain an updated address parameter. Multiplexers U10E to U12E provide for loading initial conditions into the address register during the load mode and provide for updating the address parameter in the address register in response to the delta parameter in the delta register in the run mode. The delta parameter initial condition is loaded into the delta register from the computer output port. The 6-LSBs from the computer output byte are applied to the D-inputs of delta register U17E and U7E. The CYPS clock provides a clock pulse at the appropriate time, as described with reference to Fig 6B, to clock the initial conditions into the delta registers. The address parameter initial condition is loaded into the address register from the computer output port. The 6-LSBs from the computer output byte are applied to the D-inputs of address register U8E, U9E, and U5E. The CYPM and CYPL clocks provide clock pulses at the appropriate times, as described with reference to Fig 6B, to clock the initial conditions into the address register. In the run mode, the address register is clocked with the CYPM and CYPL clocks to update the address parameter in response to the delta parameter. The
output of the address register; the Q-outputs of the U8E, U9E, and U5E register; are applied to the A-inputs of adder circuits U13E to U16E and U6E. The output of the delta register; the Q-outputs of the UI 7E and U7E register; are applied to the B-inputs of adder circuits U13E to U16E and U6E. The output of the adder circuits on the summation lines is the binary sum of the A-inputs from the address register and the B-inputs from the delta register, providing an updated address parameter that is input to the address register through the multiplexers to the D-inputs of the address register. Consequently, each time the address register is clocked, the updated address is loaded into the address register and the updated address that is loaded into the address register is output on the Q- lines from the address register to again be added to the delta parameter with the adders to provide the next updated address to the address register. The multiplexers U10E, U1 1 E, and U12E multiplex the updated address parameter from the adders into the address register to load the initial conditions into the address register at the beginning of the load mode and to load the updated address parameter from the adders thereafter. The ELS signal from U15A-3, as described with reference to Fig 6D, controls the multiplexer to load initial conditions at the start of a line sync pulse and to enable updating of the address parameter with the delta parameter thereafter. The adders are conneαed with the carry output from the preceding stage conneαed to the carry input of the next subsequent stage for a rapid carry propagating through the adder. The adders are arranged so that the overflow from U15E-9 coincides with the point that divides the scanout bits and the re- addressing bits, where the scanout bits are the three less significant bits and the re-addressing bits are the six more significant bits. The overflow signal UI 5E-9 is input to UI 6A-2 and UI 7A-2 (Fig 6Q for controlling gating of the clock. The XR-address generator will now be discussed with reference to Fig 6Q. Register U8B, U9B, and U5B store the address parameter. Register U17B and U7B store the delta parameter for updating the address parameter. Adders U13B to UI 5B and U6B add the delta parameter to the address parameter to obtain an updated address parameter. Multiplexers U10B to U12B provide for loading initial conditions into the address register during the load mode and provide for updating the address parameter in the address register in response to the delta parameter in the delta register in the run mode. The delta parameter initial condition is loaded into the delta register from the computer output port. The 6-LSBs from the computer output byte are applied to the D-inputs of delta register UI 7B and U7B. The CXRS clock provides a dock pulse at the appropriate time, as described with reference to Fig 6B, to clock the
initial conditions into the delta registers. The address parameter initial condition is loaded into the address register from the computer output port. The 6-LSBs from the computer output byte are applied to the D-inputs of address register U8B, U9B, and U5B. The CXRM and CXRL clocks provide clock pulses at the appropriate times, as described with reference to Fig 6B, to clock the initial conditions into the address register. In the run mode, the address register is clocked with the CXRM and CXRL clocks to update the address parameter in response to the delta parameter. The output of the address register; the Q-outputs of the U8B, U9B, and U5B register; are applied to the A-inputs of adder circuits U13B to U15B and U6B. The output of the delta register; the Q-outputs of the U17B and U7B register; are applied to the B-inputs of adder circuits U13B to U15B and U6B. The output of the adder circuits on the summation lines is the binary sum of the A-inputs from the address register and the B-inputs from the delta register, providing an updated address parameter that is input to the address register through the multiplexers to the D-inputs of the address register. Consequently, each time the address register is clocked, the updated address is loaded into the address register and the updated address that is loaded into the address register is output on the Q-lines from the address register to again be added to the delta parameter with the adders to provide the next updated address to the address register. The multiplexers U10B, U1 1 B, and U12B multiplex the updated address parameter from the adders into the address register to load the initial conditions into the address register during the load mode and to load the updated address parameter from the adders during the run mode. The DOA6-bar signal from U18D-6, as described with reference to Fig 6B, controls the multiplexer to load initial conditions in the load mode and to enable updating of the address parameter with the delta parameter in the run mode. The adders are conneαed with the carry output from the preceding stage conneαed to the carry input of the next subsequent stage for a rapid carry propagating through the adder. The YR-address generator will now be discussed with reference to Fig 6R. Register U8C, U9C, and U5C store the address parameter. Register U17C and U7C store the delta parameter for updating the address parameter. Adders U13C to UI 5C and U6C add the delta parameter to the address parameter to obtain an updated address parameter. Multiplexers U10C to U12C provide for loading initial conditions into the address register during the load mode and provide for updating the address parameter in the address register in response to the delta parameter in the delta register in the run mode.
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The delta parameter initial condition is loaded into the delta register from the computer output port. The 6-LSBs from the computer output byte are applied to the D-inputs of delta register UI 7C and U7C. The CYRS clock provides a clock pulse at the appropriate time, as described with reference to Fig 6B, to clock the initial conditions into the delta registers. The address parameter initial condition is loaded into the address register from the computer output port. The 6-LSBs from the computer output byte are applied to the D-inputs of address register U8C, U9C, and U5C. The CYRM and CYRL clocks provide clock pulses at the appropriate times, as described with reference to Fig 6B, to clock the initial conditions into the address register. In the run mode, the address register is clocked with the CYRM and CYRL clocks to update the address parameter in response to the delta parameter. The output of the address register; the Q-outputs of the U8C, U9C, and U5C register; are applied to the A-inputs of adder circuits U13C to U15C and U6C. The output of the delta register; the Q-outputs of the U17C and U7C register; are applied to the B-inputs of adder circuits UI 3C to UI 5C and U6C. The output of the adder circuits on the summation lines is the binary sum of the A-inputs from the address register and the B-inputs from the delta register, providing an updated address parameter that is input to the address register through the multiplexers to the D-inputs of the address register. Consequently, each time the address register is clocked, the updated address is loaded into the address register and the updated address that is loaded into the address register is output on the Q-lines from the address register to again be added to the delta parameter with the adders to provide the next updated address to the address register. The multiplexers U10C, U11C, and U12C multiplex the updated address parameter from the adders into the address register to load the initial conditions into the address register during the load mode and to load the updated address parameter from the adders during the run mode. The DOA6-bar signal from U18D-6, as described with reference to Fig 6B, controls the multiplexer to load initial conditions in the load mode and to enable updating of the address parameter with the delta parameter in the run mode. The adders are conneOed with the carry output from the preceding stage conneOed to the carry input of the next subsequent stage for a rapid carry propagating through the adder. Output of the address signals will now be discussed with reference to Figs 60 and 6P. The Q-outputs of the XP-address register and YP-address register are routed to the memory for accessing and for loading of information. The address conneαions between the memory and the address generators are listed in the
S BS
CABLE CONNECTION TABLE here under the heading CABLE-I BM1,2/BL1 (Cl). The Y-address bits YO to Y8 and the X-address bits XO to X8, including the complemented and uncomplemented X3 memory board address seleO bit, are listed therein together with source circuits on the control logic board and destination circuits on the memory boards. In the run mode, the XP-address register and YP-address register are continually docked with the gated clock, as discussed with reference to Fig 6B; resulting in the address parameters being continually updated with the delta parameters and resulting in the memory being continually addressed by the updated address parameters. The XA3 and XA3-bar memory board seleα signals are gated with UI 9A-1 in order to blank the CRT monitor and clear the buffer, as discussed with reference to Fig 6D herein.
Memory Boards A detailed design of one configuration of the memory of the present invention is shown in Figs 6E to 6N. The architeOure of one of the memory boards is shown in block diagram form in Fig 6E, is shown in detailed block diagram form in Figs 6F to 6J, and is shown in detailed logical diagram form in Figs 6K to 6N. Commonality of symbols and features in these diagrams provide for cross referencing to different levels of detail between these diagrams. This memory uses Mitsubishi M58725P RAMs having 16,384 (16K) bits per RAM, organized in a 2,048 (2K) words by 8-bits per word configuration. Logical diagrams of RAM chips are shown in Figs 6K to 6N. Each RAM chip comprises 11 -address lines AO to A10, 8-data lines DQ1 to DQ8, a chip seleα line S-bar, an output enable line OE-bar, and a write pulse line W-bar. The address lines address 1-word out of 2K-words stored in the memory chip. The data lines output the addressed word in the read mode and input a word for storage in the write mode. The data lines are tristate lines that, when in the read mode, output the addressed information when enabled with the chip seleα line S-bar and, when in the write mode, store the data in the addressed location. The output enable signal G-bar controls inputting and outputting of data from the RAM. When disabled with the chip seleα line or the output enable line, the data lines are in the floating tristate condition. The memory control logic is comprised of circuits U19A to U19E, as shown in Fig 6F. Buffers U19A and U19D are non-inverting buffers that buffer the address signals for fanout to the RAMs. In this configuration, 11 -address signals YA3B to YA8B and XA4B to XA8B are fanned out to the address inputs AO to Al 0 of the RAMs. Decoders U19B, U19C, and U19E decode the scanout portion
T
of the address word for control of the tristate data lines of the RAMs. Decoder UI 9B decodes the Y-scanout portion YAO to YA2 of the scanout portion of the Y- address. Decoders U19C and U19E decode the X-scanout portion XAO to XA2 of the X-scanout portion of the address. Decoder U19C is enabled for read operations and decoder U19E is enabled for write operations. Each of decoders; U19B, U19C, and U19E; receive 3-input scanout address lines and generate 8- decoded scanout controf lines in response to the decoding. Decoded signals MYO-bar to MY7-bar from U19B generate Y-controI signals to seleα one column of 8-RAMs with the chip seleα pin S-bar. Decoded signals MXOR-bar to MX7R- bar from U19C generate X-control signals in the read mode to seleα one row of 8-RAMs with the output enable pin G-bar. Decoded signals MXOW-bar to MX7W-bar from UI 9E generate X-cσntrol signals in the write mode to seieα one row of 8-RAMs with the output enable pin G-bar. Therefore, seleαion of a column of 8-RAMs with the Y-scanout signals and seleαion of a row of 8-RAMs with the X-scanout signals selects a single RAM common to both the seleαed row and the seleαed column for read and write operations. The decoders have gating signals E1-bar, E2-bar, and E3. Signals El-bar and E2-bar are permanently enabled on decoders U19B and U19C with a ground conneOion and signal E3 is permanently enabled on decoder U19E with a puilup conneOion. Signal E3 on decoder U19B is used to place the RAMs on the non-seleOed memory board in the standby mode for reduced power consumption. This is achieved by disabling U19B on the non-seleαed board and enabling U19B on the seleαed board with the XA3 and XA3-bar signals, which seleO the board to be utilized. Disabling U19B on the non-seleOed board disables the Y-scanout signals to the chip seleO pin S-bar, which in turn places the non-seleαed RAMs into the standby mode for reduced power consumption. The XA3 and XA3-bar gating of the U19B decoder is not necessary for memory operation, but is used for reduαion of power consumption. Pin E3 on decoder U19C and pin E2-bar on decoder U19E are controlled with the DIEN-bar signal which is derived from the computer run/load mode signal for enabling decoder UI 9C in the run mode to read from memory, to disable decoder UI 9E in the run mode to prevent writing into memory, to enable decoder UI 9E in the load mode to write into memory and to disable decoder U19C in the load mode to read from memory. When decoder UI 9E is enabled in the load mode, the write pulse W-bar controls decoder UI 9E; where decoder U19E effeαively steers the W-bar write pulse to the one of eight decoded signal lines MXOW-bar to MX7W-bar under control of the XAO, XA1 , and XA2 scanout address signals. A discussion will now be provided relative to Figs 6G to 6N to illustrate the
logical design of the memory. Figs 6G to 6K each show 16-RAMs organized in 2-logical columns and construαed on one row on a memory board, where each memory board has 4-groups of 16-RAMs each shown in one of Figs 6G to 6J. The manner in which these 4-pairs of logical columns conneα together is shown in Fig 6E and is shown by the interconneαions between Figs 6G to 6J and Figs 6K to 6N and by the discussions hereinafter. All RAMs are addressed by the same 1 1 -address lines; shown as the address bus to the A-input of each RAM in Figs 6G to .6J and shown in greater detail as the address bus to the AO to A10 inputs of RAMs U8 and U16 for each pair of logical columns in Figs 6K to 6N. The addresses are placed on the address bus by U19A and U19D (Fig 6F) and are routed to all 16-RAMs on each of the RAM groups (Figs 6G to 6J) to excite the RAM address inputs A (Figs 6G to 6J) and AO to A10 (Figs 6K to 6N). Each logical column of RAMs is seleOed by a single one of the eight Y- scanout signals from U19B (Fig 6F), shown conneOed to the S-bar pin of each RAM in the logical column in Figs 6G to 6J and shown in greater detail to the S- bar inputs of RAMs U8 and U16 for each pair of logical columns in Figs 6K to 6N. Each logical row of RAMs is seleOed by a single one of the eight X-scanout signals; MXOR to MX7R in the read mode to the output enable pin G-bar and MXOW to MX7W in the write mode to the W-bar from U19C and U19E respeOively (Fig 6F). Each of these signals are shown conneOed to the pair of RAM in the logical row for each pair of logical columns in Figs 6G to 6J and shown in greater detail for RAMs U8 and UI 6 for each pair of logical columns in Figs 6K to 6N. Each of these X-scanout signals enable the same pair of RAMs in each of the 4-pairs of logical columns (Figs 6G to 6J and Figs 6K to 6N). All RAMs in the pair of columns shown in each of Figs 6G to 6J abd Figs 6K to 6N have the corresponding data bus pins colleOed together; shown as the data bus to the D-input of each RAM in Figs 6G to 6J and shown in greater detail as the data bus to the DO to D7 pins of RAMs U8 and U16 for each pair of logical columns in Figs 6K to 6N. The data bus and control signals are conneαed to a pair of Intel 8216 bus interface chips for each pair of logical columns, as shown in simplified form in Figs 6G to 6J and in detailed form in Figs 6K to 6N. The operation of the data bus interface is discussed in greater detail hereinafter. In view of the above, all RAMs are addressed with the same address signals and one RAM that is at the interseOion of the enabled X-row scanout signal and the enabled Y-column scanout signal alone is permitted to place the addressed word on the data bus in the read mode and alone is written into at the addressed
location from the data bus. In the read mode, one RAM is enabled to output the addressed word onto the system data bus. This can be implemented by busing together the corresponding 8-data lines from each RAM. However, busing together a large number of RAM data lines, such as 128-RAM data lines in this configuration, can result in reduced RAM speed, such as due to bus and chip capacitance. Therefore, Intel 8216 bi-direOional bus drivers are provided to isolate groups of RAMs from the system data bus and from other groups of RAMs. The system data bus interface will now be described with reference to Figs 6K to 6N. Fig 6K shows the data bus interface for row-A on each of the two memory boards. Fig 6L shows the data bus interface for row-B on each of the two memory boards. Fig 6M shows the data bus interface for row-C on each of the two memory boards. Fig 6N shows the data bus interface for row-D on each of the two memory boards. For this configuration, 16-RAMs are bused together through each system data bus interface circuit, comprising two Intel 8216 components. The bi-direOional signals DBO, DB1, DB2, and DB3 are conneOed to the RAM data bus and the uni-direαional signals DIO and DOO, DI1 and DOl, DI2 and D02, and DI3 and D03 are conneαed to the uni-direαional system bus for reading from RAM through the DOO to D03 unidireαional outputs and for writing into RAM on the DIO to DI3 unidireαional inputs. A pair of Intel 8216 4-bit bus drivers are used to control the 8-data bus lines for the RAM data bus. The Intel 8216s are controlled with the board seleα signal XA3 or XA3-bar and the scanout address seleα signals for the 2-columns of RAMs associated with the Intel 8216 circuits. The board seleα signal, XA3-bar for memory board-1 and XA3 for memory board-2, control all of the Intel 8216s on the board. Therefore, the Intel 8216s on the enabled board are partially enabled to conneα the RAM data buses on that board to the system bus and the Intel 8216 on the disabled board are fully disabled to disconneα the RAM databuses on that board from the system bus. Similarly, the column seleO signals for the 2-columns of RAMs conneαed to the particular Intel 8216s are controlled with the column seleα signals so that the column seleα signal enabling a column of RAMs will also partially enabled the Intel 8216s associated with that column to conneα the seleOed column data bus to the system data bus. Because 2-columns of RAMs are conneOed to each Intel 8216 circuit, the related column seleα signals are ORed together with a NAND gate; where the column seleα signals are in complement logic form and consequently a NAND gate can perform an OR funαion; and are then ANDed with the board seleα signal XA3 or XA3-bar in a
second NAND gate in non-complement logic form to generate the control signal in complement logic form as needed for the Intel 8216 chip seleα. The Intel 8216 circuits are steered with the DIEN-bar control, which is-cσnnected fcrthe DIEN signal generated with U21 E-6 (Fig 6B). Therefore, in the run mode; the DIEN signal controls the Intel 8216s to conneα the RAM data bus through the DOO to D03 buffers to output the RAM signals onto the system output data bus and, in the load mode; the DIEN signal controls the Intel 8216s to conneα the RAM data bus through the DIO to DI3 buffers to input the write signals from the system data bus to the RAMs. Row A on the board has 2-logical columns of RAMs (Figs 6G and 6K), comprising the first column with RAMs U1A to U8A and the second column with RAMs U9A to U16A. As shown in greater detail with reference to Figs 6K to 6N; the first column is seleOed with the MYO-bar column seleα scanout signal and the second column is seleOed with the MYI-bar column seleO signal. The 2-column seleα signals are ORed together with U18E-3 and are ANDed with the board seleO signal with U18E-6 to enable U17A and U18A. Row B on the board has 2-logical columns of RAMs (Figs 6H and 6L), comprising the third column with RAMs U1 B to U8B and the fourth column with RAMs U9B to UI 6B. As shown in greater detail with reference to Figs 6K to 6N; the third column is seleαed with the MY2-bar column seleα scanout signal and the fourth column is seleOed with the MY3-bar column seleO signal. The 2- column seleO signals are ORed together with U18E-8 and are ANDed with the board seleα signal with U18E-1 1 to enable U17B and U18B. Row C on the board has 2-logical columns of RAMs (Figs 61 and 6M), comprising the fifth column with RAMs U1 C to U8C and the sixth column with RAMs U9C to U16C. As shown in greater detail with reference to Figs 6K to 6N; the fifth column is seleαed with the MY4-bar column seleα scanout signal and the sixth column is seleOed with the MY5-bar column seleo signal. The 2- column seleα signals are ORed together with U17E-3 and are ANDed with the board seleα signal with U17E-6 to enable U17C and U18C. Row D on the board has 2-logical columns of RAMs (Figs 6J and 6N), comprising the seventh column with RAMs U1 D to U8D and the eighth column with RAMs U9D to U16D. As shown in greater detail with reference to Figs 6K to 6N; the seventh column is seleOed with the MY6-bar column seleα scanout signal and the eighth column is seleαed with the MY7-bar column seleα signal. The 2-column seleO signals are ORed together with U17E-8 and are ANDed with the board seleα signal with U17E-1 1 to enable U17D and U18D.
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Buffer Board The buffer board is implemented with a buffer to buffer the outputs of memory and to apply these outputs to the rear-end board (Fig 6A). The buffer can be implemented with various forms of buffer memories, such as double buffers and FIFOs. Alternately, the buffer can be eliminated and the memory output can be routed direOly to the rear-end board. The CABLE CONNECTION TABLE provided herein illustrates on arrangement for conneOing the buffer board inbetween the memory and logic boards and the rear-end board. The buffer board receives memory information and a gated clock from the memory and logic boards to clock the memory information into the buffer and receives a rear-end board clock to clock the buffered information into the rear-end board, as generally discussed with reference to Fig 6A. Alternately, the memory and logic boards can provide the unbuffered information direOly to the rear-end board without an intervening buffer board for clocking the memory information into the DACs on the rear-end board with the gated clock from the logic board.
Rear-End Board The rear-end board interfaces the system to a CRT monitor and provides synchronization and clock signals for the CRT monitor and for the rest of the system. The rear-end board also performs auxiliary funoions, such as converting analog joystick signals to digital form for control of a display processor. The rear-end board is shown in Figs 6S to 6V in detailed schematic diagram form. A clock pulse generator 630A is implemented with a pair of inverters, an 18.432-MHz (herein referred to as 18-MHz for convenience) crystal, resistors, and capacitors as shown in Fig 6T to generate a square wave signal from inverter 630B pin-12. A counter circuit (74LS163N) is clocked from the inverted 18- MHz signal to pin-2 through inverter 74LS04 pin 2 for counting down the 18- MHz signal to about a 9-MHz clock signal for the display processor output from pin-14 and about a 2-MHz clock signal to the sync generator circuit MM5321 from pin-12. A group of 4-switches with pull-up resistors are conneOed to the preload inputs of the counter on pins 3 to 6 to preload a seleαed amount for implementing count periods other than binary numbers. A synchronization signal generator is implemented with a National SemiconduOor MM5321 component. The MM5321 is conneαed in a usual fashion, such as described in the specification sheets and shown in Fig 6T. Switches D.C., V.R., and H.R. seleO MM5321 modes of operation. The MM5321 horizontal drive signal is output from pin-15 and is used to
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blank the digital to analog converters (DACs) and is output through an 8T98-9 inverter H-DRIVE for generating the horizontal sync signal or line sync signal CLS to the digital logic boards. The horizontal drive signal is also output to flip- flop U1-9, which is used to experiment with horizontal blanking HB signals. The MM5321 vertical drive signal is output from pin-1 1 and is used to generate vertical blanking signals through an 8T97-5 to vertical blanking flip- flops U2, generating vertical blanking signal VB which is used to blank the video DACs. The vertical blanking signal VB U2-9 is buffered with 8T97-1 1 through cable C4-2 to apply the vertical blanking signal to the digital logic as the CFS signal. The MM5321 composite sync signal is output from pin-16 and is used as the composite sync signal to the CRT monitor, buffered with an 8T97-3 and an 8T98-3 for complement signals. The MM5321 blanking clock signal is output from pin-14 and is used to clock the vertical blanking flip-flops U2 and the horizontal blanking flip-flops U1-9 HB through an inverter 8T98-7. The MM5321 interlace control signal is output from pin-9 and is used to control flip-flop U1-5 FLD-bar to generate the field-1-bar signal on cable C4-12 to the control logic board. Joystick input circuits are shown in Figs 6U and 6V. Fig 6U provides the control circuits for the joystick analog to digital converters (ADCs) and Fig 6V shows the ADCs. These ADCs are input to the computer through the control logic board to provide operator control of display processing. The joysticks utilized in this configuration are Apple-2 Compatible Joysticks named Computer Compatible Joystick. They are analog joysticks having analog potentiometers for analog control. The joystick signals are input through plugs PJ1 and PJ2 at pin-6 and pin-7 for conneOion to the scaling amplifiers and ADCs shown in Fig 6V. The ADCs are controlled to start the conversion with the frame sync transition of the frame sync signal by shifting the frame sync signal through flip-flops U9A-5 and U9A-9 and deteOing the condition of U9A-5 being in the 0- state and U9A-9 being in the 1-state with AND-gate U12-3 to generate a 1-clock period start convert pulse to the ADCs. The ADCs will start the conversion in response to this start convert pulse and will latch up the converted digital number for input to the computer under program control. The two computer signals SELO and SEL1 are received from the computer through the control logic board to seleO one of four ADC numbers for input to the computer. These signals are inverted with U13-7 and U13-9. The inverted and non-inverted SELO and SEL1 signals are decoded with UI 1-3 for ADC 1-
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seleαion with signal SI, ADC-2 seleOion with signal S2, ADC-3 seleαion with signal S3, and ADC-4 seleOion with signal S4. Inverters U10 and U13 receive 8 signals from the ADCs, shown in Fig 6V, and buffers these 8-signals to drive the cable for input to the computer through the control logic board. Consequently, the computer under program control generates seleα signals SELO and SEL1 and reads the 8-bit number from the seleαed ADC. In one implementation, the computer under program control generates four sequential seleO signal codes on lines SELO and SEL1 to address the four ADCs in sequence and inputs the seleOed ADCs output number for processing under program control. The 4-ADCs and associated scaling amplifiers are shown in Fig 6V. The ADCs are implemented with the well known ADC0800 components, such as manufaOured by National SemiconduOor. The scaling amplifiers are implemented with the well known LF356 amplifiers. Each of the 4-joystick inputs from plugs PJ1 and PJ2 (Fig 6U) are shown conneαed to a different ADC channel through a scaling amplifier UI, U2, U5, and U6 (Fig 6V). The scaling amplifiers are conneOed in a conventional manner with resistor and capacitor networks to scale the joystick signals. Each scaling amplifier has its output on pin-6 conneOed to the input of its related ADC on pin-12. The ADCs convert the analog signal input at pin-12 in response to the start convert signal to pin-6 and latch the converted number in an internal register. The internal register is implemented with a tristate output controlled by the output enable signal to pin- 7. The corresponding output lines of each ADC are conneαed together to form an 8-bit bus DO to D7 which is routed to buffer amplifiers U10 and U13 (Fig 6U). Consequently, when one of the ADCs is tristate-enabled with one of the decoded seleO signals SI to S4 (Fig 6U) input to pin-7 of the ADCs (Fig 6V), the number converted by that ADC is applied to the 8-bit data bus for communication to the computer. One channel of video DAC is shown in Fig 6S. Each of the three channels are implemented with similar signals, except that the green channel having 3-bits is conneαed to data bits D5 to D7 and the red and blue channels having 2-bits are conneOed to data bits D6 and D7. These video DACs are high speed DACs for converting intensity signals from digital signal form, as generated by the display processor, to analog signal form for exciting a CRT monitor. Three video DACs are used to convert three video signals; the red video signal, the blue video signal, and the green video signal; to generate the RGB signals to the CRT monitor. The video DACs can be implemented with the TDC1016 DACs manufaOured by TRW. The conneαions for this DAC are shown in the VIDEO
DAC CONNECTION TABLE provided herein. The D9 and DIO data pins are conneOed to ground. The digital red and blue signals having 2-bits resolution are conneαed to the D7 and D8 data pins.The digital green signal having 3-bits resolution is conneOed to the D6 and D8 data pins. The other data pins are conneOed to ground. Buffer amplifiers are implemented with the well known LM359 buffer amplifier, where the buffer amplifier conneαions are shown in Fig 6S. The output of each buffer amplifier excites one of the red, green, or blue inputs to the CRT monitor.
Circuit Specifications The circuits used in the experimental system are generally commercially available circuits that are well known and that are described in widely distributed specification sheets and component catalogs. A list of these specification sheets and catalogs is provided hereinafter and the materials referenced therein are incorporated herein by reference. For example, the 74LS00, 74ALS00, and 74AS00 specifications are set forth in the referenced Texas Instruments and Motorola catalogs and the Intel 8216 bus interface and the Intel 2149 RAM specifications are set forth in the referenced Intel catalogs; which are herein incorporated by reference. 1. Texas Instruments, ALS/AS Logic Circuits Data Book, 1983. • 2. Texas Instruments, The TTL Data Book, Volume 3, 1984. 3. Texas Instruments, The TTL Pocket Data Book, 1983. 4. Intel, Component Data Catalog, 1981. 5. Intel, Memory Components Handbook, 1984. 6. Motorola, Schottky TTL Databook, 1981. Various circuits used in the experimental system are described in the following list of component specifications, which are herein incorporated by reference. 1. TRW, LSI D/A Converters, TDC1016J-8/9/10. 2. TRW, Monolithic Video D/A Converters; TDC1016J-8, TDC0106J-9, TDC1016J-10; 1979. 3. Texas Instruments, TMS-4016, 2048-Word By 8-Bit Static RAM. 4. National SemiconduOor, ADC0800 8-Bit A/D Converter. 5. National SemiconduOor, MM5321 TV Camera Sync Generator. 6. Signetics, Hex Buffers/Inverters; 8T95, 96, 97, 98. 7. Mitsubishi; M58725P,S;P-15,S-15; 16384-BIT (2048-word by 8-bit static RAM.
MEMORY EXPANDABILITY IπtroduOion The memory configurations disclosed herein can be readily expanded; such as in the bit direOion, the word direOion, and the memory direαion. For example; the bits per word can be varied from one bit, to four bits, to eight bits, to sixteen bits, and more bits per word; the words per memory can be varied from 16, to I K, to 256K, to 1 meg, to 8 meg, to 1 billion, and more words per memory; and the number of memories can be varied from one memory, to four memories, to 16 memories, and more memories per system. Various memory configurations are discussed herein illustrating memory expandability, either explicitly or implicitly. See the Fig 4H to 4K configurations disclosed herein. Memory expandability may be discussed in the context of a display system. However, such display system expandability is illustrative of multitudes of other applications for the memory technology disclosed herein. For example, in a display configuration, the memory can be expanded in pixel depth and in image area (pixel quantity). Expandability in pixel depth and in image area are disclosed separately infra. However, expandability in both, pixel depth and image area, can be achieved by combining these two disclosures. Similarly, in a computer main memory configuration, the memory can be expanded in word length and in word quantity. Expandability in word length and in word quantity are disclosed separately infra. However, expandability in both, word length and word quantity, can be achieved by combining these two disclosures. ~" Pixel Depth The eight bits per pixel disclosed for the Mitsubishi RAM configuration (Figs 6E to 6N) can be readily varied. The memory system shown in Fig 4F can be implemented with one megabit DRAMs for a display system having one-million pixels of one bit each. Paralleling eight of these DRAMs with common addressing and separate output bits will yield one-million pixels of eight bits each. Paralleling nine of these DRAMs with common addressing and separate output bits will yield one-million pixels of nine bits each. Paralleling sixteen of these DRAMs with common addressing and separate output bits will yield one-million pixels of sixteen bits each. The memory system shown in Fig 4F can be implemented with one megabit DRAMs for a display system having 250K-pixels of 4-bits each. Paralleling two
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of these DRAMs with common addressing and separate output bits will yield 250K-pixels of eight bits each. Paralleling three of these DRAMs with common addressing and separate output bits will yield 256K-pixels of twelve bits each. Paralleling four of these DRAMs with common addressing and separate output bits will yield 250K-pixels of sixteen bits each.
Image Area The 250K-pixels disclosed for the Mitsubishi RAM configuration (Figs 6E to 6N) can be readily varied. The memory system shown in Fig 4F can be implemented with one megabit DRAMs for a display system having one-million pixels of one bit each. Paralleling two of these DRAMs with different addressing (common address bits and chip seleOion with different chip seleα addresses) and bussed output bits will yield two-million pixels of one bit each. Paralleling eight of these DRAMs with different addressing (common address bits and chip seleOion with different chip seleα addresses) and bussed output bits will yield eight-million pixels of one bit each. The memory system shown in Fig 4F can be implemented with one megabit DRAMs for a display system having 250K-pixels of 4-bits each. Paralleling two of these DRAMs with different addressing (common address bits and chip seleOion with different chip seleO addresses) and bussed output bits will yield 500K-pixels of 4-bits each. Paralleling eight of these DRAMs with different addressing (common address bits and chip seleOion with different chip seleO addresses) and bussed output bits will yield two-million pixels of 4-bits each.
Bit Planes The pixel depth configuration disclosed above can be adapted to provide different bit planes, where a particular one or particular groups of bits in the pixels can be written into or read out of separate from other bits in the pixels. For example, one bit in each pixel can be used as an overlay bit plane that can be loaded independent of the other bits in the pixel and can be scanned-out together with the other bits in the pixel. An overlay bit plane in image memory can be rotated, compressed, translated, and perspeOive-processed with the image; such as for gridlines, map notations, and others. An overlay bit plane in refresh memory can be fixed in the viewport; not rotated, compressed, translated, and perspeOive-processed with the image; such as for reticles and others. The geometric processor is disclosed herein relative to writing an image into
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image memory on a line-by-line basis. This configuration can also be used to write graphic veoors into an overlay bit plane in image memory on a veOor-by- veαor basis. This can be implemented by direOly writing the veOors under control of a supervisory processor or indireαly by loading a veOor memory under control of a supervisory processor and then writing the veOors under control of the veOor memory.
Word Length In a computer main memory configuration, the eight bits per word disclosed for the Mitsubishi RAM configuration (Figs 6E to 6N) can be readily varied. The memory system shown in Fig 4G can be implemented for a computer main memory with one megabit DRAMs having one-million words of one bit each. Paralleling eight of these DRAMs with common addressing and separate output bits will yield one-million words of eight bits each. Paralleling nine of these DRAMs with common addressing and separate output bits will yield one- million words of nine bits each. Paralleling sixteen of these DRAMs with common addressing and separate output bits will yield one-million words of sixteen bits each. The memory system shown in Fig 4G can be implemented for a computer main memory with one megabit DRAMs having 250K-words of 4-bits each. Paralleling two of these DRAMs with common addressing and separate output bits will yield 250K-words of eight bits each. Paralleling three of these DRAMs with common addressing and separate output bits will yield 256K-words of twelve bits each. Paralleling four of these DRAMs with common addressing and separate output bits will yield 250K-words of sixteen bits each.
Word Quantity In a computer main memory configuration, the 250K-words disclosed for the Mitsubishi RAM configuration (Figs 6E to 6N) can be readily varied. The memory system shown in Fig 4G can be implemented for a computer main memory with one megabit DRAMs having one-million words of one bit each. Paralleling two of these DRAMs with different addressing (common address bits and chip seleαion with different chip seleO addresses) and bussed output bits will yield two-million words of one bit each. Paralleling eight of these DRAMs with different addressing (common address bits and chip seleOion with different chip seleO addresses) and bussed output bits will yield eight- million words of one bit each. The memory system shown in Fig 4G can be implemented for a computer
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main memory with one megabit DRAMs having 250K-wo/ds of 4-bits each. Paralleling two of these DRAMs with different addressing (common address bits and chip seleαion with different chip seleO addresses) and bussed output bits will yield 500K-words of 4-bits each. Paralleling eight of these DRAMs with different addressing (common address bits and chip seleOion with different chip seleO addresses) and bussed output bits will yield two-million words of 4-bits each.
MEMORY PIPELINE A memory pipeline configuration can provide a price and performance improvement. Propagation delays in the address signal generation (including address multiplexing) and in the output data signals reduces the clock rates for the memory. Pipelining of the memory, both address signals and output data signals, can be implemented by combinations of intermediate registers to limit propagation delays and multi-phase clocks to compensate for propagation delays. Both of the techniques are shown in the embodiment of a display system using Mitsubishi RAMs herein. Multi-phase clocking will now be discussed. Multi-phase clocking involves keeping track of both, maximum and minimum, propagation delays in order to seleO the correO clock phase and to insure that this phase boundaries will not be exceeded. A multi-phase clock can be generated by counting-down a high speed clock and by logically combining various counter signals. Reducing memory propagation delays; whether with high speed circuits, or parallel logic, or pipeline registers, or multi-phase clocking; can be important. For example, memory speed can be increased by using higher cost DRAMs, but this can have a significant effeO on system cost in systems that are memory intensive. Hence, reducing propagation delays outside of the DRAMs is important. However, gate array propagation delays may be low enough to render such DRAM outside delays to be small. Enhanced speed can be achieved with a pipeline register inbetween the address generator and the memory. This pipeline register temporarily stores the address so that the address generator can be updated. This permits concurrent propagation delay: 1) through the memory (such as DRAMs) with the old address stored in the pipeline register and 2) through the address generator logic (such as the adder chain). Hence; for this pipelined memory configuration, the memory cycle period is the
DRAM tpc signal (55ns in the '-10 DRAMs) or the address counter propagation delay, whichever is greater. It is valid to assume tk-tf-tk-a RAM tp ξ signal is greater, particularly with a gate array address generator having a carry lookahead that implements high speed address generation. Additional pipelining, pipelining in addition to the use of the above pipeline register, can be implemented to further increase speed. For example; if the tf A . j pipeline register parameter in the fast page mode DRAMs cannot be reduced, then a discrete logic pipeline register can be implemented with static column mode DRAMs to further reduce the cycle time. For one DRAM chip configuration, a 20ns t^ A| _ | '-10 period and an approximate 14ns t£ AH '-7 period can be reduced, such as to a 3ns discrete 74AS174 logic hold time, which can then be further pipelined with the output strobe.
MEMORY CONTROLLER IntroduOion A memory controller can be used to generate signals to control a memory; such as for DRAM addressing and refreshing operations. Various memory architeαures are disclosed herein, such as in Figs 4F to 4K, which can be used in combination with the various memory controller configurations disclosed herein; such as memory controller configuration-! and such as memory deteOor, delay, and refresh circuits disclosed herein. Alternately, the memory controller teachings disclosed herein may be used in combination with conventional memory architeαures and the memory architeαures disclosed herein may be used in combination with conventional controllers. Similarly, portions of the memory controllers disclosed herein may be used in combination with portions of conventional controllers and portions of the memory architeαures disclosed herein may be used in combination with portions of conventional memory architeαures. The memory waveforms disclosed herein are sufficient to teach one skilled in the art how to praαice the features of the present invention. For example, said Toshiba data book defines the charaOeristics of the Toshiba DRAMs with such waveforms to teach one skilled in the art how to construO a DRAM controller for memory operation. Hence, memory waveforms by themselves are sufficient disclosure. However, additional logical design disclosure is provided herein to further facilitate the praOice of the features of the present invention.
Memory Controller Considerations Memory controllers in accordance with the present invention may be
implemented in various ways. A memory controller in accordance with the present invention can be grouped, such as grouped on a single memory controller chip or on a plurality of memory controller chips, or distributed, such as fully or partially distributed onto the memory chips. A memory controller in accordance with the present invention can be implemented on a single memory controller chip or can be partitioned onto multiple memory controller chips. For simplicity of discussion, various grouped and distributed memory controller configurations and various single chip and multiple chip memory controller configurations are discussed herein. It is intended that the memory controller configurations discussed for signal chip implementation also be implementable in multiple chip form, that the memory controller configurations discussed for multiple chip implementation also be implementable in single chip form, that the memory controller configurations discussed for grouped implementation also be implementable in distributed form, and that the memory controller configurations discussed for distributed implementation also be implementable in grouped form. Further, memory chips may be discussed as DRAM chips for convenience, which DRAM chips are intended to be illustrative of other RAM chips and other memory chips. A custom memory controller chip or chip set can be used with standard processor chips and with standard DRAM chips. The custom memory controller can implement features of the present invention and remain compatible with standard processor and DRAM chips. Also, address deteOors may be implemented on the processor chip rather than on a separate memory controller chip. In the example shown in Fig 7B, multiple CAS scanout operations and a single RAS re-addressing operation are illustrated. In alternative examples, RAS re-addressing operations can occur adjacent to each other without being separated by CAS scanout operations. Hence, the deteOors can be designed to facilitate multiple re-addressings in sequence. For example, the overflow deteOor shown in Fig 6C facilitates multiple overflows in sequence. A multi-deteOor configuration can be implemented to have external scanout, internal scanout, and re-addressing; such as shown in Figs 4H, 41, 4J, 4K, and 4T. This can be implemented with two deteOors arranged for deteOing the three address conditions. The deteOors can be of the same type, such as two overflow deteOors or two comparitor deteOors, or the deteOors can be of different types, such as one overflow deteOor and one comparitor deteOor. The first deteOor can be implemented to invoke a shorter time delay and the second deteαor can be implemented to invoke a longer time delay. This may be charaOerized as a
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hierarchial speed arrangement or a hierarchial mode arrangement or a three dimensional configuration. Many other hierarchial and multi-dimensional arrangements can also be implemented. For example, the above two deteαor example can be implemented with three deteOors arranged for deteOing the three address conditions. The time delay implemented by the Fig 6C overflow deteαor can be reduced in time delay magnitude by deleting one of the two delay flip-flops U21 B and can be increased by adding delay flip-flops to supplement flip-flops U21 B. The time delay of the "wait states" can be controlled by the number of "wait states" that are invoked. Various strategies of time available, short and long magnitudes, modal, etc. can be implemented. Such deteOor and time delay modes can each be represented in tabular form, such as illustrated by the ADDRESS CORRESPONDENCE TABLES. Various versions thereof have previously been disclosed to illustrate internal scanout bit and external scanout bit partitioning. For example, one configuration can be implemented having the LSBs assigned to the external scanout addresses and another configuration can be implemented having the LSBs assigned to the internal scanout addresses, such as depending upon whether internal scanout or external scanout is faster. Scanout speed can be affeOed by various faOors, such as the speed of the scanout circuitry and whether the scanout circuitry is on-the-chip or off-the-chip. Deteαors and associated logic (such as chip enable and seleα circuits) can be implemented on a relatively small custom memory controller chip involving only a small amount of logic circuitry and only a few pins. The amount of circuitry for the comparitor, address MSB buffer register, etc. is small and can be implemented to supplement the circuitry on a conventional memory controller chip without significant additional complexity. A configuration having 1-meg DRAMs may have ten row address bits and hence ten row address pins for the chip block seleα and ten bits for the buffer register and comparitor. A configuration having 4-meg DRAMs may have two additional pins and bits. Expansion of memory with more banks of memory chips can increase external scanout. This configuration may not need an additional deteαor because the internal scanout and external scanout can be combined together. Hence, even when larger memory chips are used, only the quantity of row address bits per chip or a subset thereof need be deteαed. Hence, only a small amount of additional logic and pins are needed to implement the system of the current invention with an upgraded memory controller. A deteOor, such as a comparitor deteOor, may need row address bits for deteαion of a re-addressing condition. However, many address lines contain
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multiplexed row and column signals. For example, a DRAM chip in a CAS scanout mode in accordance with one configuration of the present invention receives CAS addresses but not RAS addresses from the address multiplexer (such as multiplexers 430D and 430E shown in Fig 4F). This condition can be accommodated with the implementation of a row address buffer (such as buffer 414A shown in Fig 4E) to store the prior row address until a new row address is available, as identified by a RAS signal. Hence, one configuration of a DRAM chip receiving multiplexed row and column addresses uses a row address buffer on the DRAM chip and one configuration of a memory controller receiving multiplexed row and column addresses uses a row address buffer on the memory controller chip. Alternately, one configuration of a DRAM chip or a memory controller chip receiving non-multiplexed row and column addresses does not need such a row address buffer to store the current RAS input. In such a multiplexed configuration, buffer 414A can be an on-the-chip row address register and comparitor 422 can be used to compare the next row address 421 B being loaded into buffer 414A and the prior row address 421 C stored by register 414A (Fig 4E). In this configuration, the same group of row address bits are tested for all memory banks and the dedicated non-shared deteOor lines for each memory bank generated by the deteOor need only be a single wire. Hence, this memory controller configuration may have 12 row address lines that are shared between all memory banks and only a single deteOor line output dedicated to each memory bank (such as another ten lines for a ten memory bank configuration). Improved pinout and interconneoion efficiency can be achieved in a configuration where the deteOor signals are mutually exclusive by encoding the output deteOor lines. For example, 16 deteαor lines related to 16 memory banks can be encoded into four encoded deteOor lines. Hence, a memory controller chip can be implemented to use encoded deteαor signals to steer the RAS and CAS signals. Also, a processor delay circuit can be shared by a plurality of deteOors (see for example Fig 4T) thereby reducing circuitry, pinouts, and interconneαions. Further, current memory controller chips may already have address signals available on the chip for conventional funOions. Hence, a conventional memory controller chip may be upgraded to an improved memory controller chip in accordance with the present invention without the need to add a large number of additional pinouts. Alternately, a custom memory controller chip in accordance with the present invention may be implemented with the same number of pinouts and circuitry or with a relatively small increase in pinouts and circuitry compared to a conventional memory controller chip.
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in one configuration of the present invention, memory expansion outside the DRAM chip uses external scanout. Hence, in this configuration, only the row address bits (not the external scanout address bits) to the DRAM chip need be deteOed even if the memory is very large. An important feature of this configuration of the present invention is that re-addressing can be separated from scanout and that memory chips can be seleOively re-addressed and seleOively scanned out without affeOing the other memory chips that are not re-addressed nor scanned out (Fig 41). For the example of a common delay circuit or a common delayed processor, re- addressing may invoke a delay that can affeα all of the memories or memory chips. However, once the various memory chips are re-addressed in the different ways, they can each be seleOively scanned out relatively independent of whether or not they were re-addressed and independent of when they were re-addressed. In a configuration where scanout between memory chips is seleOed with external scanout logic and scanout within a memory chip is seleOed with internal scanout logic, re-addressing can be implemented internal to a memory chip and can be seleOively applied to the memory chips while external scanout effeOively seleOs the memory chip or memory chips for outputting. A memory controller implemented in accordance with the present invention can generate encoded and steered RAS lines. Such a configuration can provide seleoive re-addressing, such as on a per chip basis for memory chips or such as on a per memory bank basis for memories. Hence, the previously discussed re- addressing on a per chip basis and on a memory bank basis can be implemented automatically. Alternately, a plurality of memory banks or a plurality of memory chips can be conneOed to the same steered RAS line so that the plurality of memory chips or memory banks on the same steered RAS line are all re- addressed together. For example, eight RAS lines from a memory controller need not be limited to eight memory banks or eight memory chips but can be used to implement eight groups of memory banks or eight groups of memory chips, where each group of memory banks or memory chips are re-addressed together. Then, external scanout can be implemented to seleα the individual memory banks or the individual memory chips from the group of memory banks or memory chips that are re-addressed together. Also, a memory controller can be implemented with a global re-addressing capability, such as to re-address all of the DRAM chips on all of the RAS lines. The individual re-addressing and the global re-addressing features are compatible and can be implemented in combination as alternate modes of operation in the same memory controller.
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The Fig 4T configuration shows RAS and CAS signals controlling RAS/CAS multiplexer 460K. These RAS and CASE signals can be steered RAS and CAS signals. Also, the RAS/CAS multiplexer can be replicated, such as a separate RAS/CAS multiplexer for each memory that is controlled by the steered RAS and CAS signal for that memory. In this configuration, the Fig 4T arrangement would be implemented with RAS/CAS multiplexers 460K 0 to 460K n assigned to memories 460RQ to 460R n respeOively. A group of partitioned memory bits, such as the seleO memory bits 460B, can be decoded, such as with a decoder like memory seleO decoder 460G, to generate decoded signals, such as decoded signals 4601, to steer the RAS and CAS signals for the corresponding RAS/CAS multiplexer 460Kg to 460K n (not shown). One configuration of seleOive re-addressing implements the memory controller logic to keep the prior address MSBs stored in a buffer register thereon and also implements the deteOor to deteα the address space for the particular group of address bits (such as shown in Fig 4T). The address space deteOor enables the appropriate one of the buffer registers to be used for comparison (Fig 4T) and enables the appropriate one of the RAS output strobes to be invoked (not shown). Also, configuration circuitry can be implemented to seleO the address space for each of the address space deteOors, either on a memory controller chip or on a memory chip or otherwise, and can be initialized to seleO the address space. For example, initialization can be programmable and down-loaded under program control to a configuration register. This facilitates use of the memory controller for many different architeαures and also facilitates memory optimization for different architeαures, such as to improve memory performance for different types of programs. For example, a program can be implemented to download address space configuration data in order to group DRAMs (such as DRAMs that are hardwired on separate channels) together in the same address space in the same channel. Alternately, a program can be implemented to download address space configuration data in order to separate DRAMs (such as DRAMs that are hardwired on the same channel) into different address spaces in different channels. Some of the configurations can be dedicated and non-programmable, such as for proteOion of the operating system. Hence, this configuration flexibility can be provided a relatively simple memory controller including (1) a different channel of space deteOor, (2) address MSBs, and (3) an address deteOor and RAS line for each memory bank or group of memory banks. This may be 32 memory banks or groups of memory banks for one configuration or may be ten memory banks or groups of memory banks for an IBM PC XT configuration having ten memory banks, or otherwise.
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In another configuration, an address space deteαor can be implemented to monitor external scanout bits instead of re-addressing bits. This configuration can be implemented without an address space deteOor because the address space of each memory bank is determined by the external scanout lines. This configuration is compatible with the other configurations discussed herein, such as use of multiple address buffers and deteOors and steering of the RAS lines. In this configuration, steering of RAS lines may be considered to provide seleOive re-addressing on a per memory chip or per memory bank or per group of memory banks basis while the steering of external scanout lines selects the address space for a memory bank and performs internal scanout within the seleOive external scanout bank memory space and within the previously seleOed re-addressing bits in that externally seleOed memory bank. This facilitates programmable computer processing with jumping around of addresses between memories. This also facilitates branching to a sub-routine by re- addressing to get to that sub-routine in another memory bank and then by returning to the original memory bank without the need for additional re- addressing. This also facilitates going back and forth between two row addresses in different memory banks, such as with an instruOion memory bank and an operand memory bank, without having to continually re-address in a global re- addressing manner. This is achieved because of this seleOive re-addressing configuration. SeleOive re-addressing effeOively partitions the memory into different memories. It is particularly useful where the memories are different memories. For example, one memory bank can be implemented as an operand memory bank and other memory banks can be implemented as instruαion memory banks and operating with external scanout between memory banks. The memories can be optimized for a particular type of processing; such as with one memory bank being implemented as an operand memory bank, another memory bank being implemented as a cache memory bank, and a group of other memory banks being implemented as instruαion memory banks. This configuration is consistent with storing of instruOions in cache or instruαion memory banks and storing variables in operand memory banks. However, such configurations may somewhat increase the amount of re-addressing. An assembler can be configured to store operand variables in the operand memory bank and the hardware can be configured to use the cache memory bank or a DMA buffer memory bank to facilitate such transfers. This configuration has the appearance of mixing together external scanout across
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memory banks for instruαion memory banks with the MSB chip seleα or with RAS/CAS steering to separate operand memory and the cache memory banks. This is an important charaOerization of one configuration in accordance with the present invention, where memory bank seleOion effeOively partitions the memory into a plurality of separate memories (such as ten memories or memory banks) and external scanout scanning across memory banks and seleαing memory banks, such as with the middle significant bits -not most significant bits- integrating multiple memory banks into a single memory. The various configurations of the present invention can be implemented with conventional RAM chips. Alternately, enhancements can be achieved by using custom RAM chips that are optimized to implement the features of the present invention. For example, many configurations will have a high duty cycle for internal scanout and a low duty cycle for re-addressing. One change that can be effeOively made to the DRAM chips is to speed up internal scanout because increasing scanout speed will have a significant impaO on performance due to such a high duty cycle scanout and will have a minor impaO on cost due to the simplicity of the scanout circuitry. Another change that can be effeOively made to the DRAM chips is to slow down re-addressing because reducing re- addressing speed will have a minor impaO on performance due to such a low duty cycle re-addressing and will have a significant impaO on cost due to the re- addressing struOure of DRAM chips. Further, the deteOors and the related circuit can be implemented on the DRAM chips with or without the above discussed speed up of the internal scanout or slow down of the re-addressing. One charaOerization of this configuration is where the memory controller chip monitors the re-addressing bits, each DRAM monitors the multiplexed re- addressing bits and internal scanout bits, and external logic (which may be on the same memory controller chip or on an additional memory controller chip) steers the external scanout bits. In this configuration, neither the re-addressing memory controller nor the memory chips monitor the external scanout bits, both the re-addressing memory controller and the memory chips monitor the re- addressing bits, and only the memory chips look at the internal scanout bits. These charaOerizations can be implemented in the Fig. 4H configurations and can be described with an ADDRESS CORRESPONDENCE TABLE for each variation. This configuration has important features; where the memory controller doesn't have to monitor the internal scanout bits, the memory chips don't have to monitor the external scanout bits, and the internal scanout bits (CAS) and re-addressing bits (RAS) are already implement in current DRAM chip configurations. The external scanout bits give flexibility for memory size and
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configuration. Alternately, the external scanout bits can be the middle significant bits and the chip seleO bits can be the most significant bits, where four address partitions may be needed; internal scanout, external scanout, re- addressing, and chip seleα in that order of significance of bits to configure a full feature memory (Fig 4T). As the memory size is increased and the number of memories are increased but the DRAM chips are kept constant in the same configuration (for the purpose of comparison); the quantity of external scanout bits can be increased to increase memory size and the chip seleO bits can be increased to increase the number of memories. Increasing the chip seleO bits need not change the relationship between the internal scanout and re-addressing bits which are less significant thereto. However, increasing the internal scanout bits may be considered to spread apart the internal scanout and re-addressing bits, indicating that the re-addressing bits are to be reassigned to the more significant bit positions of the address word and hence involve rewiring. Such rewiring can be facilitated with conneOor type jumpers that jumper in the external scanout bits and the re-addressing bits for the particular external scanout configuration of the memory. Alternately, barrel type shift encoders can be used for this purpose, involving some additional propagation delay and additional logic. Alternately, this type of address seleOion can be performed by the memory controller chip under control of a configuration register. Also, multiple memories each having their own external scanout configuration, which may be different from the others, may be implemented with their own dedicated external scanout configuration registers and logic. Alternately, each separate memory can have its own memory controller chip or can use a shared chip, such as with an address that is shared between memories and such as with memory controller logic and signal paths shared between memories.
Memory Controller Waveforms Memory data books and specification sheets for memories (i.e., DRAMs) provide waveforms and timing parameters that are well known in the art for design of memory systems. For example, see the Toshiba MOS MEMORY PRODUCTS DATA BOOK '86-7 referenced herein. These well known waveforms and timing parameters can be used by one skilled in the art in accordance with the teachings herein to implement memories having the features of the present invention. For example, said Toshiba DATA BOOK has waveform diagrams for normal and OE* controlled read cycles; for read cycles, write cycles, and read-modify-write cycles; for fast page mode, static column
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mode, nibble mode operations; and for RAS* only refresh, CAS* before RAS* refresh, and hidden refresh operations. Also, said Toshiba DATA BOOK has tables of ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS listing the timing parameters. One skilled in the art can use these well known waveforms and timing parameters to design specific timing diagrams in accordance with the teachings of the present invention and can implement circuits to praOice the features of the present from the teachings herein. Examples of use of well known waveforms and timing parameters for the Toshiba TC514256P/J-10 DRAMs from said Toshiba DATA BOOK to design specific timing diagrams in accordance with the teachings of the present invention are disclosed in Figs 7A to 7D and in the discussions related thereto and circuits implementing these waveforms and timing parameters for a memory system are disclosed in Figs 7E to 71 and in the discussions related thereto. Various memory architeαures are disclosed herein; such as discussed with reference to Figs 4F to 4K and such as discussed for memory controller configuration-1 herein; and various memory circuits are disclosed herein; such as deteOor circuits and delay circuits; which can be used to implement various memory architeαures. Memory controller waveforms will now be discussed as providing an alternate method of disclosing features of the present invention. These memory controller waveforms are discussed with reference to specific embodiments; such as memory scanout and re-addressing related waveforms (Figs 7A and 7B) in the context of the configuration-1 disclosure herein and sync pulse related operations in a display configuration (Figs 7C and 7D). These waveforms (Figs 7A to 7D) are illustrative of many other implementations of the features of the present invention. For example, one skilled in the art will now be able to generate other waveforms to implement other configurations in accordance with the present invention from the teachings herein. The waveforms shown in Fig 7A disclose details associated with internal scanout operations, the waveforms shown in Fig 7B disclose details associated with deteαor signal occurrences, and the waveforms shown in Figs 7C and 7D disclose details associated with sync pulse occurrences. Also, the waveforms shown in Figs 7A to 7D are consistent with the arrangement disclosed in Figs 6C to 6N; where particular reference is made to Figs 6C and 6D therein and Fig 6W herein. Also, the waveforms shown in Figs 7C and 7D are consistent with the waveforms shown in Figs 7A and 7B. These memory controller waveforms shown in Figs 7A to 7D are illustrative of various alternate configurations. Memory scanout waveforms in accordance with configuration-1 herein are
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shown in detail in Fig 7A and are discussed in detail in the seOion related to configuration-! herein. Such memory scanout waveforms are illustrative of various alternate configurations; such as configurations operating with memory scanout within a block of memory without needing re-addressing in that block of memory and such as configurations combining memory scanout with other memory operations, such as memory re-addressing operations (Fig 7B) and memory refresh operations (Figs 7C and 7D). Memory scanout and re-addressing waveforms in accordance with configuration-1 herein are shown in detail in Fig 7B and are discussed in detail in the seαion related to configuration-1 herein. Such memory scanout and re- addressing waveforms are illustrative of various alternate configurations; such as configurations operating with memory scanout within a block of memory and operating with memory re-addressing between blocks of memory and such as configurations combining memory scanout and memory re-addressing with other memory operations, such as memory refresh operations (Figs 7C and 7D). The waveforms shown in Figs 7A to 7D disclose operation of one memory configuration in accordance with the present invention. One skilled in the art will be able to praOice the present invention illustrated in these waveforms from the waveforms in Figs 7A to 7D and the discussion herein. One skilled in the logical design art will be able to implement circuitry to generate such waveforms and to praOice the inventive features disclosed therein with digital logic; such as illustrated in Figs 6C and 6D for the Mitsubishi RAM configuration. Further, one skilled in the art will be able to apply these waveforms to other applications and other configurations of the present invention; such as frame sync pulse memory operations, computer instruOion-related memory operations, time available memory operations, cycle stealing memory operations, and other memory operations. Display-related memory operations are shown operating under control of a RUN signal envelope; such as for memory refreshing and for memory scanout. Other memory control signals can be substituted for this RUN signal in the control of memory operations. For example, a DTAC, READY, HOLD, or other processor delay type signal in a computer system, as discussed herein, can be used to initiate memory refresh operations and memory re-addressing operations in a similar way to that shown for the RUN signal controlling of memory operations herein. Memory addressing waveforms (i.e., memory scanout and re-addressing waveforms) and memory refresh waveforms in conjunOion with a time available signal (i.e., a line sync pulse signal) are shown in detail in Figs 7C and 7D and
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will now be discussed in more detail. Fig 7C shows the relationship of the field sync pulse FS (waveform-A), the line sync pulse LS (waveform-B), and the memory waveforms (waveform-C to waveform-H). Fig 7C shows the RUN signal (waveform-C and waveform-D) which defines the portion of the LS pulse that is to be used for displaying 720A (RUN) and the portion of the LS pulse that is used for DRAM refreshing, for modal deteOor re- addressing, and for updating of the display .parameters 720B (RUN*). The RUN* signal 720B is coincident with the front portion 720C of the LS pulse 720D and the RUN* signal 720C is shorter than the LS pulse 720D. For the LS pulse controlled memory operations shown in Fig 7C, neither the RUN signal 720A nor the RUN* signal 720B is enabled during the FS pulse 720E; consistent with the implementation shown in said Figs 6C, 6D, and 6W. In alternate configurations, such as FS pulse refreshing operations, memory refreshing can be performed during the FS pulse period. Fig 7C further shows a CAS refresh envelope 720G (waveform-E) and a RAS refresh envelope 720H (waveform-F) coincident with the RUN* signal envelope 720F for controlling memory refresh operations. CAS before RAS signals 7201 (waveform-G) are initially generated in response to the start of the RUN* envelope 720B to initiate DRAM refresh operations followed by multiple RAS refresh pulses 720H (waveform-F and waveform-M) to invoke multiple refresh operations for the duration of the RUN* envelope 720B. RAS before CAS signals 720J (waveform-H) are generated in response to the end of the RUN* envelope 720B to terminate DRAM refresh operations and to invoke display operations. For the alternate embodiment of FS pulse refreshing, the CAS and RAS refreshing operations can be implemented during the FS pulse period 720K; similar to the configuration discussed for LS pulse refreshing operations discussed with reference to waveform-E and waveform-F. For example; DRAM refreshing can be performed during the FS pulse; such as by adapting the memory refresh-related waveforms shown associate . with the LS pulse (i.e.; w veforms E, F, G, and H) to operate in conjunOion with the FS pulse. Fig 7D shows in more detail the waveforms associated with a single one of the line sync pulses 720D shown in Fig 7C. The display clock CPD (waveform-l) synchronizes display processing operations. An LS pulse 720D is shown synchronized with the CPD clock as synchronized LS pulse CLSRl (waveform-J and Fig 6D). A single cycle (waveform-K) of the RUN signal 720B establishes the portion of the LS pulse 720D that is to be used for display (RUN) 720A and the portion of the LS pulse 720D that is to be used for DRAM refresh and for
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-2Θ2- updating of the display parameters (RUN*) 720B. The RUN* signal 720B is shown as being initiated coincident with the front portion 720L of the LS pulse 720D and the RUN* signal 720B is shown as being shorter than the LS pulse 720D, as implemented in said Figs 6C, 6D, and Fig 6W. The CAS and RAS signals are shown in waveform-L and waveform-M generating a CAS (negative going edge) before RAS (negative going edge) operation 720M when the RUN signal makes a high to low transition (the beginning of the RUN* signal) for initiating memory refresh operations and are shown generating a first RAS (negative going edge) before CAS (negative going edge) operation 720N when the RUN signal makes a low to high transition (the end of the RUN* signal) for initiating memory read operations. Fig 7D shows how the RAS signal and the CAS signal contribute to the generation of a CAS before RAS condition 720M at the beginning of the RUN* signal to initiate refreshing and contribute to the generation of a RAS before CAS condition 720N at the end of the RUN* signal to initiate reading information from the DRAM (waveform-M). In addition, a sequence of RAS pulses are generated inbetween the CAS before RAS leading condition and the RAS before CAS trailing condition (waveform-M) to command multiple DRAM refresh operations in the refresh mode. Fig 7D shows the gated clock signal (waveform-N), such as gated clock signal U21 D-8 (Figs 6C and 6W) as being representative of DRAM read operations. It is shown proceeding at a scanout rate 720P and 720Q while the RUN signal is high and it is shown disabled 720R while the RUN signal is low. When the RUN signal goes high, the RAS before CAS operation initiates scanout cycles 720Q. Scanout and re-addressing signals, such as CAS and RAS signals, are enabled by the RUN signal 720A, as indicated by the hatched areas of waveform-C and waveform-K (Fig 7C and 7D), and are discussed in detail with reference to Figs 7A and 7B herein. For simplicity of illustration of memory operations and because of the detailed memory read operations shown in Figs 7A and 7B, the CAS signals (waveform-E and waveform-L shown in Figs 7C and 7D, respeOively) and the RAS signals (waveform-F and waveform-M shown in Figs 7C and 7D, respeαively) do not redundantly show the scanout CAS pulses and the re-addressing RAS pulses, respeαively, that are shown in detail in Figs 7A and 7B. Such CAS and RAS read signals are illustrated in Figs 7C and 7D as being coincident with the hatched areas in waveform-C and waveform-K, respeOively. However; it is intended for this example that the CAS signal (waveform-E and waveform-L) have CAS read pulses for accessing the DRAMs
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when the RUN signal is high, as indicated by the hatched areas in waveform-C and waveform-K (Figs 7C and 7D), and that the RAS signal (waveform-F and waveform-M) have RAS read pulses for re-addressing the DRAMs when the RUN signal is high, as indicated by the hatched areas in waveform-C and waveform-K (Figs 7C and 7D).
Memory Controller Configuration-1 IntroduOion Various DRAM system configurations can be generated to illustrate the features of the present invention; including memory architeOures and memory controllers. One of these memory controller configurations, memory controller configuration-1, is implemented to control Toshiba TC514256P/J-10 DRAMs; which are by-4 (4-bit output), 100ns (RAS access time), fast page mode DRAMs. See the Toshiba data book (referenced herein) at pages 119 et seq. This memory controller configuration is shown implemented in the form of an image memory controller for a display system and is designed to be expandable to 4-megapixels of 16-bits per pixel. However, this memory controller configuration can be readily reconfigured for a microcomputer main memory or other system applications. Also, it can be readily designed to be expandable to 100- megawords (or 100-megapixels), to 500-megawords (or 500-megapixels), or more and it can be readily designed having 8-bits per word (or per pixel), 16-bits per word (or per pixel), 32-bits per word (or per pixel), or more. Further, the memory controller configuration can be readily configured to use DRAMs having modes other than the fast page mode, such as the static column mode and the nibble mode. The waveforms for the fast page, static column, and nibble modes are set forth in the Toshiba Data Book referenced herein. A specific adaptation of the fast page mode waveforms to praOice the present invention is discussed in detail herein with reference to Figs 7A to 7D. One skilled in the art can readily reconfigure Figs 7A to 7D to use static column mode and nibble mode DRAMs in place of the fast page mode DRAMs from the teachings herein. Memory controller configuration-1 can be used with a range of memory architeOures. For example, memory controller configuration-1 can be used in conjunOion with multi-dimensional memory architeOures (Fig 4E), with single dimensional memory architeOures (Fig 4F), with memory architeαures having internal scanout and external scanout (Figs 4H to 4K), with memory architeOures having internal scanout without external scanout, memory architeOures having external scanout without internal scanout, and others.
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The memory controller configuration-1 design is specific to one embodiment; having specific components, specific timing, specific schematics, etc. of one specific configuration. This configuration is intended to be illustrative of one configuration of the present invention, not limiting of the scope of the present invention. Many other controller configurations can be implemented by one skilled in the art to praOice the features of the present invention for other applications, other memory chips, other system requirements, etc. One design objeOive is to optimize the memory data rate (i.e., access rate and writing rate) using a scanout operation. Another design objeOive is to minimize the clock rate of the highest speed master clock needed to provide the memory access rate.
Memory Controller Waveforms Memory controller waveforms are shown in Figs 7A and 7B, which illustrate memory addressing operations, such as memory scanout and re-addressing operations. The memory waveforms shown in Fig 7A illustrates internal scanout using CAS* cycles without re-addressing RAS* cycles for simplicity of illustration. The memory waveforms shown in Fig 7B illustrates internal scanout using CAS* cycles with an interspersed re-addressing RAS* cycle. These Fig 7A and 7B memory waveforms have been briefly discussed herein in conjunOion with the Fig 7C and 7D memory waveforms herein and will now be discussed in greater detail below. The Fig 7A and 7B memory waveforms has been carefully designed to optimize performance and to meet the timing requirements for the Toshiba TC514256P/J-10 DRAMs. They are applicable to an image memory for a display system, a main memory for a stored program computer, an array memory for an array processor, a DMA memory for a DMA processor, a filter memory for a filter processor, a cache memory processor, an artificial intelligence processor, and other memory applications. For convenience of discussion, signals may be discussed with reference to an image memory for the display system; which is illustrative of many other configurations. There is significant commonality between read and write operations. The primary difference is control of the WRITE* signal to generate a read operation when high and to generate a write operation when low. Address-related signals (i.e.; CAS*, RAS*, and addresses) are generally common to both, read and write operations. The read and write circuits (i.e., control of the WRITE* signal) is discussed with reference to the logic diagrams herein. Fig 7A illustrates internal scanout operations without the need for re-
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addressing, such as for the data being accessed from a single memory page. Fig 7B illustrates internal scanout operations and a single re-addressing operation, such as for the data being accessed from two memory pages. The waveforms shown in Figs 7A and 7B will now be discussed in more detail. Signal F500A (waveform-7A in Figs 7A and 7B) is a higher speed master clock, seleOed to be 66.6 MHz having a 15-ns period for this memory controller configuration-1 in order to meet the memory data rate objeOives with a relatively slow speed master clock. Increased memory performance can be obtained by using a higher frequency master clock to obtain finer time resolution control of the generated signals. Signals F500B and F500C (waveform-7B and waveform-7C, respeOively, in Figs 7A and 7B) are lower speed secondary and tertiary clocks, respeOively; seleOed to be one half and one quarter, respeαively, of the frequency of master clock signal F500A. Signals F500B and F500C are used in combination with signal F500A to generate various clocks, strobes, and other signals having the desired phases, time relationships, and pulse widths. Signal F500C is used as the main display processor fre* 3 running early clock CPE, is slightly earlier than the main display processor free running delayed clock CPD, and is also slightly earlier than the main display processor gated delayed clock CPG; which are described with reference to Figs 6B to 6D. Signal F500A is configured to have a 15-ns period so that tertiary clock signal F500C (having 4-times the F500A clock signal period) will have a half cycle of 30-ns to be equal to the minimum CAS* so ^ut address update period. e address signals (waveform-7D in Fig 7A) are shown as horizontal lines 721 A for stable address signal conditions and as diagonal crossed lines 721 B for changing address signal conditions. The address change periods 72 I C (i.e., 30- ns) are related to the propagation delay for CAS cycles. The address signals (waveform-7D) are ch a nged on the positive going edge of the CPD clock signal in accordance with trie gated clock for the address generators (i.e., Figs 6B to 6D). Increased memory performance can be obtained by using a shorter t A ^ address period (waveform-7D in Fig 7A), such a 20-ns t^ A *_| address period, instead of the longer 30-ns period obtained from the F500C clock signal half cycle period. For example, a higher frequency master clock F500A or different logic circuits may be used to shorten this tf AH address period. However, for simplicity of implementation and discussion, the 30-ns F500C clock signal half cvde period is used to generate this t^ A j_-| address period in memory controller cc. figuration-! .
The RAS* signal need not be generated for scanout without re-addressing operations addressing operation in accordance with Fig 7A. The CAS* signal (waveform-7E in Fig 7A) is generated during the scanout period. The internal scanout-related CAS* signal is generated from the F500B and F500C secondary and tertiary clocks to form the (F500B*)(F500Q logical signal. The negative edge of the CAS* signal is used to strobe the DRAMs, as shown by the upwardly pointing arrows under the CAS* waveform (waveform- 7E). Increased memory performance can be obtained by using a shorter t p CAS* period, such a 55-ns tt~p CAS* period, instead of the longer 60-ns period obtained from the F500C clock signal half cycle period. For example, a higher frequency master clock F500A or different logic circuits may be used to shorten this tpc CAS* period. However, for simplicity of implementation and discussion, the 60-ns F500C clock signal full cycle period is used to generate this tpc CAS* period in memory controller configuration-! . The output strobe (waveform-7F in Fig 7A), like the CAS* signal, is generated during the scanout period. The scanout-related output strobe (in complement form) is generated from the F500B and F500C secondary and tertiary clocks to form the (F500B*)(F500Q logical signal, similar to the CAS* signal generation. The positive edge 721 L of the output strobe is used to strobe the output register, consistent with the data being available from the prior CAS* cycle; as shown by the upwardly pointing arrows under the output strobe waveform (waveform-7F). Increased memory performance can be obtained by using a shorter t£ A c output strobe period, such a 35-ns t^ A ^ output strobe period, instead of the longer 60-ns period obtained from the F500C clock signal half cycle period (waveform-7P). For example, a higher frequency master clock F500A or different logic circuits may be used to shorten this t *^ output strobe period. However, because the output strobe period is related to the longer CAS* period and for simplicity of implementation and discussion, the 60-ns F500C clock signal full cycle period is used to generate this output strobe period in memory controller configuration-1. The output strobe is delayed one CAS* period from the corresponding CAS* signal that strobed the DRAM, satisfying the 35-ns t^ A requirement. See the downwardly curved arrows from the negative edge of the CAS* signal to the output positive edge of the enable pulse. Each CAS* negative edge is shown having an output strobe positive edge that is one F500C period later, satisfying the 35-ns requirement. See the downwardly curved arrows from the CAS* negative edge to the output strobe positive edge.
* - S& s* «
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The deteOor signal (waveform-7K in Fig 7B) is disclosed in Fig 6C as an address overflow signal 6C/U14A-6 generated to command a re-addressing operation, but can be generated with various other configurations disclosed herein. It is synchronous with CPG*, the gated clock. It is shown having three CPD/CPG periods for a single overflow operation, starting and ending with CPG* transitions and having two intervening CPD pulses to control time delay flip-flops 6C/U21 B-5 and 6C/U21 B-2 (BL1). The deteOor signal changes on the positive going edge of the CPG* clock signal, which is about coincident with the positive going edge of the CPD clock signal, in accordance with the gated clock logic (i.e., Figs 6B to 6D). The deteOor signal is generated to have a period equal to the sum of the t^p period and the t-^ςp period to facilitate a RAS cycle. The RAS* signal could be implemented to start earlier and hence to reduce the RAS cycle period, such as by implementing a shorter deteOor signal propagation delay or implementing an anticipatory deteOor signal. Other memory deteαors, such as discussed herein, can be used with this memory controller configuration- 1. The address signals (waveform-7L in Fig 7B) are shown as horizontal lines 721 A for stable address signal conditions and as diagonal crossed lines 721 B for changing address signal conditions. The shorter address change periods 721 C (i.e., 30-ns) are related to the propagation delay for CAS cycles and the longer address change periods 721 D (i.e., 40-ns) are related to the propagation delay for RAS cycles. The address signals (waveform-7L) are changed on the positive going edge of the CPD clock signal in accordance with the gated clock for the address generators (i.e., Figs 6B to 6D). Increased memory performance can be obtained by using a shorter t ^ address period (waveform-7L in Fig 7B), such a 20-ns t AH address period, instead of the longer 30-ns period obtained from the F500C clock signal half cycle period. For example, a higher frequency master clock F500A or different logic circuits may be used to shorten this t^μ address period. However, for simplicity of implementation and discussion, the 30-ns F500C clock signal half cycle period is used to generate this t^ A *__ | address period in memory controller configuration-! . The RAS* signal (waveform-7M in Fig 7B) is generated to execute a re- addressing operation. It is implemented to be coincident with the leading portion of the deteOor signal and having a tøp period duration. The negative going edge of the RAS* signal strobes the row address into the DRAMs. The CAS* signal (waveform-7N in Fig 7B) is generated during the scanout period having CAS* scanout signals shown preceding the RAS* signal 721 E and
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following the RAS* signal 72! F. The internal scanout-related CAS* signal is generated from the F500B and F500C secondary and tertiary clocks to form the (F500B*)(F500Q logical signal. The negative edge of the CAS* signal is used to strobe the DRAMs, as shown by the upwardly pointing arrows under the CAS* waveform (waveform-7N). Increased memory performance can be obtained by using a shorter t^p CAS* period, such a 55-ns t^p CAS* period, instead of the longer 60-ns period obtained from the F500C clock signal half cycle period. For example, a higher frequency master clock F500A or different logic circuits may be used to shorten this tpr CAS* period. However, for simplicity of implementation and discussion, the 60-ns F500C clock signal full cycle period is used to generate this tpc CAS* period in memory controller configuration-1. The CAS* signal is also generated during the re-addressing period, being maintained high during the leading portion of the deteOor signal for a period of tøp and tRCD prior to generating a negative going CAS* strobe 721 G. The CAS* cycle at the beginning of a re-addressing period has the negative going edge suppressed 721 H, with the CAS* pulse being extended or stretched for the t RP and t RCD period supra. The output strobe (waveform-7P in Fig 7B), like the CAS* signal, is generated during the scanout period having output strobes shown preceding the RAS* signal 721 E and following the RAS* signal 721 F. The scanout-related output strobe (in complement form) is generated from the F500B and F500C secondary and tertiary clocks to form the (F500B*)(F500Q logical signal, similar to the CAS* signal generation. The positive edge 721 L of the output strobe is used to strobe the output register, consistent with the data being available from the prior CAS* cycle; as shown by the upwardly pointing arrows under the output strobe waveform (waveform-7P). Increased memory performance can be obtained by using a shorter t£ A c output strobe period, such a 35-ns t ^ output strobe period, instead of the longer 60-ns period obtained from the F500C clock signal half cycle period (waveform-7P). For example, a higher frequency master clock F500A or different logic circuits may be used to shorten this t ζ -^Q output strobe period. However, because the output strobe period is related to the longer CAS* period and for simplicity of implementation and discussion, the 60-ns F500C clock signal full cycle period is used to generate this t^ A ^ output strobe period in memory control ler configuration-1. The output strobe is also generated during the re-addressing period, being maintained high during the leading portion of the deteOor signal and generating
1 a positive edge output strobe 721J at the end of the deteOor signal to strobe the
2 DRAM data accessed by the RAS*-related re-addressing CAS* cycle into the
3 output register. Similarly, the first scanout-related output strobe 721M following
4 a RAS* cycle; defined by the (F500B*)(F500O logical term; is suppressed
5 because the CAS* signal associated with the (F500B*)(F500Q logical term
6 occurring in the RAS* re-addressing cycle is suppressed as a result of the RAS*
7 cycle.
8 The output strobe is delayed one CAS* period from the corresponding CAS*
9 signal that strobed the DRAM, satisfying the 35-ns t£ A £ requirement. See the 0 downwardly curved arrows from the negative edge of the CAS* signal to the 1 output positive edge of the enable pulse, such as at the beginning of the RAS* 2 re-addressing cycle. This applies to the CAS* signal, independent of whether it 3 is a scanout CAS* cycle or a re-addressing CAS* cycle. For example; see Fig 7A 4 where each CAS* negative edge is shown having an output strobe positive edge 5 that is one F500C period later, satisfying the 35-ns t A c requirement. See the 6 downwardly curved arrows from the CAS* negative edge to the output strobe 7 positive edge. 8 A disabling or delaying signal; such as for input to a microprocessor READY, 9 DTAC, HOLD, wait state control, or other such circuit; can be derived in 0 accordance with the teachings herein. For example, the deteOor signal * (waveform-7K) (Fig 7B) may be used direOly as a disabling or delaying signal or 2 may be logically processed, such as with the multiple clock signals (the i.e.; 3 F500A, F500B, and F500C) to form a reduced period disabling or delaying 4 signal. Alternately, the RAS* signal (waveform-7M) (Fig 7B) may be used direOly as a disabling or delaying signal or may be logically processed, such as with the multiple clock signals (i.e.; F500A, F500B, and F500Q to form a reduced period disabling or delaying signal. Alternately, other disabling or delaying signals may be generated, such as by logically combining the multiple clock signals (i.e.; F500A, F500B, and F500Q with other memory system signals, to form a disabling or delaying signal.
Refresh Operations Refresh operations in general are discussed herein for a range of different system applications. Now, a particular refresh configuration will be discussed to illustrate how the refresh teachings can be applied to a multi-mode sync pulse refreshed display system. Sync pulse refreshing is particularly applicable to a display system. Other refreshing can be provided; such as for a computer executing read and write
operations and a filter processor. In memory controller configuration-! of the display processor DRAM image memory, four separate display processor modes involve refreshing are implemented, as listed below. 1) The computer write mode. 2) The burst write mode. 3) The read mode. 4) The standby mode. The refresh modes can be implemented in various forms, such as concurrent modes or mutually exclusive modes. In the memory controller configuration-1 embodiment, a mutually exclusive arrangement is implemented. This means that only one mode of refreshing is aαive at a time. For DRAMs that need to be refreshed periodically, one mode should always be aOive. For example, the standby mode can be implemented to be a default mode that is aαive whenever the other modes are all inaOive; such as with mode OR-NOT logic. The computer write mode can be used for loading the image memory from a supervisory computer, such as the Imsai S-100 computer, it can be executed at relatively low speed as the computer outputs pixel after pixel under program control. It may be used to write other information, in addition to pixels, into image memory. For example, other information may need to be written into image memory; such as the sky colors, and other information may have to be read from image memory, such as table information for the table lookup processing. Refreshing during the computer write mode can be executed in various ways, such as being performed under control of a computer output strobe (i.e., DOA7 for the Fig 6B configuration and STRB for a 68HC11 configuration) synchronous with computer output operations or being performed under control of special purpose circuits inbetween computer output operations. For said synchronous refreshing, the computer output strobe (i.e., DOA7 for the Fig 6B configuration and STRB for a 68HC11 configuration), which is generated for each output operation can also be used to generate a RAS* refresh strobe. For said inbetween refreshing, refreshing can be performed inbetween computer output strobes by implementing refresh circuitry to generate RAS* refresh strobes when a computer output strobe (i.e., DOA7 for the Fig 6B configuration and STRB for a 68HC11 configuration) is not present. The burst write mode can be used for loading the image memory from a high speed disk memory. It can be executed at relatively high speed as a disk memory loads pixel after pixel under control of a disk controller. It too may be used to write other information, in addition to pixels, into image memory supra.
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-211- For example, it may be invoked to burst load pixels and other information during the field sync pulse period in order to avoid contention with display operations and also to simplify refreshing. Refreshing may be simplified by enabling refreshing operations for each mode (except possibly for the computer write mode which may have its own self contained computer synchronized refreshing) at the beginning of each line sync pulse and leaving the field sync pulse period free of refreshing requirements. Consequently, refreshing of image memory during the burst write mode can be consistent with line sync refreshing discussed herein. The read mode, when scanning out the image, and the standby mode, when not scanning out the image nor writing, can both be implemented to enable refreshing during the beginning of each line sync pulse, as discussed herein. This line sync refreshing may be less desirable for the computer write mode because it may be more inefficient to synchronize the computer write operations with the computer output strobe (i.e., DOA7 for the Fig 6B configuration and STRB for a 68HC1 ! configuration) then with the sync pulses. Consequently; in order to avoid contention, the write mode signals (DOA5 and DOA6) can be used to disable the line sync and field sync commanded refresh operations. Hence, line sync refreshing can be disabled whenever the image memory is not in a computer write mode. Alternately, the read mode, when scanning out the image, and the standby mode, when not scanning out the image nor writing, can both be implemented to enable refreshing at times other than during the beginning of each line sync pulse. For example, refreshing can be implemented on a cycle stealing basis, such as by stealing cycles from image scanout at 5-refresh operations per line period or other more suitable rate, or on a field sync basis, such as during each field sync period, or on another basis. The number of refresh cycles per scanline will now be calculated. Assuming the condition of 480 video scan lines/frame, an interlaced video scan of 2- fields/frame, a video frame period of 0.034 seconds, and a DRAM refresh period of 0.008 seconds; a minimum of 5-refresh cycles can be generated per line sync pulse. (512 DRAM rows/DRAM refresh period) (480 scanlines/0.034 seconds)(0.008 seconds/DRAM refresh period) - 512/1 13 - 4.5
Assuming a 100ns DRAM having a 200ns refresh cycle period and a 16MHz clock (memory controller configuration-1), 5-refresh cycles involve about 1 us.
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Refreshing of a disk input buffer memory will now be discussed. It may not be necessary to refresh a disk input buffer memory in the burst write mode for conditions where disk loading operations implicitly refresh the DRAMs during read and write operations. Refreshing of the disk input buffer memory can be implemented as discussed herein for DRAM refreshing. Also, refreshing of the disk input buffer memory at times other than during disk loading operations can be implemented, such as discussed for the standby refresh mode of the image memory. In view of the above, disk input buffer memory refreshing may be performed in two different modes, as listed below. a) In the disk load mode when the disk input buffer memory is being loaded from disk. b) In the standby mode when the disk input buffer memory is not being loaded from disk and is not in a burst write mode. In the disk load mode, the disk input buffer can be refreshed for each byte transferred from disk similar to the implementation of the computer write mode __a_r_, because of the relative slowness of the disk load operations. In the standby mode, the disk input buffer may not be performing other operations and hence may be continuously refreshed supra.
Read And Write Operations Read and write operations for memory controller coπfiguration-1 are shown in the timing diagrams (Figs 7A and 7B) and the logic diagram (Figs 7E and 7F). The internal CAS scanout maximum rate is a funαion of the address counter propagation delay and the DRAM register hold time. RAS re-addressing maximum rate is a funαion of the RAS* delays (t R p and
Mode Transitions The transitions between the various modes has been carefully considered and has been designed to be hazard free. For example, modes have been designed to be mutually exclusive, operation has been designed to resolve contention, and guardbands have been used to improve modal transitions to teach the artisan use of these features. Various other mutually exclusive modal arrangements, designs to resolve contention, and guardbands can be implemented by the artisan from the teachings herein. Alternately; modes can be interspersed and guardbands can be reduced or eliminated. The transitions between the scanout read mode and the re-addressing read
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mode are hazard free, as shown in Figs 7A and 7B supra. In order to simplify the configuration-1 example, it is herein assumed that the slope parameters for updating the address registers are seleOed to eliminate multiple sequential overflows. For example, slopes of 0.5 pixels, or 0.25 pixels, or 0.125 pixels, etc. will provide such operation. The transitions between the read modes and the burst write mode is hazard free, particularly when the burst write mode is invoked during the field sync pulse period. This is because, in this memory controller configuration-1, the read modes are disabled during this field sync pulse period. A guardband having a small delay precedes the start and follows the end of the burst write operations. The transitions between the read modes and the computer write mode is hazard free because of the following. For startup or initialization computer write operations in memory controller configuration-1 , any in-process read operations are transitionary operations and hence of no concern. For continuing computer write operations in memory controller configuration-1 , such as for loading a table lookup; write operations are invoked during the field sync pulse period with a guardband and hence are hazard free.
Signal Generation Configuration-1 controller signal generation can be implemented in various ways; such as with different types of synchronous circuits, asynchronous circuits, or combined synchronous and asynchronous circuits. A synchronous implementation is shown in Figs 7A to 71 using clock oscillator 756A generating master clock signal F500A, flip-flop 756B counting down master clock F500A to get secondary clock F500B, and flip-flop 756C counting down secondary clock F500B to get tertiary clock F500C. These clock signals are used to synchronously generate the various memory control signals. CAS operations will now be discussed for memory controller configuration-1. CAS operations can be invoked during various conditions, such as during the three modes listed and discussed below. 1) The run mode. 2) The computer write mode. 3) The refresh mode. There is no contention between these three modes because they are mutually exclusive and because the present implementation has a built in guardband (extra i me) separating the different modes. For example, the write mode is implemented under control of the supervisory computer during the FS pulse
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when the run mode and the refresh mode are disabled and the write mode has a guardband separating write cycles resulting from software delays in the supervisory computer which generates the write strobe (DOA7) under program control. Also, the run mode is generated inbetween line sync pulses and the refresh mode is generated during line sync pulses with U22E flip-flop propagation delays separating these modes. Also, the U22E register (Fig 7G) is shown having an extra stage at the beginning before the CLSR1 stage for a guardband delay before invoking refresh cycles. ' During the run mode, the CAS signal can be generated for internal scanout operations (Fig 7A) and for internal scanout and re-addressing operations (Fig 7B). The CAS signal can be generated by properly setting and resetting the CAS flip-flop 756D. Zero setting of the CAS flip-flop is enabled by the RUN signal U13A-8 and by the DOA6 signal, as discussed for clock signals U12A-6 and U12A-8 (Fig 6Q. The CAS signal is controlled to follow the F500B* AND F500C signal condition (Fig 7A); except that this sequence is interrupted during the RAS re-addressing operation (Fig 7B); by being clocked high by the F500B AND F500C signal 756E and being clocked low by the F500B* AND F500C signal 756F. Because the DRAM CAS operation is invoked by the negative going edge of the CAS signal, the reset input to the CAS flip-flop may be considered to be more important than the set input is to the CAS flip-flop. Fig 7A run mode CAS signal generation will now be discussed. During the run mode and for the condition that deteαor signal U14A-6 is high (indicative of internal scanout operations), the CAS signal follows the (F500B*)(F500Q clock phases. The CAS flip-flop 756D can be set by the F500A clock signal clocking the F500B AND F500C signal (756E) into the CAS flip-flop just before the F500B signal is clocked to go low in the middle of the F500C clock pulse period when the F500C clock pulse is high (F500B AND F500Q. The CAS flip-flop can be reset by the F500A clock signal clocking the F500B signal (756F) into the CAS flip-flop just before the F500B signal is clocked to go high at the end of the F500C clock pulse period when the F500C clock pulse is high and going low (F500B AND F500C*). Fig 7B run mode CAS signal generation will now be discussed. During the run mode and for the condition that the deteOor signal U23C-10 is high (indicative of the re-addressing operation) and in addition to the Fig 7A conditions; two additional conditions need be to be considered. 1 ) The start of the RAS signal 721 H (Fig 7B). 2) The RAS-related CAS operation 721G (Fig 7B). The CAS signal can be kept from going low at the start of the RAS signal 721 H
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and can be kept high until the RAS-related CAS operation 721G with the circuitry shown in Fig 7E, as discussed below. The CAS signal can be kept from going low at the start of the RAS signal 721 H by disabling the resetting of the CAS flip-flop with the anticipatory gate (deteOor) signal U23C-11 (Fig 6Q, where the anticipatory gate (deteOor) signal U23C-1 1 (Fig 6Q anticipates an immediately following gate (deteOor) signal. In this configuration, the CAS signal is kept high during the RAS-related gate (deteOor) signal (Fig 7B, 721 H to 721 G) until the RAS-related CAS operation is executed by enabling the resetting of the CAS flip-flop with the proper gate (deteOor) signal U21 B-2 (Fig 6Q, thereby over-riding the gate (detector) signal disabling of the CAS signal through gate 756J. It should be noted that, in this configuration, the CAS signal is kept high during the gate (deteαor) period because the same anticipatory gate (deteαor) signal U23C-11 (Fig 6Q that disables the resetting of the CAS flip-flop supra is kept unchanged because the gated clock (CPG) is disabled during the gate (deteαor) period and hence the address counter is not docked and does not change. After generating the RAS-related CAS operation 721G, the CAS signal is kept low through the next F500B* AND F500C operation by disabling the CAS flip-flop from being set with the U23C-10 deteOor signal. During the computer write mode, the CAS signal can be controlled as part of a full RAS/CAS write cycle for every computer write operation. This can be accomplished by generating a sequence of RAS and CAS pulses that is initiated with the computer output strobe (i.e., DOA7 for the Fig 6B configuration and STRB for a 68HC11 configuration). One write configuration is disclosed with reference to Figs 7G and 7H, as discussed in detail below. During the memory refresh mode, the CAS signal can be controlled as part of RAS and CAS refresh cycles for every LS pulse that occurs during the FS* period. This can be accomplished by generating a sequence of RAS and CAS pulses that is initiated with the LS pulse. One refresh configuration is disclosed with reference to Figs 7G and 7H, as discussed in detail below. The F510 signal from the refresh mode and write mode circuit (Fig 7G) is shown input to gate 756M in Fig 7E for combining with the run mode CAS signal from CAS flip-flop 756D to generate the CAS output signal from gate 756N to the DRAM chips. When in the run mode, the run signal U13A-8 disables gate 756M through the inverter and enables gate 756L to pass the run mode CAS signal from flip-flop 756D through gate 756N to the DRAM chips. When in the refresh mode or write mode, the run signal U13A-6 disables gate 756L and enables gate 756M through the inverter to pass the refresh mode and write mode CAS signal F510 generated in Fig 7G through gate 756N to the
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DRAM chips. RAS operations will now be discussed for memory controller configuration-1. RAS operations can be invoked during various conditions, such as during the three modes listed and discussed below. 1) The run mode. 2) The computer write mode. 3) The refresh mode. There is no contention between these three modes because they are mutually exclusive and because the present implementation has a built in guardband (extra time) separating the different modes supra. During the run mode, the RAS signal is held low during the fast page operations (Fig 7A) and is seleOively controlled to go high during the re- addressing operations (Fig 7B). As shown in Fig 7B, the RAS signal is controlled to go high for 80-ns or more beginning at the start of the re-addressing gate (deteOor) signal. This is achieved with the RAS flip-flop 757D being set simultaneously with the gate (detector) flip-flop (U23Q using the anticipatory gate (deteαor) signal (U23C-11). The RAS signal is then reset to be low after 80ns or more, achieved with the RAS flip-flop being cleared with the proper logical combination of the F500B* and F500C* clocks and the first gate (deteOor) phase signal (U21 B-5). Fig 7B run mode RAS signal generation will now be discussed. During the run mode and for the condition that the deteOor signal U23C-10 is low (indicative of the internal scanout operation) as shown in Fig 7A; the RAS flip- flop 757D is kept low, having previously been cleared and having the D input held low with the U21 B-5 signal being low. During the run mode and for the condition that the deteαor signal U23C-11 is high (indicative of the re- addressing operation) and in addition to the Fig 7A conditions; two additional conditions need be to be considered. 1 ) The start of the RAS signal 721 H (Fig 7B). 2) The end of the RAS signal 7211 (Fig 7B). The RAS flip-flop can be set high at time 721 H and can be kept high until the end of the RAS signal 7211 with the circuitry shown in Fig 7E, as discussed below. The RAS flip-flop can be set high at the start of the RAS signal 721 H condition with the U23C-11 anticipatory gate (deteOor) signal through gate 757E to the D input of the RAS flip-flop 757D enabled by the U21 B-5 signal being set low and inverted for inputting to gate 757E. The anticipatory gate (deteOor) signal U23C-11 (Fig 6Q anticipates an immediately following gate (deteαor) signal.
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In this configuration, the RAS signal is kept high during the RAS-related gate (deteOor) signal period (Fig 7B, 721 H to 7211) until the RAS flip-flop is cleared with the proper gate (deteOor) signal U21 B-5 (Fig 6Q. It should be noted that, in this configuration, the RAS signal is kept high during the gate (deteOor) period until the RAS flip-flop is cleared because the same anticipatory gate (deteOor) signal U23C-11 (Fig 6Q that controls the RAS flip-flop supra is kept unchanged because the gated clock (CPG) is disabled during the gate (deteOor) period and hence the address counter is not clocked and does not change. At time 7211, the RAS signal is cleared with the F500B* and F500C* clock condition and the U21 B-5 gate (deteOor) signal, which has gone high, and is maintained low through the rest of the deteOor period U23C-10 by disabling the RAS flip-flop from being set by the U21 B-5* deteOor signal to gate 757E. Further, the RAS signal is assured of being set low for scanout operations by clearing the RAS flip- flop with the U23C-10 deteOor signal through the inverter to gate 757C to the clear-bar input of the R. 5 flip-flop. During the computer write mode, the RAS signal can be controlled as part of a full RAS/CAS write cycle for every computer write operation. This can be accomplished by generating a sequence of RAS and CAS pulses that is initiated with the computer output strobe (i.e., DOA7 for the Fig 6B configuration and STRB for 68HC11 configuration). The IR Q period has a maximum value requirement in addition to a minimum value requirement. The RAS signal going low should precede the CAS signal going low by the I-^ Q period (25ns to 65ns). The one CPD clock period separating the CAS and RAS signals is 60ns, which meets this maximum timing requirement for this configuration. During the memory refresh mode, the RAS signal can be controlled as part of RAS and CAS refresh cycles for every LS pulse. This can be accomplished by generating a sequence of RAS and CAS pulses initiated with the LS pulse. One refresh configuration is disclosed with reference to Figs 7G and 7H, as discussed in detail below. The F511 signal from the refresh mode and write mode circuit (Fig 7G) is shown input to gate 757M in Fig 7E for combining with the run mode RAS signal from R • -_. iip-flop 757D to generate the RAS output signal from gate 757N to the DRAM chips. When in the run mode, the run signal U13A-8 disables gate 757M through the inverter and enables gate 757L to pass the run mode RAS signal from flip-flop 757D through gate 757N to the DRAM chips. When in the refresh mode or write mode, the run signal U13A-8 disables gate 757L and enables gate 757M through the inverter to pass the refresh mode and write mode RAS signal F511 generated in Fig 7G through gate 757N to the DRAM chips.
SUBSTITUTE S
During the refresh mode, such as for refreshing during the line sync LS condition; refreshing can be implemented by generating the RAS and CAS signals for one of the various refresh modes, such as the CAS before RAS refresh mode. Implementation of the CAS before RAS refresh mode enabled by the CLSR signals generated by the CLSR register U22E (Figs 6D and 7G) will now be discussed for this configuration-1 for convenience. Many other configurations can also be implemented. The U22E register circuit, as modified for this refresh operation, is shown in Fig 7G. The U22E register has the U20E-6 signal (Fig 6D) as an input. This U20E-6 signal has the logical equation CLSRl AND CFSRl * so that it will follow the CLS line sync signal during the CFS* condition but not during the CFS condition. This resolves contention between write operations that are performed during the CFS period and with refresh operations that are performed during the CLS* period. The U22E register is clocked with the CPD signal (Figs 6D and 7G). The various register stages generate the CLSR1, CLSR2, and CLSR4 signals and are separated by the stage generating the CLSR3 signal (Figs 6D and 7G) and are modified to have a plurality of additional stages related to the CLSR3 stage and to have a guardband stage preceding the CLSR1 stage (Fig 7G). For the modified Fig 7G configuration, the CAS refresh signal F505Q and the RAS refresh signal F506Q are shown being generated under control of clock CPD and hence the refresh gray code counter flip-flops F505Q and F506Q (discussed below) are clocked at the CPD (and hence the CPE) clock rate. Consequently, the four phases of the two bit gray code counter F505 and F506 take four CPD clocks for a refresh operation. The number of CLSR3 flip-flops in the CLSR register can be seleOed in various ways; such as to make the total number of stages in the CLSR register equal to four times the number of refresh cycles to be generated during the LS pulse plus the guardband stage or stages. For example, if one guardband stage is to be used and if eight refresh cycles are to be generated, the CLSR1 to CLSR4 stages (including the multiple CLSR3 stages) total 32 stages plus one guardband stage for a total of 33 stages. Further, extra stages can be inserted before the CLSRl stage, for the CLSR3 stages, after the CLSR4 stage, etc. as needed for guardband stages and as needed to adjust the stages of delay to synchronize the CLSR signal U19D-4 with the refresh operations. It is desirable that the F505 and F506 flip-flops are both left in the high state following the refresh operation so that the transition from the refresh mode and the run mode is made with the F505 and F506 flip-flops in the high state. This is accomplished by seleαing the number of U22E stages to end in this condition.
For example, the abovementioned 32 stages (less guardband) starts the F505 and F506 flip-flops in the high state and concludes with the F505 and F506 flip-flops in the high state. In alternate configurations; a counter, such as implemented with 74LS161 counter circuits, can be used to perform the funαions performed with register U22E. For example, the 32 CLSR register stages discussed for the configuration- 1 refresh implementation supra can be reduced to five counter stages. Figs 7G and 7H show the refresh signal generation circuitry and waveforms, respeOively. A review of the CAS before RAS refresh waveforms at page 127 in Toshiba Data Book referenced herein indicates that the CAS and RAS waveforms have the general form of two squarewaves that are 90 degrees out of phase. These waveforms are shown in simplified form in Fig 7H having the refresh timing symbols (t) superimposed thereon and having the related minimum values for these timing symbols (shown with greater-than symbols) for the Toshiba TC514256P/J-10 superimposed thereon. Such waveforms can be generated in various ways, such as by a gray code counter having the following transition table.
TRANSITION TABLE PRESENT STATE NEXT STATE F505Q F506Q F505D F506D 0 0 0 1 0 1 1 1 1 0 0 0 1 1 1 0
One configuration of a gray code counter is shown in schematic form in Fig 7G with flip-flops F505 and F506 for implementing this transition table. Review of the minimum time values (Fig 7G) indicates that a gray code counter clock having a 50-ns clock period (quarter cycle period) can meet the refresh cycle CAS and RAS timing requirements. The 60-ns F500C clock signal can be used because it is conveniently available and because it has a wide safety margin for this gray code counter clock. The gray code counter is shown being set with the output of gate 756R, comprising the complement of the CLSR1 signal and the output of the guardband stage 756S, through gate 756K so that the gray code counter will start off in the set state, consistent with the start of the CAS before RAS refresh waveform in said Toshiba Data Book. The output of gate 756R occurs at the beginning of a CLS period when the CLS signal (included in the U20E-6 signal) has just set the guardband flip-flop but has not as yet set the CLSRl flip-flop, thereby generating a short one clock period wide pulse out of gate 756R to preset the gray code counter. A D flip-flop having an asynchronous SET* circuit, such as the 74LS74 D flip-flop, is shown for convenience of discussion. However, other circuits, such as RS or JK flip-flops or counter circuits, can be used. Also, the asynchronous SET* circuit can be replaced with initializing circuitry, such as at the synchronous input (i.e., D input) circuits. Also, other circuit arrangements can be used to implement the configuration-1 controller. The CAS refresh signal F505Q and the RAS refresh signal F506Q are shown enabled with the CLSRl signal to perform refreshing operations during the CLSRl condition. The CLSRl signal enables gate 758B to permit the F505Q signal to be output as the F510 CAS signal from gate 758E and enables gate 758C to permit the F506Q signal to be output as the F511 RAS signal from gate 758F while the F507Q* signal disables gates 758A and 758D to prevent the F506Q signal from being output as the F510 CAS signal from gate 758E and to prevent the F505Q signal from being output as the F511 RAS signal from gate 758F.
SUBSTITUTE SHEET
The write circuit implementation will now be discussed with reference to Figs 7G and 71. The write operations for this configuration-1 are simplified for the following reasons. The address signals and the write mode signal DOA5 are setup by the computer before generating the DOA7 pulse to perform the write operation (i.e., Fig 6B). Also, the RAS signal automatically controls the RAS and CAS multiplexers to generate the sequence of first the RAS address and then CAS address being applied to the DRAMs in synchronization with the RAS and CAS signals (i.e., Figs 4H to 4K). The write mode is invoked with the DOA5 signal being high and the DOA6 signal being low. Then, the DOA7 pulse going high initiates a write cycle. See Fig 6B at U22B-3, U22C-11, U18E-11, etc. Gate 756T (Fig 7G) generates a signal to set the F507 flip-flop during the write mode before the write strobe DOA7 is generated to initialize the gray code counter through gate 756K. The U22C-11 signal and the DOA5 signal (Fig 6B) are NANDed together with NAND gate 756T to generate a set signal when in the write mode (DOA5) and before the write strobe (U22C-11) is generated to set the F505 and F506 flip- flops (Fig 7G). This initializes the gray code counter in the write mode when a DOA7 write pulse is not present and initiates a RAS and CAS write cycle when a DOA7 write pulse is generated. After a single RAS and CAS write cycle is completed, the feedback signal from gate 756U sets the F507 flip-flop to terminate the RAS and CAS write cycle with the F505 and F506 flip-flops in the set condition. Many other configurations can also be implemented. The F505 and F506 flip-flops are controlled to generate a single RAS/CAS sequence (Fig 71) starting from the F505 and F506 flip-flops both being in the high state and ending with the F505 and F506 flip-flops both being in the high state. The starting of the F505 and F506 flip-flops in the high state is performed with the signal from gate 756T, as discussed above. The ending with the F505 and F506 flip-flops in the high state is discussed below. The F505 and F506 flip- flops are sequenced from both flip-flops being in the high state through the gray code counter states shown in the transition table supra and in the waveforms in Fig 71 through the F505Q* AND F506Q and F505Q* AND F506Q* states to the F505Q AND F506Q* state. This F5ϋ;.Q AND F506Q* state is deteOed with gate 756U (enabled with the write mode signal DOA5) to set flip-flop F507. Flip-flop F507 was reset by the signal from gate 756T that initialized the F505 and F506 flip-flops. Now, flip-flop F507 being set causes the F505 and F506Q flip-flops to be set through gate 756K until the signal from gate 756T again resets flip-flop F507 for another write cycle or until another mode in seleOed. The
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setting of the F506 flip-flop when the F505 flip-flop goes high (when the F506 flip-flop is low) through gate 756U, flip-flop F507, and gate 756K is consistent with the write cycle timing waveforms in said Toshiba Data Book at page 124 because there is no time delay required between the RAS signal going high and the CAS signal going high, where it is even permissible for the CAS signal to go high before the RAS signal goes high. Flip-flop F507 insures that only a single write cycle will be generated with the gray code counter. This is achieved by the following. The F507 flip-flop is reset in the write mode during the period that the write strobe U22C-1 1 is high by resetting the F507 flip-flop with the U22C-1 1 signal and the DOA5 signal through gate 756T. When the write strobe U22C-1 1 goes low, the reset input circuit is disabled and the set input circuit is enabled. When the gray code counter is advanced to the F505Q AND F506Q* state, indicative of the completion of the write cycle; the F507 flip-flop is clocked to the set condition, setting the F505 and F506 flip-flops through the 756K gate and maintaining the F505 and F506 flip-flops set. The F505 and F506 flip-flops are maintained set until the write strobe U22C-1 1 ends; thereby resetting the F507 flip-flop, ending the lockup of the F505 and F506 flip-flops, and preparing for the next write or refresh cycle. It is desirable that the F505 and F506 flip-flops are both left in the high state following the write operation so that the transition from the write mode and the run mode is made with the F505 and F506 flip-flops in the high state. This is accomplished by setting the F505 and F506 flip-flops with the F507 flip-flop through gate 756K at the end of the write operation. The circuitry shown in Fig 7G, previously discussed for refresh signal generation circuitry is shown time shared for write cycle operations in the configuration-1 controller. Alternately, a non-time shared (dedicated) configuration can be implemented having the gray code counter F505 and F506 duplicated for refresh and for write operations and having the refresh-related control circuitry dedicated to the refresh counter and having the write-related control circuitry dedicated to the write counter. A review of the CAS and RAS write cycle waveforms for the Toshiba TC514256P/J-10 at page 124 in Toshiba Data Book referenced herein indicates that the CAS and RAS waveforms have the general form of two squarewaves that are 90 degrees out of phase with each other, similar to the CAS before RAS refresh waveforms supra except that the RAS and CAS waveform leading and trailing charaOeristics are reversed from the refresh waveforms. For example, the CAS before RAS refresh operations involve the CAS signal leading the RAS
SUBS
signal while the write operations involve the RAS signal leading the CAS signal. Hence, the refresh waveforms may be considered to be 180 degrees out of phase with each other. The write waveforms, shown in simplified form in Fig 71, are similar to but reversed in phase from the refresh waveforms shown in simplified form in Fig 7H. The write waveforms (Fig 71) can be generated in various ways, such as by a gray code counter having the above discussed transition table. The configuration of a gray code counter shown in schematic form in Fig 7G can be used for implementing this transition table. However, the CAS and RAS outputs of the gray code counter need to be reversed for write operations. The minimum time values for the DRAM write cycle indicates that the gray code counter clock used for refresh operations having a 50-ns clock period (quarter cycle period) can meet the write cycle CAS and RAS timing requirements. As with refreshing operations, the 60-ns F500C clock signal can be used for writing operations because it is conveniently available and because it has a wide safety margin for this gray code counter clock. The gray code counter is shown being set with the F505S signal from gate 756K so that the gray code counter will start off in the set state, consistent with the start of the CAS and RAS cycle write cycle waveform in said Toshiba Data Book. The RAS write signal F505Q and the CAS write signal F506Q are shown enabled with the U22C-11 signal to gate 756T (Fig 7E) to enable a write cycle operation during the DOA5 write mode. The CAS write signal F506Q and the RAS write signal F505Q are shown enabled with the F507Q* signal to enable writing operations during the F507Q condition. The F507Q* signal enables gate 758A to permit the F506Q signal to be output as the F510 CAS signal from gate 758E and enables gate 758D to permit the F505Q signal to be output as the F511 RAS signal from gate 758F while the CLSR1 signal disables gates 758B and 758C to prevent the F505Q signal from being output as the F510 CAS signal from gate 758E and to prevent the F506Q signal from being output as the F511 RAS signal from gate 758F. The run, refresh, and write modes are assured of starting without contention and of being completed without contention. As discussed above; the refresh, write, and run modes are mutually exclusive and are separated by guardbands. Hence, they do not have contention during operations. Further; the CAS and RAS flip-flops for the refresh, write, and run modes are initialized before starting the modes to insure proper startup. For example, the gray code counter (Fig 7G) is initialized by the signal from gate 756T prior to starting a write cycle and is initialized by the signal from gate 756R prior to starting a refresh operation. Also, the deteOor can be initialized to a re-addressing operation, such as with
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the RUN signal U13A-8 to the SET* input of flip-flop K1 (Fig 6W), to insure that the memory is properly RAS addressed at the beginning of a scanline when entering the run mode. Still further, the CAS flip-flop 756D and the RAS flip-flop 757D can be set with the RUN signal, similar to the setting of the deteOor flip- flop Kl (Fig 6W) with the RUN signal U13A-8 to the SET* input and similar to the setting of the gray code counter (Fig 7G) with the F505S signal, in a configuration where it is desired to start run mode operations at the 721H operating point (Fig 7B). Further, the refresh and write cycles are assured of being completed without interruption because the CLS signal controlling the maximum length of the refresh period and the DOA7 signal controlling the maximum length of the write period are much longer than the refresh and write cycles, respeOively; because the U22E counter insures that the multiple refresh cycles will be completed before terminating the refresh operation; and because the gray code counter insures that the write cycle will be completed before terminating the write cycle. Similarly, the RAS and CAS logic for the run mode (Fig 7E) insures that the RAS and CAS cycles will be properly cycled. Further, the run mode is implemented as a read only mode and hence interruption of a run mode RAS or CAS cycle will only affeO reading of a parameter which is at the end of a scanline and hence of no praαical consequence. Output strobe operations will now be discussed for memory controller configuration-1 relative to Fig 7F. Output strobe operations can be invoked during various conditions, such as during the three modes listed and discussed below. 1) The run mode. 2) The computer write mode. 3) The refresh mode. There is no contention between these three modes because they are mutually exclusive and because the present implementation has a built in guardband (extra time) separating the different modes supra. During the run mode, the output strobe signal is the complement of the CAS* signal (Figs 7A and 7B). Two conditions need be considered. 1) The end of the re-addressing operation (Fig 7B). 2) The start of the fast page operation (Fig 7B). At the end of the re-addressing operation 721J (Fig 7B), an output strobe is generated to load the pixel accessed with the RAS/CAS re-addressing operation into the output register. This is achieved by gating the proper (F500B*)(F500Q clock phase with the delayed second re-addressing phase (U21 B-2). The delayed second re-addressing phase is generated by the flip-flops 760D and
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760E delaying the U21 B-2 signal to gate 760C (Fig 7F). The output strobe is invoked at the end of the re-addressing operation instead of at the beginning of the fast page mode scanout to cover an alternate configuration where multiple re-addressing operations might occur in sequence and hence each re-addressing operation should be self contained. However, such multiple re-addressing operations cannot occur in configuration-1 supra. It should be noted that the last output strobe (in a fast page mode immediately before a re-addressing operation) is generated even though a simultaneously generated CAS negative edge may be disabled. This is because this last output strobe is used to strobe the pixel accessed with the last CAS negative edge. The output strobes correspond to the prior CAS access, not the simultaneously generated CAS access. At the start of the fast page internal scanout operation following a re- addressing operation, the first output strobe 721M is disabled because the last accessed pixel (during the re-addressing operation) has already been strobed into the output register. This can be achieved by stretching the gate (deteOor) signal U14A-6 (Fig 6C) with flip-flop 760E to deteO the first output strobe following a re-addressing operation for disabling of this first output strobe. The output strobe is enabled for read operations, which occur during the run mode but not during the refresh mode or the write mode. Hence, the output strobe is enabled with the run mode signal U13A-8. For all read operations except for re-addressing (the fast page scanout), the output strobe is shown as an inverted CAS* signal with an aαive positive edge at the same time as the CAS* aOive negative edge. This is because the data out is stable for the prior CAS* operation when the next CAS* operation is initiated with the negative going CAS edge. Hence, the output strobe is offset one CAS* cycle. The output strobe immediately before a RAS* cycle is the output strobe for the immediately prior CAS* cycle. For the re-addressing read operation (the non-fast page scanout), the output strobe is also shown as an inverted CAS* signal with an aOive positive edge at the same time as the CAS* aOive negative edge would occur (F500B* AND F500Q. In contrast to the fast page scanout operations, the read re-addressing output strobe and the C/ S* signal are shown as being mutually exclusive (not occurring together) 721J and 721 M. Output strobe generation will now be discussed in greater detail with referenced to Fig 7F. During the run mode, the output strobe signal can be generated for internal scanout operations (Fig 7A) and for internal scanout and re-addressing operations
SϋB
(Fig 7B). The output strobe signal can be generated by properly setting and resetting the output strobe flip-flop 760A. One setting of the output strobe flip- flop is enabled by the RUN signal U13A-8 and by the DOA6 signal, as discussed for clock signals U12A-6 and U12A-8 (Fig 6Q. This insures that output strobes will not be generated at other times, such as during the write mode and the refresh mode. The output strobe signal is controlled to follow the F500B* AND F500C signal condition (Fig 7A); except that this sequence is interrupted during the RAS re-addressing operation (Fig 7B); by being clocked low by the F500B AND F500C signal from gate 760C and being clocked high by the F500B* AND F500C signal from gate 760B (in reverse of the CAS logic supra). Because the DRAM output strobe operation is invoked by the positive going edge of the output strobe signal, the set input to the output strobe flip-flop 760A may be considered to be more important than the reset input is to the output strobe flip- flop. Fig 7A run mode output strobe signal generation will now be discussed. During the run mode and for the condition that deteOor signal U14A-6 is high (indicative of internal scanout operations), the output strobe signal follows the (F500B*)(F500Q clock phases. The output strobe flip-flop 760A can be reset by the F500A clock signal clocking the F500B AND F500C signal from gate 760C into the output strobe flip-flop 760A just before the F500B signal is clocked to go low in the middle of the F500C clock pulse period when the F500C clock pulse is high (F500B AND F500O. The output strobe flip-flop can be set by the F500A clock signal clocking the F500B signal from gate 760B into the output strobe flip-flop 760A just before the F500B signal is clocked to go high at the end of the F500C clock pulse period when the F500C clock pulse is high and going low (F500B AND F500C*). Fig 7B run mode output strobe signal generation will now be discussed. During the run mode and for the condition that the deteOor signal U23C-10 is high (indicative of the re-addressing operation) and in addition to the Fig 7A conditions; two additional conditions need be to be considered. 1) The re-addressing operation (Fig 7B). 2) The start of the internal scanout operation (Fig 7B). The output strobe signal can be kept from going low during the re-addressing operation until the end of the deteOor signal U23C-10 721 J by disabling the reset input signal from gate 760C with the U21 B-5 signal through an inverter. The output strobe signal can be kept from going low at the start of the internal scanout operation 721 M by delaying the U21 B-2 signal for two CPD (or CPE or
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F500Q clock periods through flip-flops 760D and 760E to disable the output strobe flip-flop from being reset with this delayed U21 B-2 signal to gate 760C through an inverter. The configuration-1 controller disclosed herein illustrates the features of the present invention to one skilled in the art. It will be readily recognized that high speed logical circuits may need tuning; such as varying the clock oscillator frequency, adjusting propagation delays, using one-shot circuits and delay lines to generate pulses and to delay pulses, etc. Propagation delays can be adjusted by seleαing circuits having the desired speeds, using RC networks to slow down signals, using 74AS04 and 74AS08 circuits in signal lines to increase propagation delays, etc.
MISCELLANEOUS CONSIDERATIONS Assignment Of Memory Addresses Various arrangements are discussed herein that obtain particular advantages when operations are concentrated within a block of memory and when re- addressing between blocks of memory is reduced. In many applications, proper assignment of memory addresses facilitates such reduαion of re-addressing operations. Various methods of assigning addresses in accordance with the present invention will now be discussed. A software programming package, such as an assembler or compiler, is typically used for assigning of addresses for instruαions and for data in a stored program computer system. Hence, such a software programming package can be programmed to assign addresses for instruOions and for data in an optimum manner in accordance with the present invention. For example, routines of instruOions can be assigned addresses within a block of memory that minimizes re-addressing operations. Iterative routines of instruαions can be assigned addresses within a block of memory so that the iterative operations minimize iterating back and forth and back and forth across blocks of memory. Subroutines can be assigned addresses within a block of memory so that the subroutine operations minimize changing blocks of memory. Operands can be stored in the same block of memory with the accessing instruOions so that re- addressing is not necessary for operand accessing or storage. Transfer addresses can be assigned to the same block of memory, where for example a transfer instruOion or a subroutine call instruOion can be placed in the same block of memory as the transfer address or the subroutine address, respeαively.
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APPLICATIONS IntroduOion The teachings of the present invention can provide substantial advantages in many different types of systems. These systems include display systems, television systems, database memory systems, array processor systems, signal processor systems, filter systems, stored program computer systems, DMA systems, cache memory systems, artificial intelligence systems, and others. Such systems are disclosed in significant detail in the related patent applications. The display (including television), filter, array, database, DMA, and stored program computer systems are disclosed in further detail below. The teachings of the present invention can provide substantial advantages in many different types of memories. These memories include image memories, array memories, computer main memories, scratch pad memories, first-in first- out (FIFO) memories, cache memories, pipeline memories, buffer memories, and other memories. Such memories are disclosed in further detail below. Also, various types of memories are disclosed in significant detail in the related patent applications. The display system includes loading of address registers from a supervisory computer and updating of address registers by adding delta parameters thereto: which is similar to a stored program computer loading an address register with a transfer address and updating of an address register with a program counter; or an array processor, signal processor, or filter processor loading an address register with a start address and updating of an address register with an array address sequencer; or a DMA controller loading an address register with a start address and incrementing of an address register; or a database loading an address register with a start address and incrementing of an address register with a database address sequencer; or a cache memory controller loading an address register with a start address and incrementing of an address register; or an artificial intelligence processor loading an address register with a start address and updating of an address register with an array address sequencer; The display system includes scanout of display information: which is similar to a stored program computer scanning out information to a hard disk memory; or an array processor, signal processor, or filter processor memory scanning out information to be processed; or an artificial intelligence processor scanning out information to be processed; or a DMA controller memory scanning out information to load into a hard disk memory; or a cache memory controller scanning out information to load into a hard disk memory; or a database memory scanning out information to be relationally processed.
Perspeαive The computer industry is heavily dependent on DRAMs. Computers, laser printers, and other computer type products are currently memory-intensive. This memory-intensiveness is increasing at a significant rate. Even consumer TVs and VCRs are becoming significant users of DRAMs. Further, the memory requirements tend towards speed-intensive (higher bandwidth) memories. Hence, the trends are towards more speed-intensive memories in more memory- intensive systems. The clock rates of micro processors are presently high and are increasing. Although DRAMs are relatively low in cost, they are also relatively slow. Some small increase in DRAM speed can be obtained at increased cost; such as specifying higher cost 80ns DRAMs instead of lower cost 100ns DRAMs. More commonly, "wait states" are implemented to slow down the computer to the lower speed of the less expensive DRAMs. As a partial solution, higher speed computers are implemented with cache memories to compensate for the low DRAM speed. However, cache memories have disadvantages; such as increasing system costs, increasing the chip count, causing software incompatibilities, low tolerance to dispersed addressing, and "cache thrashing". A cache memory algorithm tries to guess what information stored in main memory will be needed by the processor. Cache thrashing is an effeα where the cache memory tries to deal with multiple small tasks, resulting in rapid loading and purging of cache memory, which causes the computer to perform slower than the same computer without cache memory. Ideally, if a high speed main memory were available and affordable, the program would be main memory resident and the processor would direOly access the main memory without the use of a cache memory; thereby eliminating the cache memory guessing game and eliminating detrimental effects, such as cache thrashing. The DRAM performance enhancement technology (the DPE technology) of the present invention, significantly increases memory performance without increasing cost. Speed improvements of the order of 300% can be achieved. There is no penalty for this performance enhancement; neither price, nor reliability, nor component standardization, nor addressing flexibility. The DPE technology does not clock the DRAMs any faster, it utilizes the DRAMs more efficiently. It rigidly adheres to DRAM specifications and to established worst case design praαices. It uses commercially available standard DRAM components. It uses features that are explicit in the DRAM industry standards. Hence, it will be as applicable to the new generations of 16-megabit
and 64-megabit DRAMs as it is to the current 1 -megabit and 4-megabit DRAMs. The changes are in the DPE memory architeαure, without requiring higher clock rates and without requiring special DRAM components. The DPE technology facilitates both, lower costs and higher performance. The DPE technology reduces the need for cache memories, but it is compatible with cache memories and can be implemented with cache memories or in cache memory form for even further performance enhancements. Examples of DPE applications are provided below. Medium speed Personal Computers (PCs) currently use higher speed DRAMs and often require "wait states". When implemented with the DPE technology, such medium speed PCs can use lower speed DRAMs without the need for "wait states". This achieves the combination of lower cost (lower speed DRAMs cost less) and higher performance (elimination of "wait states" increases performance). High speed PCs currently use higher speed DRAMs and often use cache memories or "wait states". When implemented with the DPE technology, such high speed PCs can use lower speed DRAMs without the need for "wait states" or cache memories. This lowers costs (elimination of cache memory and reduced DRAM speed requirements) and increases performance (the computer main memory now has higher performance) and further enhances software compatibility that is degraded when a cache memory is used. Multiported DRAM systems using the DPE technology can further enhance system performance. Computer systems are conventionally configured with memories having a computer memory port and various DMA memory ports. When a DMA port is using the memory, such as loading information from a hard disk; the computer is typically placed on hold to avoid contention for the memory. This reduces computer performance. With the DPE technology, the main memory can economically be implemented to be fast enough to support concurrent and interspersed memory read/write operations by the computer and by the DMA channel. The performance enhancement of the DPE technology is not degraded by concurrent use of different regions of memory by the computer and by DMA channels. For example, the memory address can be continually multiplexed between instruαion addresses, operand addresses, and various DMA addresses without degrading the enhanced DPE performance. Performance can be further enhanced (above the current 300% enhancement) and DRAM component manufaOuring costs can be reduced by designing a custom DRAM component to optimize the DPE technology. A computer implemented with the DPE technology can be called the
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"credit card computer™" because it is a high speed "cache-less computer™"
Television Applications The features of the present invention are also particularly advantageous for television configurations. A television system may involve a frame buffer and a display processor; such as for scan conversion and for transforming, filtering, and otherwise processing a television image. A memory or a hierarchy of memories can be used to implement the television system; such as a frame buffer memory implemented with DRAMs or CCDs for temporarily storing a frame of television image. The multi-dimensional arrangement discussed in the context of a display processor having an X addressing dimension and a Y addressing dimension is particularly pertinent to a television system. Particular advantage can be obtained in a television frame buffer by storing image information in a memory map form so that adjacent pixels on the screen are stored in the same memory block to the degree reasonably permitted. Similarly, particular advantage can be obtained in a television frame buffer by storing image information in a memory map form so that pixels in the same scanline on the screen are stored in the same memory block to the degree reasonably permitted. A television system can be implemented with an image memory for storing image information, an address register for generating image memory addresses, a memory refresh deteOor for generating a memory refresh deteOor signal to invoke memory refresh operations, a memory scanout deteOor for generating a memory scanout deteαor signal to invoke memory scanout operations, and a memory re-addressing deteαor for generating a memory re-addressing deteαor signal to invoke memory re-addressing operations. These features of the present invention may be used separately or in combinations and may be implemented with the various alternate configurations disclosed herein and disclosed in the related patent applications and may be implemented with many other configurations that will now become apparent to one skilled in the art from the teachings herein. For example, a television image memory can be implemented with the memories discussed herein for any one or combination thereof; such as in Figs 6E to 6N, Figs 4F to 4K, DRAM configuration-!, or others disclosed herein: a television image memory address register can be implemented with the address registers discussed herein for any one or combination thereof; such as in Figs 60 to 6R, Figs 4B to 4G, DRAM configuration-1 , or others disclosed herein: a memory refresh deteOor can be implemented with the memory refresh
deteOors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory refresh deteOor circuits (i.e., a sync pulse refresh deteOor circuit) or others disclosed herein: memory scanout and re-addressing deteαors can be implemented with the memory scanout and re- addressing deteOors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory addressing deteOor circuits (i.e., an address overflow deteOor shown in Fig 6C or an address comparitor deteOor shown in Figs 4D and 4E) or others disclosed herein. Read operations, write operations, and read-modify-write operations; such as having scanout and re-addressing in accordance with the present invention; are particularly pertinent for a television system. Read operations can be used to scanout image memory or the frame buffer for refreshing the display monitor. Write operations can be used for loading image memory or the frame buffer with a new frame of information. Read-modify-write operations can be used for processing the image in image memory or the frame buffer, such as for filtering the image or otherwise processing the image.
Database Processor Applications The features of the present invention are also particularly advantageous for database processor configurations. A database processor typically processes information stored in a database memory, such as for relational database operations. A memory or a hierarchy of memories can be used to implement the database memory system; such as a main database memory implemented on a disk memory and a database buffer or cache memory (i.e., implemented with DRAMs) for temporarily buffering database information accessed from the disk memory, or such as a main database memory implemented with DRAMs, or such as a main database memory implemented with CCDs and a database buffer or cache memory (i.e., implemented with DRAMs) for temporarily buffering database information accessed from the CCD memory. A relational database can be implemented using the memory of the present invention. One configuration of a relational database includes a relational processor that searches the database for particular information. The relational database system can be implemented with DRAMs. For example, the main database memory can be implemented with DRAMs, a buffer or cache memory can be implemented with DRAMs, and/or other parts of the system can be implemented with DRAMs supra. The relational processor searches the database information to attempt to find a match with the reference information. The searching process involves multitudes of memory accesses and comparisons.
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The memory accesses typically involve information stored in close proximity, such as related information stored in the same block of memory. Accessing of information stored in the same block can be performed with the scanout operation discussed herein. Accessing of information stored in different blocks can be performed with combinations of the scanout and re-addressing operations discussed herein. Particular advantage can be obtained in a database memory system by storing database information that is related and is to be accessed substantially together in the same block of memory in order to maximize higher speed scanout operations and to minimize lower speed re-addressing operations. A database system ~an be implemented with a database memory for storing database information, an address register for generating database memory addresses, a memory refresh deteOor for generating a memory refresh deteαor signal to invoke memory refresh operations, a memory scanout deteOor for generating a memory scanout deteOor signal to invoke memory scanout operations, and a memory re-addressing deteαor for generating a memory re- addressing deteαor signal to invoke memory re-addressing operations. These features of the present invention may be used separately or in combinations and may be implemented with the various alternate configurations disclosed herein and disclosed in the related patent applications and may be implemented with many other configurations that will now become apparent to one skilled in the art from the teachings herein. For example, a database memory can be implemented with the memories discussed herein for any one or combination thereof; such as in Figs 6E to 6N, Figs 4F to 4K, DRAM configuration-1, or others disclosed herein: a database memory address register can be implemented with the address registers discussed herein for any one or combination thereof; such as in Figs 60 to 6R, Figs 4B to 4G, DRAM configuration-!, or others disclosed herein: a memory refresh deteαor can be implemented with the memory refresh deteOors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory refresh deteOor circuits (i.e., a time available refresh deteOor circuit) or others disclosed herein: memory scanout and re-addressing deteOors can be implemented with the memory scanout and re-addressing deteOors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory addressing deteOor circuits (i.e., an address overflow deteOor shown in Fig 6C or an address comparitor deteαor shown in Figs 4D and 4E) or others disclosed herein. Read operations, write operations, and read-modify-write operations; such as having scanout and re-addressing in accordance with the present invention; are
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particularly pertinent for a database memory system. Read operations can be used to scanout the database memory for loading a cache memory or a buffer memory or for relational processing. Write operations can be used for writing into a cache memory or a buffer memory or for writing new database information into the database memory. Read-modify-write operations can be used for processing the information in a cache memory, in a buffer memory, or in the database memory; such as for sorting the database information or otherwise processing the database information.
Array Processor Applications The features of the present invention are also particularly advantageous for array processor configurations. An array processor typically processes arrays of numbers; such as for filter processing disclosed in related Patent No. 4,209,843. A memory or a hierarchy of memories can be used to implement the array processor system; such as a main array memory implemented on a disk memory and an array buffer or cache memory (i.e., implemented with DRAMs) for temporarily buffering array information accessed from the disk memory, or such as a main array memory implemented with DRAMs, or such as a main array memory implemented with CCDs and an array buffer or cache memory (i.e., implemented with DRAMs) for temporarily buffering array information accessed from the CCD memory. The multi-dimensional arrangement discussed in the context of a display processor having an X addressing dimension and a Y addressing dimension is particularly pertinent to a two dimensional array processor for processing a two dimensional array of information. A multi-dimensional arrangement is also applicable to an array processor having a multi-dimensional array of information to be processed. The display processor previously discussed may be considered to be a type of array processor that processes an array of pixels. An array processor memory can be implemented using the memory features of the present invention. One configuration of an array processing system includes an array processor that processes arrays of numbers stored in a main array memory. The array processor system can be implemented with DRAMs. For example, the main array memory can be implemented with DRAMs, a buffer or cache memory can be implemented with DRAMs, and/or other parts of the system can be implemented with DRAMs supra. The array processor accesses, processes, and restores the array information. The array processing involves multitudes of memory accesses and restores; typically involving information stored in close proximity, such as related information stored in the same block of
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memory. Accessing of information stored in the same block can be performed with the scanout operation discussed herein. Accessing of information stored in different blocks can be performed with combinations of the scanout and re- addressing operations discussed herein. Particular advantage can be obtained in an array processor system by storing array information that is related and is to be accessed substantially together in the same block of memory in order to maximize higher speed scanout operations and to minimize lower speed re-addressing operations. An array system can be implemented with an array memory for storing array information, an address register for generating array memory addresses, a memory refresh deteαor for generating a memory refresh deteOor signal to invoke memory refresh operations, a memory scanout deteOor for generating a memory scanout deteOor signal to invoke memory scanout operations, and a memory re-addressing deteαor for generating a memory re-addressing deteαor signal to invoke memory re-addressing operations. These features of the present invention may be used separately or in combinations and may be implemented with the various alternate configurations disclosed herein and disclosed in the related patent applications and may be implemented with many other configurations that will now become apparent to one skilled in the art from the teachings herein. For example, an array memory can be implemented with the memories discussed herein for any one or combination thereof; such as in Figs 6E to 6N, Figs 4F to 4K, DRAM configuration-1 , or others disclosed herein: an array memory address register can be implemented with the address registers discussed herein for any one or combination thereof; such as in Figs 60 to 6R, Figs 4B to 4G, DRAM configuration-!, or others disclosed herein: a memory refresh deteαor can be implemented with the memory refresh deteOors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory refresh deteαor circuits (i.e., a time available refresh deteOor circuit) or others disclosed herein: memory scanout and re- addressing deteOors can be implemented with the memory scanout and re- addressing deteαors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory addressing deteOor circuits (i.e., an address overflow deteOor shown in Fig 6C or an address comparitor deteαor shown in Figs 4D and 4E) or others disclosed herein. Read operations, write operations, and read-modify-write operations; such as having scanout and re-addressing in accordance with the present invention; are particularly pertinent for array processor system. Read operations can be used to scanout the array memory for loading a cache memory or a buffer memory or for
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array processing. Write operations can be used for writing into a cache memory or a buffer memory or for writing new array information into the array memory. Read-modify-write operations can be used for processing the array information in a cache memory, in a buffer memory, or in the array memory; such as for array processing of the information or otherwise processing the array information. Particularly efficient configurations can be implemented for array processing applications. For example; image processing, graphic processing, transform processing, and correlation and convolution processing can be implemented with arrays of data in regular arrays that lends itself to efficient memory enhancement configurations. FFT configurations having special addressing requirements can be implemented more efficiently with special configurations of memory blocks and memories to address array parameters with a minimum of re-addresssing. Such configurations typically process arrays of numbers having close relationships therebetween. Hence, such configurations enhance scanout and reduce re-addressing yielding particularly efficient memory operation.
Signal Processing Applications The features of the present invention are also particularly advantageous for signal processing configurations. A signal processor typically processes digitized signals; such as seismic signals discussed in related Patent No. 4,209,843. A memory or a hierarchy of memories can be used to implement the signal processing system; such as a main signal processing memory implemented on a disk memory and buffer or cache memory (i.e., implemented with DRAMs) for temporarily buffering signal processing information accessed from the disk memory, or such as a main signal processing memory implemented with DRAMs, or such as a main signal processing memory implemented with CCDs and a signal processing buffer or cache memory (i.e., implemented with DRAMs) for temporarily buffering signal processing information accessed from the CCD memory. Signal processing information can include input signal samples to be processed and output signal samples that have been processed. The multi-dimensional arrangement discussed in the context of a display processor having an X addressing dimension and a Y addressing dimension is particularly pertinent to a two dimensional signal processor for processing two dimensional information. A multi-dimensional arrangement is also applicable to a signal processor having multi-dimensional signal processing information to be processed. A signal processor memory can be implemented using the memory features
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of the present invention. One configuration of a signal processing system includes a signal processor that processes information stored in a main memory. The signal processing system can be implementec with DRAMs. For example, the main memory can be implemented with DRAMs, a buffer or cache memory can be implemented with DRAMs, and/or other parts of the system can be implemented with DRAMs supra. The signal processor accesses, processes, and restores the signal information. The signal processing involves multitudes of memory accesses and restores; typically involving information stored in close proximity, such as related information stored in the same block of memory. Accessing of signal processing information stored in the same block can be performed with the scanout operation discussed herein. Accessing of signal processing information stored in different blocks can be performed with combinations of the scanout and re-addressing operations discussed herein. Particular advantage can be obtained in a signal processing system by storing signal processing information that is related and is to be accessed substantially together in the same block of memory in order to maximize higher speed scanout operations and to minimize lower speed re-addressing operations. A signal processing system can be implemented with a signal sample memory for storing signal samples, an address register for generating signal sample memory addresses, a memory refresh deteαor for generating a memory refresh deteOor signal to invoke memory refresh operations, a memory scanout deteαor for generating a memory scanout deteαor signal to invoke memory scanout operations, and a memory re-addressing deteαor for generating a memory re- addressing deteOor signal to invoke memory re-addressing operations. These features of the present invention may be used separately or in combinations and may be implemented with the various alternate configurations disclosed herein and disclosed in the related patent applications and may be implemented with many other configurations that will now become apparent to one skilled in the art trom the teachings herein. For example, a signal sample memory can be implemented with the memories discussed herein for any one or combination thereof; such as in Figs 6E to 6N, Figs 4F to 4K, DRAM configuration-1, or others disclosed herein: a signal sample memory address register can be implemented with the address registers discussed herein for any one or combination thereof; such as in Figs 60 to 6R, Figs 4C to 4G, DRAM configuration-! , or others disclosed herein: a memory refresh deteOor can be implemented with the memory refresh deteOors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory refresh deteαor circuits (i.e., a time available refresh deteOor circuit) or others disclosed herein:
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memory scanout and re-addressing deteαcrs can be implemented with the memory scanout and re-addressing deteOors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory addressing deteαor circuits (i.e., an address overflow deteOor shown in Fig 6C or an address comparitor deteαor shown in Figs 4D and 4E) or others disclosed herein. Read operations, write operations, and read-modify-write operations; such as having scanout and re-addressing in accordance with the present invention; are particularly pertinent for a signal processor system. Read operations can be used to scanout the signal memory for loading a cache memory or a buffer memory or for signal processing. Write operations can be used for writing into a cache memory or a buffer memory or for writing new signal information into the signal memory. Read-modify-write operations can be used for processing the signal information in a cache memory, in a buffer memory, or in the signal memory; such as for signal processing of the information or otherwise processing the signal information.
Filter Processor Applications The features of the present invention are also particularly advantageous for filter processor configurations. A filter processor typically processes arrays of numbers; such as discussed in related Patent No. 4,209,843. A memory or a hierarchy of memories can be used to implement the filter processor system; such as a main filter memory implemented on a disk memory and buffer or cache memory (i.e., implemented with DRAMs) for temporarily buffering filter information accessed from the disk memory, or such as a main filter memory implemented with DRAMs, or such as a main filter memory implemented with CCDs and a filter buffer or cache memory (i.e., implemented with DRAMs) for temporarily buffering filter information accessed from the CCD memory. Filter information can include input signal samples to be filtered, reference signal samples to be used in the filtering, and output signal samples that have been filtered. The multi-dimensional arrangement discussed in the context of a display processor having an X addressing dimension and a Y addressing dimension is particularly pertinent to a two dimensional filter processor for processing two dimensional information. A multi-dimensional arrangement is also applicable to a filter processor having multi-dimensional filter information to be processed. A filter processor memory can be implemented using the memory features of the present invention. One configuration of a filter processing system includes a
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filter processor that processes information to be filtered stored in a main filter memory. The filter processor system can be implemented with DRAMs. For example, the main filter memory can be implemented with DRAMs, a buffer or cache memory can be implemented with DRAMs, and/or other parts of the system can be implemented with DRAMs supra. The filter processor accesses, processes, and restores the filter information. The filter processing involves multitudes of memory accesses and restores; typically involving information stored in close proximity, such as related information stored in the same block of memory. Accessing of filter information stored in the same block can be performed with the scanout operation discussed herein. Accessing of filter information stored in different blocks can be performed with combinations of the scanout and re-addressing operations discussed herein. Particular advantage can be obtained in a filter processor system by storing filter information that is related and is to be accessed substantially together in the same block of memory in order to maximize higher speed scanout operations and to minimize lower speed re-addressing operations. A filter processing system can be implemented with a filter sample memory for storing filter samples, an address register for generating filter sample memory addresses, a memory refresh deteOor for generating a memory refresh deteOor signal to invoke memory refresh operations, a memory scanout deteOor for generating a memory scanout deteOor signal to invoke memory scanout operations, and a memory re-addressing deteαor for generating a memory re- addressing deteOor signal to invoke memory re-addressing operations. These features of the present invention may be used separately or in combinations and may be implemented with the various alternate configurations disclosed herein and disclosed in the related patent applications and may be implemented with many other configurations that will now become apparent to one skilled in the art from the teachings herein. For example, a filter sample memory can be implemented with the memories discussed herein for any one or combination thereof; such as in Figs 6E to 6N, Figs 4F to 4K, DRAM configuration-1 , or others disclosed herein: a filter sample memory address register can be implemented with the address registers discussed herein for any one or combination thereof; such as in Figs 60 to 6R, Figs 4B to 4G, DRAM configuration-!, or others disclosed herein: a memory refresh deteαor can be implemented with the memory refresh deteOors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory refresh deteOor circuits (i.e., a time available refresh deteαor circuit) or others disclosed herein: memory scanout and re-addressing deteαors can be implemented with the
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memory scanout and re-addressing deteOors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory addressing deteαor circuits (i.e., an address overflow deteOor shown in Fig 6C or an address comparitor deteOor shown in Figs 4D and 4E) or others disclosed herein. Read operations, write operations, and read-modify-write operations; such as having scanout and re-addressing in accordance with the present invention; are particularly pertinent for filter processor systems. Read operations can be used to scanout the filter memory for loading a cache memory or a buffer memory or for filter processing. Write operations can be used for writing into a cache memory or a buffer memory or for writing new filter information into the filter memory. Read-modify-write operations can be used for processing the filter information in a cache memory, in a buffer memory, or in the filter memory; such as for filter processing of the information or otherwise processing the filter information. The memory features of the present invention can be readily praαiced with a filter system, such as the filter system of related Patent No. 4,209,843. This filter system application is also representative of other applications; such as an array processor, signal processor, DMA processor, and database processor system applications. A disclosure of filter processor applications in accordance with the present invention will now be discussed with reference to Fig 6D therein ("therein" meaning in said related Patent No. 4,209,843). Z-RAM 614 may be a RAM in accordance with the present invention, such as a Mitsubishi RAM or a Toshiba RAM as discussed herein. Also, P-RAM 625 may be implemented with a ROM in accordance with the present invention or alternately P-RAM 625 may be implemented with a RAM in accordance with the present invention, such as with a Mitsubishi RAM or with a Toshiba RAM as discussed herein. Although the filter processor discussed with reference to said Fig 6D is shown as a single bit filter processor, alternate multi-bit configurations are also disclosed therein. The number of bits per word, or per sample, or per memory address can be varied from 1-bit to 32-bits or more as disclosed herein. The arrangement shown in Fig 6D of said Patent No. 4,209,843 will now be compared with reference to Fig 4B relative to implementation of memory 614. Z-RAM 614 generating output signals ZK in response to address signals K from address generator 619 therein can be implemented as memory 222 generating memory output signals 223 in response to address signals 219 herein. Filter processor including counter 613, multiplier 626, and associated logic therein
•HE^ su«* i tvnJ e
can be implemented as processor 216 herein. Deteαor 220 herein can be added to the system of said Fig 6D therein, such as for deteOing a change in the address MSBs from address generator 619 therein and invoking a delay, such as by gating the clock C to C-counter 616. The arrangement shown in Fig 6D of said Patent No. 4,209,843 will now be compared with reference to Fig 4B herein relative to implementation of memory 625; which is shown implemented as a ROM and alternately can be implemented as a RAM or other memory. P-ROM 625 generating output signals PJO in response to address signals J from address generator 617 therein can be implemented as memory 222 generating memory output signals 223 in response to address signals 219 herein. Filter processor including counter 613, multiplier 626, and associated logic therein can be implemented as processor 216 herein. DeteOor 220 herein can be added to the system of said Fig 6D therein, such as for deteαing a change in the address MSBs from address generator 617 therein and invoking a delay, such as by gating the clock C to C-counter 616. The sequential nature of the addressing to memory 614 and memory 625 therein facilitates the scanout and re-addressing features of the present invention. For example, in a single dimensional configuration in accordance with Fig 4G herein having incremental counter addressing in accordance with Fig 6D therein; an array of 1024 filter samples, based upon a 10-bit column address, can be processed in the scanout mode of operation before a re-addressing operation need be invoked. Alternately, non-incremental addressing may be implemented. In either incremental or non-incremental addressing configuration; filter processing that does not need to move between different blocks of memory, such as with all data being maintained within one block of memory, has increased performance because of reduced need for re-addressing operations; filter processing that does not often need to move between different blocks of memory, such as with all data being maintained within a few blocks of memory, has slightly lower performance compared to the above example because of a slightly increased need for re-addressing operations; and filter processing that more often needs to move between different blocks of memory, such as with data being distributed over many blocks of memory, has further reduced performance compared to the above examples because of an increased need for re-addressing operations. Consequently, it is desirable to configure the system to maximize scanout operations and to minimize re-addressing operations. The arrangement shown in Fig 10E of said Patent No. 4,209,843 will now be compared with reference to Fig 4B herein relative to implementation of
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memories 1010, 1011, and 1018. Memories 1010, 1011, and 1018 generating output signals 1013, 1012, and 1016 respeαively in response to address signals from an address generator therein can be implemented as memory 222 generating memory output signals 223 in response to address signals 219 herein. Filter processor including multiplier 1014 and summer 1017 therein can be implemented as processor 216 herein. Deteαor 220 herein can be added to the system of said Fig 10E therein, such as for deteOing a change in the address MSBs from the address generator therein and invoking a delay. The other disclosures in said Patent No. 4,209,843 can also be implemented in accordance with the teachings in the present invention.
Artificial Intelligence Processor Applications The features of the present invention are also particularly advantageous for artificial intelligence processor configurations. An artificial intelligence processor typically processes inferences. A memory or a hierarchy of memories can be used to implement the artificial intelligence processor system; such as a main artificial intelligence memory implemented on a disk memory and buffer or cache memory (i.e., implemented with DRAMs) for temporarily buffering artificial intelligence information accessed from the disk memory, or such as a main artificial intelligence memory implemented with DRAMs, or such as a main artificial intelligence memory implemented with CCDs and a artificial intelligence buffer or cache memory (i.e., implemented with DRAMs) for temporarily buffering artificial intelligence information accessed from the CCD memory. Artificial intelligence information can include inference information to be processed. An artificial intelligence processor memory can be implemented using the memory features of the present invention. One configuration of a artificial intelligence processing system includes a artificial intelligence processor that processes information stored in a main artificial intelligence memory. The artificial intelligence processor system can be implemented with DRAMs. For example, the main artificial intelligence memory can be implemented with DRAMs, a buffer or cache memory can be implemented with DRAMs, and/or other parts of the system can be implemented with DRAMs supra. The artificial intelligence processor accesses and processes the artificial intelligence information. Accessing of artificial intelligence information stored in the same block can be performed with the scanout operation discussed herein. Accessing of artificial intelligence information stored in different blocks can be performed with combinations of the scanout and re-addressing operations discussed herein.
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Particular advantage can be obtained in an artificial intelligence processor system by storing artificial intelligence information that is related and is to be accessed substantially together in the same block of memory in order to maximize higher speed scanout operations and to minimize lower speed re- addressing operations. An artificial intelligence processing system can be implemented with an artificial intelligence memory for storing artificial intelligence information, an address register for generating artificial intelligence memory addresses, a memory refresh deteOor for generating a memory refresh deteOor signal to invoke memory refresh operations, a memory scanout deteOor for generating a memory scanout deteOor signal to invoke memory scanout operations, and a memory re-addressing deteαor for generating a memory re-addressing deteαor signal to invoke memory re-addressing operations. These features of the present invention may be used separately or in combinations and may be implemented with the various alternate configurations disclosed herein and disclosed in the related patent applications and may be implemented with many other configurations that will now become apparent to one skilled in the art from the teachings herein. For example, an artificial intelligence memory can be implemented with the memories discussed herein for any one or combination thereof; such as in Figs 6E to 6N, Figs 4F to 4K, DRAM configuration-1 , or others disclosed herein: an artificial intelligence memory address register can be implemented with the address registers discussed herein for any one or combination thereof; such as in Figs 60 to 6R, Figs 4C to 4G, DRAM configuration-1 , or others disclosed herein: a memory refresh deteOor can be implemented with the memory refresh deteOors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory refresh deteαor circuits (i.e., a time available refresh deteαor circuit) or others disclosed herein: memory scanout and re-addressing deteαors can be implemented with the memory scanout and re-addressing deteOors discussed herein for any one or combination thereof; such as disclosed in the section herein direOed to memory addressing deteOor circuits (i.e., an address overflow deteOor shown in Fig 6C or an address comparitor deteOor shown in Figs 4D and 4E) or others disclosed herein. Read operations, write operations, and read-modify-write operations; such as having scanout and re-addressing in accordance with the present invention; are particularly pertinent for artificial intelligence processor systems. Read operations can be used to scanout the artificial intelligence memory for loading a cache memory or a buffer memory or for artificial intelligence processing. Write
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operations can be used for writing into a cache memory or a buffer memory or for writing new artificial intelligence information into the artificial intelligence memory. Read-modify-write operations can be used for processing the artificial intelligence information in a cache memory, in a buffer memory, or in the artificial intelligence memory; such as for artificial intelligence processing of the information or otherwise processing the artificial intelligence information. The sequential nature of the addressing to memory 614 and memory 625 therein facilitates the scanout and re-addressing features of the present invention. For example, in a single dimensional configuration in accordance with Fig 4G herein having incremental counter addressing in accordance with Fig 6D therein; an array of 1024 inference parameters, based upon a 10-bit column address, can be processed in the scanout mode of operation before a re- addressing operation need be invoked. Alternately, non-incremental addressing may be implemented. In either incremental or non-incremental addressing configuration; artificial intelligence processing that does not need to move between different blocks of memory, such as with all data being maintained within one block of memory, has increased performance because of reduced need for re-addressing operations; artificial intelligence processing that does not often need to move between different blocks of memory, such as with all data being maintained within a few blocks of memory, has slightly lower performance compared to the above example because of a slightly increased need for re-addressing operations; and artificial intelligence processing that more often needs to move between different blocks of memory, such as with data being distributed over many blocks of memory, has further reduced performance compared to the above examples because of an increased need for re-addressing operations. Consequently, it is desirable to configure the system to maximize scanout operations and to minimize re-addressing operations.
DMA Applications The features of the present invention are also particularly advantageous for direO memory access (DMA) configurations; such as appropriate for computer systems and other systems. A DMA processor typically transfers information between a memory and an external device; such as transferring information from an off-line disk memory into a computer main memory and from a computer main memory into an off-line disk memory. Conventional DMA controllers transfer information to and from blocks of adjacent memory locations. Hence, the scanout and re-addressing features of the present invention can be used efficiently. For example, the single dimensional memory architeOure discussed
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herein with reference to Fig 4G having 10-LSBs for scanout facilitates the transfer of 1024 words at high speed scanout data rates before a single re-addressing operation is invoked. This is such a high scanout duty cycle that the re- addressing operation has negligible effeo on performance. A DMA system can be implemented with a DMA memory for storing information transferred under DMA control, an address register for generating DMA memory addresses, a memory refresh deteOor for generating a memory refresh deteOor signal to invoke memory refresh operations, a memory scanout deteOor for generating a memory scanout deteαor signal to invoke memory scanout operations, and a memory re-addressing deteαor for generating a memory re-addressing deteOor signal to invoke memory re-addressing operations. These features of the present invention may be used separately or in combinations and may be implemented with the various alternate configurations disclosed herein and disclosed in the related patent applications and may be implemented with many other configurations that will now become apparent to one skilled in the art from the teachings herein. For example, a DMA memory can be implemented with the memories discussed herein for any one or combination thereof; such as in Figs 6E to 6N, Figs 4F to 4K, DRAM configuration-!, or others disclosed herein: a DMA memory address register can be implemented with the address registers discussed herein for any one or combination thereof; such as in Figs 60 to 6R, Figs 4B to 4G, DRAM configuration-1, or others disclosed herein: a memory refresh deteOor can be implemented with the memory refresh deteOors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory refresh deteOor circuits (i.e., a time available refresh deteαor circuit) or others disclosed herein: memory scanout and re-addressing deteαors can be implemented with the memory scanout and re-addressing deteOors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory addressing deteOor circuits (i.e., an address overflow deteOor shown in Fig 6C or an address comparitor deteOor shown in Figs 4D and 4E) or others disclosed herein. Read operations, write operations, and read-modify-write operations; such as having scanout and re-addressing in accordance with the present invention; are particularly pertinent for a DMA system. Read operations can be used to scanout the memory, such as for outputting to a hard disk. Write operations can be used for writing into memory, such as for inputting from a hard disk. Read- modify-write operations can be used for processing the information loaded into the memory, such as from a hard disk.
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Cache Memory Applications The features of the present invention are also particularly advantageous for cache memory configurations; such as appropriate for computer systems and other systems. A cache memory processor typically provides a high speed buffer memory inbetween a slower speed memory and a processor. Conventional cache memory controllers transfer information to and from blocks of adjacent memory locations. Hence, the scanout and re-addressing features of the present invention can be used efficiently. For example, the single dimensional memory architeOure discussed herein with reference to Fig 4G having 10-LSBs for scanout facilitates the transfer of 1024 words at high speed scanout data rates before a single re-addressing operation is invoked. This is such a high scanout duty cycle that the re-addressing operation may have negligible effeα on performance. One cache memory configuration can be implemented with a RAM having an address counter for addressing a memory location for read and write operations. A record of information can be loaded into the cache memory from a lower speed memory, such as from a disk memory or from a lower speed RAM. A processor can processor the information stored in cache memory at higher speed to facilitate higher speed processing than possible with the lower speed memory without the cache memory. The record of information can then be unloaded from the cache memory to be stored back into the lower speed memory to free the cache memory for other operations. Loading and unloading information with cache memory can be implemented as a sequential writing and reading respeOively, which facilitates higher speed scanout operations in accordance with the present invention. Some re- addressing operations are invoked, such as resulting from the scanout address crossing a block boundary. However, such re-addressing operations represent 3 relatively low duty cycle compared to scanout operations. Processing of information out of cache memory provides advantages similar to the advantages discussed for the array, filter, and signal processors and the stored program computer supra. The cache memory system can be implemented with a cache memory for storing information, a cache memory address register for generating cache memory addresses, a cache memory refresh deteOor for generating a cache memory refresh deteαor signal to invoke cache memory refresh operations, a cache memory scanout deteαor for generating a cache memory scanout deteαor signal to invoke cache memory scanout operations, and a cache memory re-
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addressing deteαor for generating a cache memory re-addressing deteOor signal to invoke cache memory re-addressing operations. These features of the present invention may be used separately or in combinations and may be implemented with the various alternate configurations disclosed herein and disclosed in the related patent applications and may be implemented with many other configurations that will now become apparent to one skilled in the art from the teachings herein. For example, a cache memory can be implemented with the memories discussed herein for any one or combination thereof; such as in Figs 6E to 6N, Figs 4F to 4K, DRAM configuration-!, or others disclosed herein: a cache memory address register can be implemented with the address registers discussed herein for any one or combination thereof; such as in Figs 60 to 6R, Figs 4B to 4G, DRAM configuration-!, or others disclosed herein: a memory refresh deteOor can be implemented with the memory refresh deteOors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory refresh detector circuits (i.e., a time available refresh deteOor circuit) or others disclosed herein: memory scanout and re- addressing deteαors can be implemented with the memory scanout and re- addressing deteOors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory addressing deteαor circuits (i.e., an address overflow deteOor shown in Fig 6C or an address comparitor deteαor shown in Figs 4D and 4E) or others disclosed herein. Read operations, write operations, and read-modify-write operations; such as having scanout and re-addressing in accordance with the present invention; are particularly pertinent for a cache memory system. Read operations can be used to scanout the memory, such as for outputting to a hard disk. Write operations can be used for writing into memory, such as for inputting from a hard disk. Read-modify-write operations can be used for processing the information loaded into the memory, such as from a hard disk.
Stored Program Computer Applications The features of the present invention are also particularly advantageous for stored program computer configurations. A stored program computer is herein intended to include microcomputers and microprocessors, such as the Intel 80286 and 80386 and the Motorola 68000 families; personal computers, such as the IBM PC (PC/XT and PC/AT) and the IBM PS2 personal computer families; a general purpose computer; a micro-programmable computer; a minicomputer; a small scale computer; a large scale computer; and a super computer, such as manufaOured by Cray and by Amdahl. A stored program computer typically
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processes information under control of a stored program, such as discussed in the related patent applications (i.e.; Serial No. 101,881). A memory or a hierarchy of memories can be used to implement the stored program computer system; such as an off-line or peripheral memory implemented on a disk memory, a main memory (i.e., implemented with DRAMs) for storing a program and for storing information to be processed some or all of which being loaded from the disk memory, or such as a main memory implemented with DRAMs for storing a program and for storing information to be processed, or such as an off- line or peripheral memory implemented with CCDs and a main memory (i.e., implemented with DRAMs) for storing a program and for storing information to be processed some or all of which being loaded from the CCD memory. A stored program computer memory can be implemented using the memory features of the present invention. One configuration of a stored program computer system includes a stored program computer that processes information stored in a main memory. The main memory can be implemented with DRAMs. For example, the main memory can be implemented with DRAMs, a buffer or cache memory can be implemented with DRAMs, and/or other parts of the system can be implemented with DRAMs supra. The computer accesses, processes, and restores the information. The processing involves multitudes of memory accesses and restores; typically involving instruOions stored in close proximity and information stored in close proximity, such as related instruOions stored in the same block of memory and such as related information stored in the same block of memory. Accessing of instruOions stored in the same block can be performed with the scanout operation discussed herein. Accessing of information stored in the same block can also be performed with the scanout operation discussed herein. Accessing of instruαions or information stored in different blocks can be performed with combinations of the scanout and re- addressing operations discussed herein. Particular advantage can be obtained in a computer system by storing instruOions that are related and are to be accessed substantially together in the same block of memory and by storing information that is related and is to be accessed substantially together in the same block of memory in order to maximize higher speed scanout operations and to minimize lower speed re- addressing operations. In addition to the improved instruOion execution time supra, other performance improvements can be obtained in a stored program computer system. For example, many stored program computer systems use off-line disk memory, such as floppy disk memory and hard disk memory, to store
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1 information off-line until needed. The information is then loaded from disk
2 memory into the computers main memory for processing. After processing, the
3 information is then unloaded from main memory into the disk memory for
4 storage. Also, during processing, the information is often saved by unloading
5 from main memory into the disk memory for storage. This loading from and
6 unloading to the disk memory is usually a sequential information transfer from
7 disk memory to main memory and to disk memory from main memory respeOively. This is partially because the information is store on disk in
9 sequential form, such as in seOors and tracks, implicit in the eieOro-mechanical ι o nature of a disk memory and partially because information files, such data files
_ and program files, are construOed or assembled in a sequential format.
12 In view of the above, computer data formats are appropriate for sequential
13 transfers; which can utilize the scanout and re-addressing features of the present
14 invention for performance enhancement. In many applications; operations, such
15 as overlaying from disk memory and saving to disk memory can obtain the full
16 advantage of the scanout and re-addressing feature of the present invention, such
17 as almost four times performance enhancement obtainable from the Toshiba
18 DRAMs supra. This performance enhancement is available for computers that
19 transfer data in various ways, such as under program control and under DMA
20 control. A DMA based comouter system should be able to obtain important ~ 1 performance enhancement, such as due to the relatively high performance -2 capability available with DMA data transfers. Program execution for data
23 tran cf ers should be able to obtain significant performance enhancement from the
24 sea* it and re-addressing features of the present invention, such as when the
25 program for transferring data under program control is small and iterative. This 6 is because the program may readily fit within a block of memory and hence may 7 be able to operate with mostly scanout operations and with relatively few re- 8 addressing operations. 9 A stored program computer system can be implemented with a main program 0 memory for storing program instruαions, an address register for generating main 1 program memory addresses, a memory refresh deteαor for generating a memory 2 refresh deteαor signal to invoke memory refresh operations, a memory scanout 3 deteαor for generating a memory scanout deteαor signal to invoke memory 4 scanout operations, and a memory re-addressing deteOor for generating a 5 memory re-addressing deteOor signal to invoke memory re-addressing 6 operations. These features of the present invention may be used separately or in 7 combinations and may be implemented with the various alternate configurations 8 disclosed herein and disclosed in the related patent applications and may be
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implemented with many other configurations that will now become apparent to one skilled in the art from the teachings herein. For example, a main program memory can be implemented with the memories discussed herein for any one or combination thereof; such as in Figs 6E to 6N, Figs 4F to 4K, DRAM configuration-1 , or others disclosed herein: a main program memory address register can be implemented with the address registers discussed herein for any one or combination thereof; such as in Figs 60 to 6R, Figs 4B to 4G, DRAM configuration-1, or others disclosed herein: a memory refresh deteαor can be implemented with the memory refresh deteOors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory refresh deteOor circuits (i.e., a time available refresh deteOor circuit) or others disclosed herein: memory scanout and re-addressing deteαors can be implemented with the memory scanout and re-addressing deteOors discussed herein for any one or combination thereof; such as disclosed in the seαion herein direOed to memory addressing deteαor circuits (i.e., an address overflow deteαor shown in Fig 6C or an address comparitor deteαor shown in Figs 4D and 4E) or others disclosed herein. Read operations, write operations, and read-modify-write operations; such as having scanout and re-addressing in accordance with the present invention; are particularly pertinent for a computer system. Read operations can be used to scanout the memory, such as for outputting to a peripheral. Write operations can be used for writing into memory, such as for inputting from a peripheral. Read-modify-write operations can be used for processing the information loaded into the memory.
FIFO Memories A first-in first-out (FIFO) memory can achieve significant advantages by using the features of the present invention. One FIFO configuration can be implemented with a RAM having an input address counter for addressing a memory location for writing the next input word, having an output address counter for addressing a memory location for accessing the next output word, and control logic for advancing the input address counter and the output address counter in response to writing and reading respeαively and for insuring that the address counters do not pass each other for an overflow or an underflow condition. A FIFO can be implemented as an incremental memory having an incrementally advanced input address counter and having an incrementally advanced output address counter for incrementally advancing the input address
s u B<3T iτ τe w*#
and for incrementally advancing output address as words are written and read from the FIFO respeOively. Consequently, writing into a FIFO can be implemented within a scanout and reading from a FIFO can be implemented within a scanout. If the input address and the output address are within the same block of memory, such as with the output address closely following the input address; then input and output operations can be interleaved without invoking a re- addressing operation. If the input address and the output address are not within the same block of memory, such as with the output address following the input address from a long distance; then interleaving input and output operations invokes a re-addressing operation when changing from an input operation to an output operation invokes a re-addressing operation. However, regardless of whether changes between input and output operations invoke re-addressing operations; many input operations can typically be performed before a re- addressing operation is invoked as a result of the input address crossing a block boundary and many output operations can typically be performed before a re- addressing operation is invoked as a result of the output address crossing a block boundary. However, such re-addressing operations represent a relatively low duty cycle compared to scanout operations.
Multiple Buffer Memories Multiple buffer memory; such as double, triple, and quadruple buffer memories; can achieve significant advantages by using the features of the present invention. A double buffer memory will be discussed as being illustrative of other multiple buffer memories. One double buffer memory configuration can be implemented with two relatively independent RAM memories each having an address counter for addressing a memory location for read or write operations. Information in one of the two memories is being processed while information in the other of the two memories is being loaded for subsequent processing or is being unloaded of processed information. Loading and unloading information with a multiple buffer memory can be implemented as a sequential writing and reading respeOively, which facilitates higher speed scanout operations in accordance with the present invention. Some re-addressing operations are invoked, such as resulting from the scanout address crossing a block boundary. However, such re-addressing operations represent a relatively low duty cycle compared to scanout operations. Processing of information out of a multiple buffer memory provides
iHEET
advantages similar to the advantages discussed for the array, filter, and signal processors and the stored program computer supra.
Pipeline emories Pipeline memories can achieve significant advantages by using the features of the present invention. One pipeline memory configuration can be implemented with two relatively independent RAM memories each having an address counter for addressing a memory location for read or write operations. Information from one of the two memories is processed by a first processor and the first processed information is . loaded into the second of the two memories in pipeline form as it is being processed. The first processed information stored in the second of the two memories is concurrently being processed by a second processor in pipeline form. Loading and unloading information with a multiple buffer memory can be implemented as a sequential writing and reading respeαively, which facilitates higher speed scanout operations in accordance with the present invention. Some re-addressing operations are invoked, such as resulting from the scanout address crossing a block boundary. However, such re-addressing operations represent a relatively low duty cycle compared to scanout operations. Processing of information out of a multiple buffer memory provides advantages similar to the advantages discussed for the array, filter, and signal processors and the stored program computer supra.
PC XT BIOS Program Application Stored program computer applications are discussed herein. An application to a BIOS program for a PC/XT computer will now be discussed to illustrate some of the features of the present invention. For example, the PC/XT main memory can be re configured in accordance with the scanout and re-addressing features of the present invention to obtain significant performance enhancement. The PC/XT BIOS program listing is provided in the IBM Technical Reference manual dated April 1984 at pages 5-24 to 5-105. It is usually assembled for storage in the ROM portion of the PC/XT main memory, but one skilled in the art can readily assemble it for storage in the RAM portion of main memory to facilitate this example. The PC/XT BIOS code is stored in addresses F000 to FFEE H having 0FEE H bytes or 4078 D bytes. F000 H to FFEE H - FEE H - 4078 D
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Additional bytes of scratchpad memory are used, as defined by the EQU statements in the BIOS program listing. The PC/XT has a main memory that is organized with 64K DRAMs having 8- bits of RAS address and 8-bits of CAS address, equating to 64K bytes of RAM per bank, and having 10-banks of DRAMs. If the PC/XT main memory was reconfigured in accordance with the present invention, then the 8-bits of CAS address would provide 256-bytes of internal scanout and the 10-banks of DRAMs would provide a 10-times improvement using external scanout, yielding 2560 D -bytes per block of scanout. This is more than half of the PC/XT BIOS program of 4078p bytes. Hence, if the PC/XT BIOS program were stored in the RAM portion of the PC/XT main memory, the PC/XT BIOS program and the related scratch pad memory can readily fit in two blocks of main memory. Further performance enhancement can be obtained by improved program partitioning. In a first partitioning example, the PC/XT BIOS program, as with many programs, can be partitioned into independent routines that have minimal interaOion therebetween. The PC/XT BIOS program can be partitioned into a plurality of blocks so that the routines that are stored in different blocks are independent therebetween to minimize interaOion between PC/XT BIOS routines stored in different blocks of memory. Such minimal interaOion between blocks of memory implies improved performance in accordance with the scanout and re-addressing features of the present invention. In a second partitioning example, scanout can be increased and re-addressing can be reduced by partitioning the scratchpad memory in the block of memory with the routine by which it is more often utilized. For example, accessing operands from or storing operands to a block of memory different from the block of memory containing the instruOions will invoke re-addressing operations but accessing operands from or storing operands to the same block of memory containing the instruOions will not invoke re-addressing operations. In view of the above improvements in the architeOure of the PC/XT main memory; the BIOS program should be able to run significantly faster, almost 4- times faster for the above Toshiba DRAM example, then as implemented in the conventional PC/XT computer.
Stored Program Computer Implementation General Stored program computers are typically implemented to process operands by executing instruαions. Operands can be stored in various ways. Operands
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can be stored locally (herein local operands) together with instruOions, such as with inline operands; operands can be stored remotely (herein global operands or remotely stored operands) separate from instruαions, such as in an operand memory space. Programs are assembled by assemblers or compiled by compilers or machine coded by programmers or otherwise generated. Typically, the instruOions are stored in an instruOion memory space (instruOion segment) in sequence having branches, jumps, and other such instruOions discontinuing the sequence of instruαion executions in the instruαion memory space; inline operands are arranged with the related inline instruαions in the instruαion memory space; and an operand memory space having a table of global-type operands is stored in an operand memory space (operand segment) located outside of the instruOion memory space. Often, instruOion execution involves instruOion and inline operand addressing in the instruαion memory space with numerous intervening operand addressings in the operand memory space as the global-type operands are processed. Hence, addressing of instruOions with intervening addressing of operands can cause the memory address to move back and forth between the instruαion memory space and the operand memory space. This can reduce the performance enhancement of the disclosed configurations. Several stored program computer configurations that improve stored program computer operation in accordance with the present invention are discussed below.
Programming Method Configuration In a programming method configuration, the programming method (such as an assembler, compiler, or other method) can be implemented to generate programs having operands combined with instruαions in the same memory block to permit addressing of instruOions in sequence and addressing of related operands with minimum re-addressing. For example; assemblers, compilers, and other program generation methods can be implemented to distribute operands together with instruOions, to distribute instruOions and operands between blocks of the same memory or between different memories, or otherwise. This configuration is particularly pertinent to dedicated systems having a relatively small quantity of operands and having control of or knowledge of where the operands are stored, such as in a dedicated control system, but is also pertinent to other configurations. In a configuration having a comparitor buffer register dedicated to each memory block (such as the Fig 4T configuration), an assembler can be implemented to either place the related instruOions in a particular memory
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block and, where there is no room in that memory block, to place it in other memory blocks of other memory banks so that external scanout can be maximized and re-addressing can be minimized. In addition, the assembler can insert instruOions to re-address a particular memory bank for anticipated accessing or, in a high speed iterative loop, before the loop is entered in order to set it up. This can be done by accessing or storing in the memory block for another memory bank. This is another example of how each of multiple memories don't have to be in the same addressed memory block at the same time. Also, the memory can be configured so that the internal and external scanout covers a very large memory space and hence may only need occasional re-addressing. In a configuration having a ROM and a RAM, the RAM may be continually re-addressed, and in a configuration having a RAM/RAM, the program RAM may be continually re-addressed. However, if the program is in one memory bank and the operands are in another memory bank and they are both properly addressed with the comparitor buffer, then the program in one memory bank can repetitively access operands in the other memory bank without re-addressing operations. Conversely, in a less desirable assembler configuration, the assembler might spatially distribute instruOions between memory banks rather than between memory blocks, involving significant re- addressing. This implements memory bank switching external scanout with higher speed internal scanout operations and occasionally involves slower speed re-addressing operations. This is a charaOerization of how a stored program computer in accordance with the multiple memory and multiple deteOor configurations of the present invention could be implemented in conjunαion with a improved assembler. This is an important charaOerization of this feature. In this configuration, instead of the more significant bits seleαing the memory bank, the less significant bits seleα the memory bank for external scanout and, instead of addresses running through a memory bank before getting to another memory bank (the LSBs), the addresses run through the memory banks for external scanout before re-addressing within the memory bank. In this configuration, the assembler need not be specially implemented to distribute the instruOions and operands across the memory banks because the hardware addressing struOure automatically performs this distribution. This is because consecutive addresses, which are in the LSBs of the assembled code, are distributed across memory banks for this external scanout by the hardware addressing configuration, which is transparent to the assembler. Consequently, the assembler need not be modified to implement this configuration. However,
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the placement of scratch pad parameters in a particular memory block of a particular memory bank that is different from the memory banks having most of the instruOion accessing the operands from the scratch pad provides important advantages. Alternately, the assembler can be modified to implement particular configurations to enhance operation in accordance with the present invention.
Multiple Memory Configuration The memory can be implemented in a multiple memory configuration. The instruOion memory space can be implemented by an instruOion memory having an instruOion memory deteOor circuit and the operand memory space can be implemented by an operand memory having an operand memory deteOor circuit. The address generator can address instruOions and local (such as inline) operands in the seleαed memory block of instruOion memory and the address generator can address operands in the seleOed block of operand memory without the need for re-addressing from instruOion memory to operand memory and back to instruOion memory. This is because instruαion memory and operand memory are implemented as separate memories, such as shown in Fig 4T, and hence addressing back and forth between instruOion memory and operand memory does not in itself invoke re-addressing. This configuration is particularly pertinent to dedicated systems having a relatively large quantity of operands and having control of or knowledge of where the operands are stored, such as in a dedicated control system having an operand memory, but is also pertinent to other configurations. The operand memory can be implemented with RAM chips as an operand memory having its own row address buffer register and deteOor. The program can be assembled or compiled so that the addresses of the global operands correspond to the block address of operand memory. In this way, a program can access instruOions in sequence from instruOion memory and can access operands from operand memory without invoking re-addressing caused by changes between interspersed instruOion memory accesses and operand memory accesses. Some computers (such as the Motorola 68HC11) use lower memory as operand memory for quick instruOion addresses having implied MSBs. In these configurations, lower memory can be implemented as a separate operand memory. This facilitates use of a multiple memory architeOure for existing configuration computers and for existing programs.
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BIOS ROM Configurations An example of multiple memory operations will now be discussed in an improved PC embodiment. This discussion supplements the discussion in the PC/XT BIOS Program Applications seαion herein. The PC BIOS ROM contains a program for performing interface operations. The main memory RAM is used to store operands under control of the BIOS program, where variable operands cannot be stored in ROM because ROM is not alterable by the program. The BIOS ROM does not have RAS/CAS internal scanout and re-addressing capability. Also, even though external scanout can be implemented for the BIOS ROM; the small quantity of ROM chips minimizes the enhancement due to external scanout. However, the main memory RAM does have RAS/CAS internal scanout and re-addressing capability. Hence, use of scanout and re-addressing for the main memory RAM can provide important performance enhancement, with or without use of scanout and re- ~ dressing for the BIOS ROM. In this discussion, the BIOS ROM and the main memory RAM may be considered to be different mt .lories sharing the memory address register. A memory deteαor and delay circuit can be implemented for RAM operand accesses and RAM operand writes under control of the BIOS program stored in the BIOS R ,vl to enhance performance of RAM accesses and writes. A memory deteαor and delay circuit can be implemented for ROM BIOS instruαion accesses to enhance performance of the BIOS ROM in combination with the memory deteαor and delay circuit implemented for RAM operand accesses and RAM operand writes. Alternately, a memory deteαor and delay circuit need not be implemented for ROM BIOS instruOion accesses in combination with the memory deteOor and delay circuit implemented for RAM operand accesses and RAM operand writes. Examples of other circuits that can share an address generator with the subjeα memory will now be discussed for a stored program computer configuration. A memory address generator may be used for addressing input and output circuits in addition to addressing main memory RAM, such as with memory mapped input and output (I/O) circuits that are included in the address space addressed by the computer address generator. Further, a memory address generator may be used for addressing ROM in addition to addressing main memory RAM, such as with the PC computers having a BIOS ROM included in the address space addressed by the micro processor address generator. Also, a memory address generator may be used for addressing a display image memory in addition to addressing main memory RAM, such as with the PC computers
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having a display image memory included in the address space addressed by the micro processor address generator. Also, a memory address generator may be used for addressing a plurality of memory banks each having a separate RAS addressing struOure and hence may be considered to be different memories.
Additional Stored Program Computer Considerations As discussed above, a system can be struOured so that the operands; including the program operands, refresh memory, arrays, etc.; are in different memory banks or external scanout memory space than the instruOion memory so that the instruOions can access and write operands from other memory banks without re-addressing. If the operands exceed the memory block space in a particular memory bank, they can be implemented in multiple memory blocks for scanout without re-addressing. The operands associated with different routines can be grouped together in an operand memory so that there is a minimum of memory block re-addressing for a particular routine in order to access operands. It may be desirable to permit a routine to be distributed, not only in the memory block of a single memory bank but across the spatial domain in memory blocks of all memory banks such as in external scanout. For a routine that covers the same memory block in a plurality of memory banks and for a configuration where re-addressing is achieved block by block by re-addressing, executing this routine may involve re-addressing to load the MSB registers for each of the appropriate memory banks. For example, if there are eight appropriate memory banks it will involve eight re-addressings. Alternately, a short instruOion can be implemented that will re-address a plurality of memory banks simultaneously in preparation for accessing a memory block across many memory banks. In certain configurations, It may be desirable to exclude the operand memory blocks from being re-addressed by this re-addressing instruOion. This re-addressing instruOion might be implemented by setting a hardware flag, such as to be performed on the next transfer instruOion, or by using a transfer or call instruαion to re-address all of the appropriate memory banks. Alternately, all memory banks except for the operand memory bank can be re-addressed together as in the Fig 6 configuration. Hence, seleOive re- addressing can be implemented on an individual memory bank basis and group re-addressing for a plurality of memory banks can be implemented to be performed simultaneously for multiple memory banks. For example, this configuration is consistent with implementations where the lower memory addresses are used for operands and the upper memory addresses are for the
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program. This configuration may use an assembler for distributing operands (but not for instruOions) differently. This is because the instruOions are sequential in nature with addressing providing memory bank switching, but the operands to be contained in an operand memory bank can cut across memory blocks in that operand memory bank. Hence, the external scanout address bits can have a memory bank removed therefrom for operands. This need not be a wiring partitioning, but can be an assembler partitioning. Because an assembler is generally used with hardware for check-out, the assembler and the hardware can be charaOerized as assigning of instruOions to a first plurality of memory banks, assigning operands to a second plurality of memory banks, accessing an instruOion from one memory bank, and accessing an operand from another memory bank without re-addressing. This can be implemented to be transparent to the programmer and the user except that the operands may be distributed at different address memory banks in the listing. However, this can be compensated by listing the operands together and by listing the instruOions together even though there may be memory banks of discontinuities between the instruOions for the operands and there may be discontinuities between the addresses of operands and instruαions. This is an excellent implementation for a stored program computer configuration. In a configuration having a rather large memory block size resulting from external scanout and a relatively small number of transfer and call type instruOions, instruαion execution can involve relatively few re-addressing operations. One consideration is operand read and write operations. However, a configuration having dedication of a memory bank or memory banks to operands and implementing independent memory block seleα for operand memory facilitates operand read and write operations. Hence, a stored program computer memory configuration using this implementation may be almost as efficient as an array processor memory. In view of the above, because instruOions can be distributed in memory blocks across the memory banks, and because instruOions are mostly sequential; a configuration can be implemented to re-address MSBs constantly for all of the instruOion memory and non-constantly only for operand memory. However, in alternate configurations, advantages may be obtained by having separate independent re-addressing buffers for each memory bank. Two methods are special instruOions and setting of a latch. The latch may be resettable after it has been utilized, such as a one shot latch rather than a modal latch, although modal latches can also be implemented.
ET
Dynamic Allocation Configuration In a dynamic allocation configuration, such as charaOerized by personal computers, the computer is implemented to accommodate a disk operating system (such as CP/M or DOS). An application program overlays instruOions and operands from disk into main memory, which is implemented with RAM chips. The operating system may be considered to implement dynamic allocation of main memory. Hence, the instruOions and operands are stored at addresses that are different for different computer configurations, for different operating environments, and for different operating sequences. For example, the size of the application program operand space and the programs that are memory resident can alter the physical addresses assigned to instruOions and operands. This dynamic allocation type configuration will be discussed in more detail below. In a PC type configuration overlaying instruOions and operands, they are often overlaid into dynamically allocated instruOion space and operand space of main memory. Although it is not required to partition the main memory into instruOion space and operand space, performance advantages can be obtained in certain configurations if it is thus partitioned. General purpose systems need flexibility in the amount of operands and instruOions, in certain configurations it may be desirable to have separate re-addressing deteαors for each memory bank so that the amount of instruOion memory space and operand memory space can be varied at will. A configuration register can be used to seleα which memory banks are re-addressed simultaneously. Certain of these memory architeOures can be charaOerized as closed loop architeOures, where the processor and the address register are in a closed loop under control of a re-addressing deteαor. In various configurations, it is desirable to distribute the instruOions spatially over memory banks to facilitate external scanout and it is desirable to concentrate operands in one memory bank and to minimize distribution of operands spatially in order to maximize the amount of spatial memory space for the instruOions. In a memory enhancement configuration using commercially available DRAMs, the performance enhancement for each scanout operation is about 3.5 times (1 0ns/55ns - 3.45 times • => 3.5 times). In a disclosed configuration, this performance enhancement will be reduced, but only slightly, for an occasional re-addressing operation. However, in a stored program computer configuration, this performance enhancement may be reduced even more due to re-addressing between the instruOion memory space and the operand memory space.
SHEET
Examples illustrating performance enhancement for a disk operating system based stored program computer configuration are provided below. In configurations having a ROM BIOS (DOS or OS2 based PCs and PS2s) and for ease of discussion, instruOion memory space may be considered to be in the ROM BIOS and the RAM main memory may be considered to be in the operand memory space. The ROM BIOS typically has the BIOS instruαions and some BIOS operands and the RAM main memory typically has the other operands. Hence, many of the BIOS instruαions can be executed without changing memory blocks or memories. A first dynamic allocation configuration is discussed with reference to the SPATIAL DIMENSION CONFIGURATION TABLES; where one in four instruOions on the average needs an operand from the data segment, re- addressing for instruαion to instruOion byte or word and for operand to operand byte or word is at scanout timing, and an occasional re-addressing when a sequence of instruOions exceeds a memory block boundary in the same dimension is disregarded because it may be infrequent (such as each 128 accesses). The first configuration may be considered to be implemented with a multi-dimensional address space having a plurality of dimensions. Each dimension is defined by the different memory having its own dimension address register (DRAM chips that are seleOed by the address space bits and that store the re-addressing bits for that dimension and that are not in the re-addressing space of other DRAM chips as with external scanout chips). Address changes in the scanout direOion, either wi t hin a dimension (internal scanout and external scanout) or between dimensions (changing dimensions without the need to re- address the new dimension), generates fast addressing and is maximized. Address changes in the re-addressing direOion, either within a dimension (re- addressing the current dimension) or between dimensions (re-addressing the next dimension), generates slow addressing and is minimized. This maximizing of scanout and minimizing of re-addressing (in this illustrative configuration) is facilitated by seleαing the dimensions and by scattering the instruOions and operands in packets throughout. Because the address lines, as skewed as they may be, are consistent; the scattered locations are stored and accessed from the proper locations and hence implementing an implicit decoder. A second dynamic allocation configuration is discussed with reference to STAGGERED CONFIGURATION TABLES using staggered dimensions; where some of the lower middle significant bits (such as the 7th and 8th bits from the LSB) are used as dimensional bits to cause the operands to be placed in a different dimension (on an average) than the instruαions. This causes a group of
SUBSTITUTE SHEET
instruαions (such as 2 exp 7 - 128 instruαions) to be accessed from the same dimension (such as dimension 1), then causes the next sequential group of instruOions (such as 2 exp 7 - 128 instruOions) to be accessed from a second dimension (such as dimension 2), then causes the next sequential group of instruαions (such as 2 exp 7 - 128 instruαions) to be accessed from still another dimension (such as dimension 3), and then causes the next sequential group of instruOions (such as 2 exp 7 - 128 instruαions) to be accessed from still another dimension (such as dimension 4) with arbitrary seleOion of the relative memory block (relative to the memory block of the corresponding instruαion) from which an operand will be accessed (such as dimension 1). Certain implementations of this second configuration may inyolve an inefficiency (such as 1/128 inefficiency) caused by a forced re-addressing to another dimension for a sequence of instruαions In aOual operation, all of the instruOions may be in the same dimension with all of the operands for a worst case re-addressing condition or all of the instruOions may be in a different dimension from all of the operands for a best case re-addressing condition. However, if the lower middle significant bits are seleOed to be low enough (such as 2 exp 7 - 128), the average over a short period of time (such as one second) will have enough instruOions executed (such as 500,000 instruOions executed for a second) to provide a good statistical average. It is desired that the lower middle significant bits be seleOed to be low enough (such as 2 exp 7 - 128) to average out the statistical uncertainties of the dimension containing the operands and be high enough (such as 2 exp 7 = 128) to keep the instruαion access re-addressing to be small. This second configuration facilitates greater performance for a larger memory, but not necessarily for an expanded memory. This is because the dimensions should be fixed at the minimum number of dimensions so that there are no unpopulated holes in the address space that the program counter goes through in the minimum configuration. However, memory expansion can also include changing the number of dimensions by changing address lines. This is valid for a volatile memory because booting up the program reloads main memory to the new configuration but ROM is not reloaded and hence is not automatically reconfigured for an increase in dimensions. Hence, in this configuration the BIOS ROM should be outside of this multi-dimensional address space, such as by using a different set of fixed address lines for the BIOS ROM that are independent of the dimensioning for the RAM address space. For this same reason (that there are no unpopulated holes in the address space that the
~ B s τιτυ nr
----ZA
program counter goes through), the multi-dimensional address space should be rectangular.
ADDITIONAL CONSIDERATIONS Bit Partitioning Terminology Various memory architeOures have been disclosed relative to more significant address bits, most significant address bits, middle significant address bits, less significant address bits, least significant address bits, and other charaOerizations of significance of address bits. It is intended that these groupings of address bits be representative of other groupings of address bits. For example; a first group of address bits, or a first plurality of address bits, or a first part of the address, or a first portion of file address, or other such first charaOerization can be the more significant bits or the most significant bits of the address and a second group of address bits, or a second plurality of address bits, or a second part of the address, or a second portion of the address, or other such second charaOerization can be the less significant bits or the least significant bits of the address. As another example, in a counter configuration the less significant bits change more rapidly and the more significant bits change less rapidly or the less significant bits represent the addresses of data that has more adjacency and the more significant bits represent the addresses of data that has less adjacency.
Chip Size Considerations The size of the RAM chips (such as the number of bits per chip) and the chip configuration (such as the number of bits per chip address) can affeα the memory architeOure. For example, the larger the chips (the more bits in the chip address), the more the internal scanout and the less the external scanout. Also, the larger the memory (the more bits in the memory address), the more the external scanout. The more the external scanout, the more the flexibility in implementing multiple memories.
Memory Refresh Memory refresh operations can cause contention between processor operations and refresh operations. One way to resolve contention is to put the processor on hold during refresh operations. However, seleOively holding the processor can enhance processing bandwidth. For example, if the processor is generating a store operation when the memory is involved in a refresh operation, a buffer register or other memory circuit can be used to buffer the
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data and address for the store operation until the refresh operation is completed, permitting the processor to continue with non-contention related processing and not be held up waiting for completion of the refresh operation.
DRAM Fast Page/Static Column Mode Timing Average timing for one configuration of a display processor is a funαion of scanout time and re-addressing time. Assuming a maximum X/Y address slope of unity and a 2-megapixel (12-bit 2- dimensional) scanout, re-addressing occurs at a worst case rate (based upon an average slope of unity) of 6-bits of integer pixel position or 63 slope updates, This represents 1/16 of a scanline of pixels. Hence, re-addressing occurs 16- times per scanline maximum and occurs on the average of 12-times per scanline based upon a range of slopes inbetween 0.5 and unity. This is a 1/16th worst case duty cycle applied to the re-addressing operation (triple CPD clocks or two extra CPD clocks) for a 1/8th (12.5%) increase in time due to the re-addressing operation. Assuming a maximum slope of unity and an 8-megapixel (14-bit) 2- dimensional scanout, re-addressing will occur at a worst case rate (based upon an average slope of unity) of 7-bits of integer pixel position or 63 slope updates. This represents 1/32 of a scanline of pixels. Hence, re-addressing occurs 32- times per scanline maximum and occurs on the average of 24-times per scanline average based upon a range of slopes inbetween 0.5 and unity. This is a 1/32nd worst case duty cycle applied to the re-addressing operation (triple CPD clocks or two extra CPD clocks) for a 1/16th (6%) increase in time due to the re- addressing operation.
GENERAL CONSIDERATIONS Abbreviations may be used herein, which abbreviations are defined below. "ns" means nanoseconds. " us" means microseconds. "ms" means milliseconds. An asterisk "*" following a logical symbol or a line over a logical symbol is read as "bar" and means that the logical symbol is in complemented signal form. Components in the schematic diagrams have been seleαed For simplicity of discussion. For example, AND gates and OR gates may be used in place of NAND gates and RS flip-flops may be used in place of D flip-flops or JK flip- flops. These schematic diagrams can be changed by one skilled in the logical
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design art from the teachings herein optimization of propagation delays, use of a different line of integrated circuits, etc. Well known flip-flops have synchronous inputs that are controlled by the clock and asynchronous inputs that are independent of the clock. The asynchronous inputs typically over-ride the synchronous inputs. For example, flip-flops 756D and F507 (Figs 7E and 7H) each has synchronous inputs S and R that are controlled by the clock CK; flip-flop 757D (Fig 7E) has synchronous input D that is controlled by the clock CK and asynchronous clear input CR that is not controlled by the clock and that over-rides the D synchronous input; and flip-flops F505 and F506 (Fig 7H) each has synchronous input D that is controlled by the clock CK and asynchronous set input SET* that is not controlled by the clock and that over-rides the D synchronous input.
DISCLOS RE DOCUMENTS Disclosure Document No. 131,747 has been filed in the U. S. Patent and Trademark Office on OOober 17, 1984; which Disclosure Document No. 131,747 is herein incorporated by reference; and which Disclosure Document No. 131,747 has copies of many of the documents and specification sheets referenced herein as follows. 1. National SemiconduOor specification sheet for the MM5321 synchronization generator. 2. Signetics specification sheet for the 8T95, 96, 97, 98 hex buffers/inverters. 3. National SemiconduOor specification sheet for the ADC 0800 A/D converter. 4. Texas Instruments specification sheet for the TNS-4016 RAM. 5. TRW specification sheet for the TDC1016J-8, TDC1016J-9, TDC1016J-10 video D/A converters. 6. Mitsubishi EleOric specification sheet for the M58725P, S;P-15, S-15, RAMs. 7. Computer Compatible Joystick InstruOion sheet. 8. CompuPro CPU 8085/88 Technical Manual. 9. Viewpoint/3A Plus User's Manual. 10. CompuPro RAM 17 Technical Manual. 11. CompuPro RAM 16 Technical Manual. 12. CompuPro 8080 Multi-User Monitor program listing. 13. CompuPro System Support 1 User Manual. 14. International Instrumentation Incorporated Universal Disk Enclosures manual.
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15. Siemens OEM Floppy Disk Drive FDD 100-8 manual. 16. CompuPro Disk 1 User Manual. Disclosure Document No. 210,594 has been filed in the U. S. Patent and Trademark Office on or about September 19, 1988 and Disclosure Document No. 252,883 has been filed in the U. S. Patent and Trademark Office on or about May 8, 1990; which Disclosure Documents No. 210,594 and No. 252,883 are herein incorporated by reference. The material in Disclosure Documents No. 210,594 and No. 252,883 have been integrated herein.
RELATED DOCUMENTS Various documents are pertinent hereto and are herein incorporated by reference. 1) 8086 Family User's Manual; Oαober 1979; by Intel Corp. 2) TECHNICAL REFERENCE; September 1985; by IBM Corp. 3) MCS-85 USER'S MANUAL; September 1978; by Intel Corp. 4) MC68020 User's Manual; 1984; by Motorola inc. 5) 8-BIT MICROPROCESSOR & PERIPHERAL DATA manual; 1983; by Motorola Inc. 6) MOS MEMORY PRODUCTS DATA BOOK; 1986-1987; by Toshiba. 7) Shottky TTL Data Book; 1983; by Motorola Inc. 8) 8086 Family User's Manual; Oαober 1979; by Intel Corp.; particularly at pages 4-10, A-23 to A-25, B-9, B-1 1 , B-69, B-70. 9) TECHNICAL REFERENCE; September 1985; by IBM Corp.; particularly at pages 1-76, 1-82, and at Bibliography-1. 10) MCS-85 USER'S MANUAL; September 1978; by Intel Corp.; particularly at pages 5-2 and 5-6. 11) MC68020 User's Manual; 1984; by Motorola Inc.; particularly at pages 4-3 and 4-5. 12) 8-BIT MICROPROCESSOR & PERIPHERAL DATA manual; 1983; by Motorola Inc.; particularly at page 3-157. 13) MOS MEMORY PRODUCTS DATA BOOK; 1986-1987; Toshiba; particularly at pages 119, 121 , 123, 125, 127, and 128. 14) Motorola Shottky TTL Data Book; 1983; particularly at pages 4-59 to 4- 62. 15) Intel Memory Design Handbook; 1977. 16) MC68HC11 HCMOS Single-Chip Microcomputer Programmer's Reference Manual; First Edition; particularly at Seαion 5 therein.
SUBSTITUTE S
The prior art is further indicated by the references cited on the List Of Art Cited By Applicant filed herewith, as may be predated in view of the effeoive filing dates of the various disclosures in the present application. The references cited on the List Of Art Cited By Applicant filed herewith are herein incorporated by reference as if fully set forth at length herein.
SHEET
TAB ES
F FIG 4H ADDRE S CORRESPONDENCE TABLE
ADDRESS GROUP
INTERNAL SCANOUT
INTERNAL SCANOUT
EXTERNAL SCANOUT EXTERNAL SCANOUT
RAS RE-ADDRESS
RAS RE-ADDRESS
EXTERNAL SCANOUT
400Y NOT USED 400Z NOT USED
BSTITUTE SHEET
SECOND FIG 4H ADDRESS CORRESPOND NC ABL
SU BSTITUTE SHEET
THIRD FIG 4H ADDRESS C
SUBST
FORTH FIG 4H ADDRESS CORRES ONDENCE L
SUBSTITUTE SHe
FIFTH FIG 4H ADDRESS CORRESPONDENCE
SUB ST
SIXTH FIG 4H ADDRESS CORRESPONDENCE TABLE
SUBSTITUTE SHEET
SUBSTITUTE SHEET
FIG 41 ADDRESS CORRESPONDENCE TABLE
INPUT ADDRESS ADDRESS GROUP LINE DIMENSIONS (FIG 41) ONE TWO
INTERNAL SCANOUT
INTERNAL SCANOUT
EXTERNAL SCANOUT
EXTERNAL SCANOUT
RAS RE-ADDRESS
RAS RE-ADDRESS
SUBSTI T
FIG 4J ADDRESS CORRESPONDENCE TABLE
INPUT ADDRESS ADDRESS GROUP LINE DIMENSIONS fFIG 4J) ONE TWO
401A INTERNAL SCANOUT 401B 401C 401D 401E 401F 401G 401H 4011 INTERNAL SCANOUT
401V EXTERNAL SCANOUT 401W 401X 401Y 401Z EXTERNAL SCANOUT
401L RAS RE-ADDRESS 401M 401N 401P 401Q 401R 401S 401T 401U RAS RE-ADDRESS
401J NOT USED 4OIK NOT USED
SUBSTITUTE SHEET
VIDEO DAC CONNECTION TABLE
NO CONNECTION
-5VDC
6.8 MICROFARAD CAPACITOR TO -5VDC
-IV
GROUND
GROUND
VIDEO OUTPUT TO BUFFER AMPLIFIER
GROUND
+5VDC
GROUND
BLANKING SIGNAL
CLOCK
MOST SIGNIFICANT BIT, COMPLEMENT MOST SIGNIFICANT BIT, UNCOMPLEMENT +5VDC
DATA BIT 2, COMPLEMENT DATA BIT 2, UNCOMPLEMENT GROUND GROUND DATA BIT 3, COMPLEMENT - GROUND DATA BIT 3, UNCOMPLEMENT GROUND DATA BIT 4, COMPLEMENT - GROUND DATA BIT 4, UNCOMPLEMENT GROUND DATA BIT 5, COMPLEMENT - GROUND DATA BIT 5, UNCOMPLEMENT RED,
BLUE GROUND; GREEN SIGNAL
DATA BIT 6, COMPLEMENT - GROUND DATA BIT 6, UNCOMPLEMENT RED, BLUE,
GREEN SIGNAL DATA BIT 7, COMPLEMENT - GROUND DATA BIT 7, UNCOMPLEMENT RED, BLUE,
GREEN SIGNAL DATA BIT 8, COMPLEMENT - GROUND DATA BIT 8, UNCOMPLEMENT GROUND DATA BIT 9 , COMPLEMENT - GROUND DATA BIT 9, UNCOMPLEMENT LEAST SIGNIFICANT BIT, COMPLEMENT LEAST SIGNIFICANT BIT, UNCOMPLEMENT NO CONNECTION NO CONNECTION NO CONNECTION
τε SHEET
SUBSTVTU
COMPUTER PORT TABLE PORT-A CONTROL PORT
NOTES
HIGH IS UNBLANKED,
LOW IS BLANKED
DOA5 SEQUENTIAL-LOAD SEQUENTIAL LOAD OF
IMAGE MEMORY
DOA6 LOAD-BAR/RUN BRACKETED BY FRAME
BLANKING CFS
BRACKETED BY PBO AND PCO
VERTICAL FIELD BLANKING PULSE
HORIZONTAL LINE BLANKING PULSE
SEQUENTIAL CONTROL OF IMAGE LOADING
(1) RESET DOA5
(2) LOAD X+Y START ADDRESSES, (PIXEL ADDRESS TIMES 8)
(3) LOAD SLOPES TIMES 256
(4) SET DOA5
(5) GENERATE A SEQUENCE OF STROBED DATA OUTPUTS ALONG LINE
(6) ADDRESS COUNTER WILL AUTOMATICALLY ADVANCE
(7) DOA5 must be set before strobing data into memory independent of whether one or a sequence of strobes is to be generated.
SHEET j ϋβS Ϊ rruTE
PORT-B ADDRESS/DATA PORT
NAME FUNCTION NOTES
LSB
MSB
LSB
MSB
SUBSTITUTE SHEET
PORT-C DESTINATION SELECT PORT
NAME FUNCTION NOTES
LSB
MSB
LSB
MSB
SUBSTITUTE SHEET
DESTIHATION SELECT ASSIGNMENTS £ B7 B6 B5 BA B3 B2 B1 BO REGISTER B7 B6 B5 BA B3 B2 Bl BO.
0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1
2 0 0 0 0 0 0 1 0
127 0 0 0 0 1 1 1 1
128 0 0 0 1 0 0 0 0
129 0 0 0 0 0 0 1
130 0 0 0 0 0 1 0
NOTES
1. Frame sync and CP-bar must be synchronized
2. Gated clock.
3. First line sync per frame is under the frame sync envelope. Therefore, U20D-1 generates second line sync as first pulse.
4. First line sync under frame sync envelope loads pixel registers.
S UBSTITUTE SHE T
CABLE CONNECTION TABLE
CABLE-1 BH1.2/BL1 (CD
PIN SIGNAL SIGNAL DESCRIPTION SOURCE DESTINATION
1 GROUND GROUND
2 YAO HEHORY ADDRESS, BIT-YO BL1-U9E-10 BH1.2-U19B-1
3 GROUND GROUND
A YA1 HEHORY ADDRESS, BIT-Y1 BL1-U9E-12 BH1,2-U19B-2
5 GROUND GROUND
6 YA2 HEHORY ADDRESS, BIT-Y2 BL1-U9E-15 BH1.2-U19B-3
7 GROUND GROUND
8 YA3 HEHORY ADDRESS, BIT-Y3 BL1-U8E-2 BH1.2-U19A-2
9 GROUND GROUND
10 YAA HEHORY ADDRESS, BIT-YA BL1-U8E-5 BH1.2-U19A-4
11 GROUND GROUND
12 YA5 HEHORY ADDRESS, BIT-Y5 BL1-U8E-7 BH1.2-U19A-6
13 GROUND GROUND
14 YA6 HEHORY ADDRESS, BIT-Y6 BL1-U8E-10 BH1.2-U19A-10
15 GROUND GROUND
16 YA7 HEHORY ADDRESS, BIT-Y7 BL1-U8E-12 BH1,2-U19A-12
17 GROUND GROUND
18 YA8 HEHORY ADDRESS, BIT-Y8 BL1-U8E-15 BH1.2-U19A-1A
19 GROUND GROUND
20 XAO HEHORY ADDRESS, BIT-XO BL1-U9D-10 BM1.2-U19C-1
21 GROUND GROUND
22 XA1 HEHORY ADDRESS, BIT-X1 BL1-U9D-12 BM1.2-U19C-2
23 GROUND GROUND
24 XA2 HEHORY ADDRESS, BIT-X2 BL1-U9D-15 BH1.2-U19C-3
25 GROUND GROUND
26 XA3 HEHORY ADDRESS, BIT-X3 (BH2) BL1-U8D-2 BH1.2-U19B-6
27 GROUND GROUND
28 XA3-BAR HEHORY ADDRESS, BIT-X3-BAR (BH1) BL1-U18D-4 BH1.2-U19B-6
29 GROUND GROUND
30 XAA HEHORY ADDRESS, BIT-XA BL1-U8D-5 BH1,2-U19D-A
31 GROUND GROUND
32 XA5 HEHORY ADDRESS, BIT-X5 BL1-U8D-7 BH1.2-U19D-6
33 GROUND GROUND
34 XA6 HEHORY ADORESS, BIT-X6 BL1-U8D-10 BH1,2-U19D-10
35 GROUND GROUND
36 XA7 HEHORY ADDRESS, BIT-X7 BL1-U8D-12 BH1.2-U19D-12
37 GROUND GROUND
38 XA8 HEHORY ADDRESS, BIT-X8 BL1-U8D-15 BH1,2-U19D-1A
39 GROUND GROUND
AO W1-BAR HEHORY READ/URITE (LOU => WRITE) BL1-U22C-11 BM1.2-U19E-A
A1 GROUND GROUND
42
A3 GROUND GROUND
AA
45 GROUND GROUND
A6
A7 GROUND GROUND
48
49 GROUND GROUND
50
s "£sr
CABLE-II BH1.2/BL1/BB1 (C2)
PIN SIGNAL SIGNAL DESCRIPTION SOURCE DESTINATION
1 GROUND GROUND
2 HIO HEHORY DATA INPUT, BIT-O (PBO) BL1-C6-9 BH1,2-U17A,B,C,D-A
3 GROUND GROUND
A HI1 HEHORY DATA INPUT, BIT-1 (PB1) BL1-C6-22 BH1,2-U17A,B,C,D-7
5 GROUND GROUND
6 HI2 HEHORY DATA INPUT, BIT-2 (PB2) BL1-C6-10 BH1,2-U17A,B,C,D-9
7 GROUND GROUND
8 HI3 HEHORY DATA INPUT, BIT-3 (PB3) BL1-C6-23 BH1,2-U17A,B,C,D-12
9 GROUND GROUND
10 HIA HEHORY DATA INPUT, BIT-A (PBA) BL1-C6-11 BH1,2-U18A,B,C,D-A
11 GROUND GROUND
12 HI5 HEHORY DATA INPUT, BIT-5 (PB5) BL1-C6-2A BH1,2-U18A,B,C,D-7
13 GROUND GROUND
1A HI6 HEHORY DATA INPUT, BIT-6 <PBό) BL1-C6-12 BH1,2-U18A,B,C,D-9
15 GROUND GROUND
16 HI7 HEHORY DATA INPUT, BIT-7 (PB7) BL1-C6-25 BH1,2-U18A,B,C,D-12
17 GROUND GROUND
18 HOO HEHORY DATA OUTPUT, BIT-0 (GREEN) BHl,2-U17A,B,C,D-2 BB1-U...;CA-22
19 GROUND GROUND
20 HOI HEHORY DATA OUTPUT, BIT-1 (GREEN) BHl,2-U17A,B,C,D-5 BB1-U...;CA-2A
21 GROUND GROUND
22 H02 HEHORY DATA OUTPUT, BIT-2 (GREEN) BH1,2-U17A,B,C,D-11 BB1-U...;CA-26
23 GROUND GROUND
2A H03 HEHORY DATA OUTPUT, BIT-3 (RED) BH1,2-U17A,B,C,D-1A BB1-U...;CA-28
25 GROUND GROUND
26 HOA HEHORY DATA OUTPUT, BIT-A (RED) BH1,2-U18A,B,C,D-2 BB1 ;CA-30
27 GROUND GROUND
28 H05 HEHORY DATA OUTPUT, BIT-5 (BLUE) BH1,2-U18A,B » C,D-5 BB1 ;CA-32
29 GROUND GROUND
30 H06 HEHORY DATA OUTPUT, BIT-6 (BLUE) BH1,2-U18A,B,C,D-11 8B1 ;CA-34
31 GROUND GROUND
32 H07 HEHORY DATA OUTPUT, BIT-7 (SPARE) BH1,2-U18A,B,C,D-1A BB1 ;CA-36
33 GROUND GROUND
3A DIEN-BAR HEHORY READ/WRITE BL1-U21E-6 BH1,2-U18A,B,C,D-15
BH1,2-U17A,B,C,D-15, U19C-6, BB1-U23C-1.15, BB1-U23D-1.15
35 GROUND GROUND 36
37 GROUND GROUND 38
39 GROUND GROUND 40
41 GROUND GROUND A2
A3 GROUND GROUND AA
A5 GROUND GROUND 46
47 GROUND GROUND 48
49 GROUND GROUND 50
SUBSTITUTE SHEET
CABLE-III BR1/BL1/BB1 (C3)
SOURCE DESTINATION
BB1-U22C-10
BB1-U22C-13
BB1-U22C-6
BB1-U22C-3
BB1-U22D-3
BB1-U22D-6
BB1-U22D-13
BB1-U22D-10
BL1-U21E-6 BB1-U7B-4
BL1-U21D-8 BB1-U7A,U6A,U5A-2
BB1-U21E,U22E-10 BB1-U23E-10
SUBSTITUTE SHEET
BLE-IV BR1 BL1 BB1 CA
SUBSTITUTE SHEET
CABLE-V BL1/C0MPUTER PORT-A CONTROL (C5) IN SIGNAL SIGNAL DESCRIPTION SOURCE DESTINATION
COMPUTER DATA INPUT, FRAME SYNC CA-2 COMPUTER
COMPUTER DATA INPUT, LINE SYNC CA-A COMPUTER
COMPUTER DATA INPUT, FIELD 1-BAR CA-12 COMPUTER
COMPUTER DATA INPUT COMPUTER
COMPUTER DATA OUTPUT, TEST PULSE-1 COMPUTER
COMPUTER DATA OUTPUT, JOYSTICK SEL.-O COMPUTER CA-16
COMPUTER DATA OUTPUT, TEST PULSE-16 COMPUTER
COMPUTER DATA OUTPUT, LOAD-BAR/RUN COMPUTER BL1-U18D-5
GROUND
COMPUTER DATA INPUT COMPUTER
COMPUTER DATA INPUT COMPUTER
COMPUTER DATA INPUT COMPUTER
COMPUTER DATA INPUT COMPUTER
GROUND
GROUND
COMPUTER DATA OUTPUT, JOYSTICK SEL.-1 COMPUTER DATA OUTPUT, UNBLANK COMHAND SEQ. LOAD OF IMAGE HEHORY OUTPUT DATA STROBE
SHEET
SUBSTITUTE
s UBSTITUTE SHEET
CABLE-VIl BL1/C0MPUTER PORT-C REGISTER SELECT (C7) NAL SIGNAL DESCRIPTION SOURCE DESTINATION
COMPUTER COMPUTER COMPUTER COMPUTER
COMPUTER BL1-U19B-1, U20B-1
COMPUTER BL1-U19B-3, U20B-3
COHPUTER BL1-U21D-5
COMPUTER BL1-U21D-2
COMPUTER COHPUTER COHPUTER COMPUTER
COMPUTER BL1-U19B-2, U20B-2
COMPUTER BL1-U19B-6, U20B-5
COMPUTER BL1-U21D-A
COHPUTER BL1-U21D-1
j u B srrruTE SHEET
OF DIP LAYOUT
SUBSTITUTE SHEET
SUBSTITUTE SHEET
(LS365 EQUIVALENT)
(LS365 EQUIVALENT)
SUBSTITUTE SHEET
SUBSTITUTE SHEET
SUBSTITUTE SHEET
SUBSTITUTE SHEET
MORY TAB - -
SUBSTITUTE SHEET
M ORY TABLE-
SUBSTITUTE
SUBSTITUTE SHEET
MEMORY TAB -
SUBSTITUTE SHEET
MEMORY T B -
SUBSTITUTE SHEET
MEMO -C
SUBSTITUTE SHEET
S8Z90/I6Sfl/I3d ε,9W)/Z6 OA
MEMORY TABLE-D C
SUBSTITUTE SHEET
BASIC PROGRAM LISTING GRAPH.ASC
100 PRINT: PRINT: PRINT "FILE: GRAPH.ASC" 110 CLEAR 1940 R%=INP (236): S%=R% AND 1: IF S%=1 THEN 1940 'LOCKUP ON VERT.SYNC=1
1980 R%=INP (236): S%=R% AND 16: IF S%=0 THEN 1940 'CHECK FIELD
1990 OUT 236,64 'INITIALIZE GRAPHICS GENERATOR 1992 R%=INP (236): S%=R% AND 1 1993 IF S%=0 THEN 1992 'LOCKUP ON VERT.SYNC=0 1994 OUT 236,0 'COMMAND LOAD, RUN-BAR 1995 OUT 238, 246: OUT 237, 0: OUT 236,128:
OUT 236,0 'X-RO MSH
1996 OUT 238, 247: OUT 237, 0: OUT 236,128: OUT 236,0 'X-ROW LSH
1997 OUT 238,242: OUT 237, 0: OUT 236,128: OUT 236,0 'X-PIXEL SLOPE MSH
1998 OUT 238,245: OUT 237, 0: OUT 236,128: OUT 236,0 'Y-PIXEL SLOPE MSH
1999 OUT 238,248: OUT 237, 0: OUT 236,128: OUT 236,0 'X-ROW SLOPE MSH
2000 OUT 238,251: OUT 237, 0: OUT 236,128: OUT 236,0 'Y-ROW SLOPE MSH
2001 OUT 238,244: OUT 237, 0: OUT 236,128: OUT 236,0 'Y-PIXEL SLOPE LSH
2002 OUT 238,240: OUT 237, 0: OUT 236,128: OUT 236,0 'X-ROW SLOPE LSH
2003 OUT 238,243: OUT 237, 255: OUT 236,128: OUT 236,0 'X-PIXEL SLOPE LSH
2004 OUT 238,241: OUT 237, 255: OUT 236,128: OUT 236,0 'Y-ROW SLOPE LSH
2005 OUT 236,80 'COMMAND RUN, LOAD-BAR ; PULSE-1 BRACKETING COMPUTATION PERIOD
2006 R%=INP (236): S%=R% AND 1: IF S%=1 THEN 2006 'LOCKUP ON VERT.SYNC=1
2007 R%=INP (236): S%=R% AND 16: IF S%=0 THEN 2006 'CHECK FIELD
2060 'ITERATIVE PROCESSING
SUBSTITUTE SHEET
2100 OUT 236,64
2140 'RESYNCHRONIZATION AND FIELD CONTROL PROCESSOR
2220 R%=INP (236): S%=R% AND 1
2300 IF S%=0 THEN 2220 'LOCKUP ON VERT.SYNC=0
3060 'INTERLACED SCAN CALCULATIONS
3100 'INPUT BYTE 128 064 032 016 008 004 002 001
3140 ' F2 Fl LS FS
3180 OUT 236,0 'COMMAND LOAD, RUN-BAR
3220 R%=INP (236): S%=R% AND 16: IF S%=0 THEN 3540 ELSE
3260 'CHECK FIELD
3260 'FIELD-2
3300 'OUTPUT POSITION PARAMETERS
3340 OUT 238, 249: OUT 237, 0: OUT 236,128: OUT 236,0 'Y-ROW MSH
3380 OUT 238, 250: OUT 237, 4: OUT 236,128:
OUT 236,0 'Y-ROW LSH
3500 GOTO 4140 3540 'FIELD-1 3580 'OUTPUT POSITION PARAMETERS 3620 OUT 238, 249: OUT 237, 0: OUT 236,128: OUT 236,0 'Y-ROW MSH
3660 OUT 238, 250: OUT 237, 0: OUT 236,128: OUT 236,0 'Y-ROW LSH
4140 OUT 236,80 'COMMAND RUN, LOAD-BAR ; PULSE-1 BRACKETING COMPUTATION PERIOD
4220 GOTO 2060 'LOOP BACK FOR NEXT FIELD 20000 END
BASIC PROGRAM LISTING LD.ASC 50 PRINT "ACCESSED "LD" FILE TO LOAD IMAGE MEMORY: REV.5/15/84 09:00"
55 INPUT "MURPHY (M) OR CAMILLE (C)";K200$ 100 INT1%=0: D%=0: K8%=1: K9%=1 112 PRINT: PRINT
II******************************************"
114 PRINT " SELECT OPERATION"
116 PRINT ••****************************************": PRINT
118 PRINT "RETURN TO OPERATING SYSTEM ... 0"
120 PRINT "SELECT OVERLAY FOR LOADING INTO IMAGE MEMORY ... 1"
122 PRINT "SELECT IMAGE TO BE LOADED INTO IMAGE MEMORY"
124 PRINT " CONCENTRIC SQUARE FRAMES 2"
126 PRINT " RECTANGLES AND LINES 3"
128 PRINT " SPIRALS 4"
130 PRINT " VIEWPORT COORDINATE SYMBOLS 5"
132 PRINT " PATTERN #6 6"
134 PRINT " PATTERN #7 7"
136 PRINT " SQUARE PATTERN 8"
138 PRINT " SQUARE FRAMES 9"
140 PRINT " PERIPHERAL SQUARES 10"
141 PRINT " PERIPHERAL TRIANGLES 11"
142 PRINT " HOUSE 12"
151 INPUT " SELECT OPERATION NUMBER";A20%
152 IF A20%<13 THEN 155
153 PRINT "****************": PRINT "IMPROPER SELECTION": PRINT '•***************"
154 GOTO 112
155 IF A20%>0 THEN 158
156 SYSTEM
158 ON A20% GOSUB 170, 4400, 4530, 5500, 4500, 7500, 8500, 9000, 9040, 9180, 9280, 11070
159 GOTO 112
170 PRINT: PRINT • ■ *******************************************"
171 PRINT " SELECT OVERLAY FOR LOADING INTO IMAGE MEMORY"
172 PRINT "****************************** PRINT
173 PRINT " RETURN TO MAIN MENU 0"
S UBSTITUTE SHEET
174 PRINT " SELECT RECTANGULAR IMAGE MEMORY PATTERN"
180 PRINT " HORIZONTAL BARS"
200 PRINT " 3-2-2 WIDTH BARS, INTENSITY VARATIONS . 1"
220 PRINT " 1-1-1 WIDTH BARS, MAXIMUM INTENSITY ... 2"
240 PRINT " LINEAR COUNT, ALL COLOR COMBINATIONS .. 8"
260 PRINT " SOLID SINGLE COLORED IMAGES"
265 PRINT " RECTANGLE 3"
270 PRINT " BACKGROUND 4"
400 PRINT " CHECKERBOARD"
420 PRINT " 4-COLORS 6"
440 PRINT " 2-COLORS 7"
442 PRINT » VARIABLE SINGLE COLORS"
443 PRINT " GREEN SAWTOOTH 10" 60 PRINT " CENTER ELEMENT"
480 PRINT " 9-PIXEL SQUARE 11"
482 PRINT " SELECT SLOPING LINE 12"
484 INPUT " SELECT PATTERN NUMBER";A5%
486 IF A5%>0 THEN 502
500 RETURN
502 IF A5%<13 THEN 520
503 PRINT "****************"• PRINT "IMPROPER SELECTION": PRINT "***************"
504 GOTO 170
520 IF A5%=3 OR A5%=4 OR A5%=12 THEN 523 ELSE 535
523 PRINT "COLOR CODE"
524 PRINT " BLACK 0"
526 PRINT " GREEN 1 TO 7"
527 PRINT " RED 8, 16, 24"
528 PRINT " BLUE 32, 64, 96"
529 INPUT " SELECT COLOR CODE SUM";INT1%
530 IF INT1%<128 THEN 535
531 PRINT:PRINT *****************************************
532 PRINT "IMPROPER COLOR CODE; ENTER COLOR CODE AGAIN"
533 PRINT »***************************************":PRINT
534 GOTO 523
535 IF A5%=11 THEN 2040
540 IF A5%=6 OR A5%=7 GOTO 560 ELSE 570
560 INPUT "CHECKERBOARD RESOLUTION, PIXELS PER SIDE";A6%
SUBSTITUTE SHEET
570 IF A5%=4 THEN 575 ELSE 580 575 A5%=3: XB%=0: YB%=0: XE%=511: YE%=511: GOTO 623 580 INPUT " START PIXEL COORDINATE";XB%,YB% 620 INPUT " STOP PIXEL COORDINATE";XE%,YE% 623 GOSUB 630 624 GOTO 170 630 /************************************************** 632 'SUBROUTINE TO OVERLAY A RECTANGLE 635 XB%=(XB%+1)*8: YB%=(YB%+1)*8 640 XE%=(XE%+1)*8: YE%=(YE%+1)*8 642' IF XB%=>8 AND XB%<XE% AND XE%=>8 AND XB%=<512*8 AND XE%=<512*8 THEN 643 ELSE 656
643' IF YB%=>8 AND YB%<YE% AND YE%=>8 AND YB%=<512*8 AND YE%=<512*8 THEN 660 ELSE 656
656' PRINT:PRINT "**************************************» 657' PRINT "IMPROPER PIXEL COORDINATES, ENTER PIXEL COORDINATES AGAIN"
658' PRINT -■***************************************»:PRINT 659' GOTO 580 660' PRINT: PRINT "***************************************•■ 665' PRINT " IMAGE MEMORY IS BEING LOADED" 'PRINT "ROW","COLOR INTENSITY"
666' PRINT "**********************************************"; PRINT
667 IF A5%=12 THEN 4200
690 XPS%=256: YPS%=0: XRP%=XB%-8
695 GOSUB 3000
700 FOR 0UTLP1%=YB% TO YE% STEP 8 'ROW LOOP
710 YRP%=OUTLPl%-8 'UPDATE TO NEXT ROW
711 XRP%=XB%-8
712 GOSUB 3000 'LOAD IMP REGISTERS
948 OUT 236,32 'SET SEQUENTIAL LOAD COMMAND
1230 'DETERMINE INTENSITY (INT1%)
1240 ON A5% GOTO
1260,1460,1720,1250,1250,1920,1980,1800,1250,1820
1250 PRINT "************* » : PRINT "SELECT A DIFFERENT IMAGE": PRINT ••************"
1260 IF D%<8 THEN 1340 'IMAGE PATTERN 1
1280 IF D%<32 THEN 1380 !-64-32-!-16-08-1-04-02-01-!
1300 IF D%<128 THEN 1420 ! BLUE ! RED ! GREEN !
1320 INT1%=0: D%=0: GOTO 1980
1340 INT1%=D% AND 7
1360 D%=D%+1: GOTO 1980
1380 INT1%=D% AND 24
1400 D%=D%+8: GOTO 1980
1420 INT1%=D% AND 96
1440 D%=D%+32: GOTO 1980
1460 A3%=FIX ( (OUTLPl%-8)/8) 'IMAGE PATTERN 2
1480 GOSUB 1520
1500 GOTO 1980
1520 '***** SUBROUTINE, MAXIMUM COLOR ********************
1540 A4%=A3% AND 3
1560* A7%=A4%+1
1580 ON A7% GOTO 1600,1620,1640,1660
1600 INT1%=0: GOTO 1680
1620 INT1%=7: GOTO 1680
1640 INT1%=24: GOTO 1680
1660 INT1%=96
1680 RETURN
1700
/********************************************************
1720 INT1%=INT1%: GOTO 1980 'PATTERN-3, SOLID COLOR
1800 K2%=(OUTLPl%-8)/8: INT1%= K2% AND 127: GOTO 1980
'PATTERN 8, LINEAR COUNT
1820 INT1%=K8%: K10%=K9% AND 1
1840 IF K10%=0 THEN 1920
1860 K8%=K8%+1 'UPCOUNT, ADD
1880 IF K8%<8 THEN 1980
1900 K9%=K9%+1: K8%=6: GOTO 1980
'CHANGE COUNT DIRECTION
1920 K8%=K8%-1 'DOWNCOUNT, SUBT
1940 IF K8%>0 THEN 1980
1960 K9%=K9%+1: K8%=2: GOTO 1980
1980 SP1%=INIT1% AND 1: SP2%= INIT1% AND 3: SP3%=INT1%
AND 7: SP4%=INT1% AND 15: SP5%=INT1% AND 31:
SP6%=INT1% AND 63: SP7%=INT1% AND 127
1985 OUT 238, 252: OUT 237, SP1%: OUT 237, SP2%: OUT 237, SP3%: OUT 237, SP4%: OUT 237,SP5%: OUT 237,SP6%: OUT 237, SP7%: OUT 237, INT1% 'DATA TO LOAD IN IMAGE MEMORY
1991 ON A5% GOTO 1994,1994,1994,1994,1994,1992,1993,1994,1994,1994
1992 A3%=FIX((2*0UTLP1%+INLP1%)/A6%): GOSUB 1520: GOTO 1994
1993 A3%=FIX((2*0UTLP1%+2*INLP1%)/A6%): GOSUB 1520: GOTO 1994
1994 FOR INLP1%=XB% TO XE% STEP 8 'PIXEL LOOP
1995 OUT 236,160: OUT 236,32
1996 NEXT INLP1%
1997 OUT 237, SP7%: OUT 237, SP6%: OUT 237, SP5%: OUT 237, SP4%: OUT 237,SP3%: OUT 237,SP2%: OUT 237, SP1%: OUT 237,0
'DATA TO LOAD IN IMAGE MEMORY
1999 IF K200$="M" THEN
2000 A8%=INP (93): A8%=A8% AND 2: IF A8%=0 THEN 2009 'OPERATOR RESET
2001 A8%=INP (92): GOTO 2006
2002 A8%=INP (1): A8%=A8% AND 2: IF A8%=0 THEN 2009 'OPERATOR RESET
2003 A8%=INP (0)
2006 A9%=A8% XOR 155 IF A9%=0 THEN 100 'ESCAPE TO MENU
2007 A9%=A8% XOR 127 IF A9%=0 THEN 2008 ELSE 2009 'DELETE TO SYSTEM
2008 SYSTEM
2009 NEXT 0UTLP1%
2010' PRINT CHR$(7); :PRINT "MEMORY LOAD COMPLETE"
2020 RETURN 'RETURN TO OVERLAY MENU
2040 'PATTERN 11
2060 INT1%=7: K17%=(256-3)*8: K18%=(256+3)*8
2080 FOR 0UTLP1%=K17% TO K18% STEP 8
2100 OUT 238, 249 'Y-ROW MSH
2120 C%=FIX(OUTLPl%/64): OUT 237, C%: OUT 236,129:
OUT 236,1 2140 OUT 238, 250 'Y-ROW LSH
SUBSTITUTE SHEET
2160 C%=OUTLPl% AND 63: OUT 237, C%: OUT 236,129:
OUT 236,1 2180 FOR INLP1%=K17% TO K18% STEP 8 'PIXEL LOOP
2200 OUT 238, 246 'X-ROW MSH
2220 C%=FIX(INLPl%/64): OUT 237, C%: OUT 236,129:
OUT 236,1 2240 OUT 238, 247 'X-ROW LSH
2260 C%=INLP1% AND 63: OUT 237, C%: OUT 236,129:
OUT 236,1 2280 OUT 238, 252 'DATA TO LOAD IN IMAGE MEMORY
2300 OUT 237, INT1%: OUT 236,129: OUT 236,1 2320 NEXT INLP1% 2340 NEXT 0UTLP1% 2360 0UTLP1%=(256-5)*8
2380 OUT 238, 249 'Y-ROW MSH
2400 C%=FIX(OUTLPl%/64) : OUT 237, C%: OUT 236,129:
OUT 236,1 2420 OUT 238, 250 'Y-ROW LSH
2440 C%=0UTLP1% AND 63: OUT 237, C%: OUT 236,129:
OUT 236,1 2460 K17%=(256-6)*8: K18%=(256)*8
2480 FOR INLP1%=K17% TO K18% STEP 8 'PIXEL LOOP
2500 OUT 238, 246 'X-ROW MSH
2520 C%=FIX(INLPl%/64): OUT 237, C%: OUT 236,129:
OUT 236,1 2540 OUT 238, 247 'X-ROW LSH
2560 C%=INLP1% AND 63: OUT 237, C%: OUT 236,129:
OUT 236,1 2580 OUT 238, 252 'DATA TO LOAD IN IMAGE MEMORY
2600 OUT 237, INT1%: OUT 236,129: OUT 236,1 2620 NEXT INLP1% 2640 GOTO 2000
3000 * ************** SUBROUTINE TO OUTPUT POSITION AND SLOPE PARAMETERS
3001 OUT 236,0 'D0A5 TURNED OFF TO DISABLE SEQUENCING DURING LOADING OF REGISTERS
3002 'SLOPE SCALE FACTOR=256*PIXELS/STEP
3003 'POSITION SCALE FACTOR =8*PIXELS
SUBS TITUTE s
3004 XPSM%=FIX(XPS%/64): XPSL%=XPS% AND 63
3005 OUT 238,242: OUT 237,XPSM%: OUT 236,128: OUT 236,0 'X-PIXEL SLOPE MSH
3006 OUT 238,243: OUT 237,XPSL%: OUT 236,128: OUT 236,0 'X-PIXEL SLOPE LSH
3007 YPSM%=FIX(YPS%/64): YPSL%=YPS% AND 63
3008 OUT 238,245: OUT 237,YPSM%: OUT 236,128: OUT 236,0 'Y-PIXEL SLOPE MSH
3009 OUT 238,244: OUT 237,YPSL%: OUT 236,128: OUT 236,0 'Y-PIXEL SLOPE LSH
3010' OUT 236, 0 'SUBROUTINE ENTRY POINT 3020 XRPM%=FIX(XRP%/64): XRPL%=XRP% AND 63 3091 YRPM%=FIX(YRP%/64): YRPL%=YRP% AND 63 'FORMAT POSITION OUTPUTS
3095 OUT 238,249: OUT 237,YRPM%: OUT 236,128: OUT 236,0 'Y-ROW MSH (Y-PIXEL MSH)
3096 OUT 238,250: OUT 237,YRPL%: OUT 236,128: OUT 236,0 'Y-ROW LSH (Y-PIXEL LSH)
3097 OUT 238,246: OUT 237,XRPM%: OUT 236,128: OUT 236,0 'X-ROW MSH (X-PIXEL MSH)
3098 OUT 238,247: OUT 237,XRPL%: OUT 236,128: OUT 236,0 'X-ROW LSH (X-PIXEL LSH)
3690 RETURN
4200 *******************************************************
4210 'DRAW A LINE
4220 DX=XE%-XB%: DY=YE%-YB%
4221 DTG=0
4222 IF DX=0 AND DY=0 THEN 4228 4224 IF ABS(DX)>ABS(DY) THEN 4227
4226 YPS%=(DY*256)/ABS(DY): XPS%=(DX*256)/ABS(DY) : DTG=ABS(DY): GOTO 4228
4227 YPS%=(DY*256)/ABS(DX): XPS%=(DX*256)/ABS(DX) : DTG=ABS(DX)
4228 XRP%=XB%-8: YRP%=YB%-8 4255 GOSUB 3000
4270 OUT 238, 252: OUT 237, INT1%
'DATA TO LOAD IN IMAGE MEMORY 4273 OUT 236,32 'SET SEQUENTIAL LOAD COMMAND
SUBSTITUTE SHEET
4274 DTG=DTG+8
4276 IF DTG>8 THEN 4288
4287 OUT 236,160: OUT 236,32: GOTO 4305
4288 FOR INLP1=8 TO DTG STEP 8 'PIXEL LOOP 4290 OUT 236,160: OUT 236,32 4300 NEXT INLP1
4305 OUT 236,0 'RESET SEQUENTIAL LOAD COMMAND
4350 RETURN
4400 /***************************************************
4410 INIT1%=7: XB%=225: YB%=255: YPS%=0: XPS%=256
4420 FOR 0UTLP1%=1 TO 10
4435 XRP%=XB%: YRP%=YB%
4437 XB%=XB%-1: YB%=YB%+1
4440 DX=2*0UTLP1%+1
4470 GOSUB 3000
4480 OUT 238, 252: OUT 237, INT1%
T " -.TA TO LOAD IN IMAGE MEMORY
4484 OUT 236,32 'SET SEQUENTIAL LOAD COMMAND
4488 FOR INLP1=8 TO DX STEP 8 'PIXEL LOOP
4492 OUT 236,160: OUT 236,32
4493 NEXT INLP1
4495 OUT 236,0 'RESET SEQUENTIAL LOAD COMMAND
4496 NEXT 0UTLP1%
4497 RETURN
4500 '****************************************************
4510 'BLACK BACKGROUND WITH COORDINATE SYMBOLS 4520' A5%=3: INT1%=0: XB%=0: YB%=0: XE%=511: YE%-=511: GOSUB 630
4522 A5%=12: INT1%=3: XB%=0: YB%=0: XE%=0: YE%=511: GOSUB 630
4523 A5%=12: INT1%=3: XB%=0: YB%=0: XE%=511: YE%=0: GOSUB 630
4524 A5%=3: INT1%=3: XB%=252: YB%=252: XE%=258: YE%=258: GOSUB 630
4525 A5%=3: INT1%=3: XB%=250: YB%=250: XE%=260: YE%=260: GOSUB 630
4526 A5%=3: INT1%=3: XB%=0: YB%=0: XE%=10: YE%=10: GOSUB 630
SUBSTITUTE SHEET
4527 RETURN
4530 '*****************************************************
4531 'RECTANGLE AND LINE PATTERN
4540 A5%=3: INT1%=2 : XB%=100: YB%=400: XE%=200:
YE%=500: GOSUB 630 4550 A5%=1: XB%=400: YB%=100: XE%=500:
YE%=200: GOSUB 630
4555 A5%=10: XB%=100: YB%=100: XE%=200: YE%=200: GOSUB 630
4556 A5%=12: INT1%=24: XB%=0: YB%=0: XE%=511: YE%=511: GOSUB 630
4557 A5%=12: INT1%=24: XB%=0: YB%=511: XE%=511: YE%=0: GOSUB 630
4561 RETURN
5500 /****************************************************
5510 'SPIRAL LINES
5535 A5%=12: INT1%=24: XB%=0: YB%=0: XE%=10000:
YE%=200: GOSUB 630 5540 A5%=12: INT1%=96: XB%=0: YB%=511: XE%=30000:
YE%=200: GOSUB 630 5561 RETURN 6500 /***************************************************
6520 A5%=3: INT1%=96: XB%=0: YB%=0: XE%=511:
YE%=511: GOSUB 630 6530 A5%=3: INT1%=24: XB%=100: YB%=500: XE%=200:
YE%=400: GOSUB 630 6550 A5%=1: XB%=500: YB%=100: XE%=400:
YE%=200: GOSUB 630
6560 A5%=10: XB%=100: YB%=100: XE%=200: YE%=200: GOSUB 630
6561 RETURN
7500 /***************************************************
7520 A5%=3: INT1%=96: XB%=0: YB%=0: XE%=511:
YE%=511: GOSUB 630 7530 A5%=3: INT1%=24: XB%=100: YB%=500: XE%=200:
YE%=400: GOSUB 630 7535 A5%=12: INT1%=24: XB%=0: YB%=0: XE%=511:
YE%=511: GOSUB 630
SUBSTITUTE SHEET
7540 A5%=12 : INT1%=24 : XB%=0 : YB%=511 : XE%=511 :
YE%=0: GOSUB 630 7550 A5%=1: XB%=500: YB%=100: XE%=400:
YE%=200: GOSUB 630
7560 A5%=10: XB%=100: YB%=100: XE%=200: YE%=200: GOSUB 630
7561 RETURN
8500 /*************************************************** 8520 A5%=3: INT1%=96: XB%=0: YB%=0: XE%=511:
YE%=511: GOSUB 630 8530 A5%=3: INT1%=24: XB%=100: YB%=500: XE%=200:
YE%=400: GOSUB 630 8535 A5%=12: INT1%=24: XB%=0: YB%=0: XE%=511:
YE%=511: GOSUB 630 8540 A5%=12: INT1%=24: XB%=0: YB%=511: XE%=511:
YE%=0: GOSUB 630 8550 A5%=1: XB%=500: YB%=100: XE%=400:
YE%=200: GOSUB 630
8560 A5%=10: XB%=100: YB%=100: XE%=200: YE%=200: GOSUB 630
8561 RETURN
9000 /******************************************************
9001 A5%=3: INT1%=7: XB%=128: YB%=128: XE%=256: YE%=256: GOSUB 630
9010 A5%=3: INT1%=16: XB%=256: YB%=128: XE%=384:
YE%=256: GOSUB 630 9020 A5%=3: INT1%=96: XB%=256: YB%=256: XE%=384:
YE%=384: GOSUB 630
9030 A5%=3: INT1%=24: XB%=128: YB%=256: XE%=256: YE%=386: GOSUB 630
9031 RETURN
9032 /*******************************************************
9040 A5%=3: INT1%=32: XB%=0: YB%=0: XE%=511:
YE%=511: GOSUB 630 9050 A5%=3: INT1%=7: XB%=104: YB%=104: XE%=127:
YE%=407: GOSUB 630 9060 A5%=3: INT1%=7: XB%=104: YB%=104: XE%=407:
YE%=127: GOSUB 630
-
9070 A5%=3 : INT1%=7 : XB%=104 : YB%=384 : XE%=407 :
YE%=407: GOSUB 630 9080 A5%=3: INT1%=7: XB%=384: YB%=104: XE%=407:
YE%=407: GOSUB 630 9090 A5%=3: INT1%=24: XB%=150: YB%=150: XE%=173:
YE%=361: GOSUB 630 9100 A5%=3: INT1%=24: XB%=150: YB%=150: XE%=361:
YE%=173: GOSUB 630 9110 A5%=3: INT1%=24: XB%=150: YB%=338: XE%=361:
YE%=361: GOSUB 630 9120 A5%=3: INT1%=24: XB%=338: YB%=150: XE%=361:
YE%=361: GOSUB 630 9130 A5%=3: INT1%=96: XB%=196: YB%=196: XE%=219:
YE%=315: GOSUB 630 9140 A5%=3: INT1%=96: XB%«196: YB%=196: XE%=315:
YE%=219: GOSUB 630 9150 A5%=3: INT1%=96: XB%=196: YB%=292: XE%=315:
YE%= * 315: GOSUB 630 9160 A5%=3: INT1%=96: XB%=292: YB%=196: XE%=315:
YE%=315: GOSUB 630
9170 A5%=3: INT1%=7: XB%=242: YB%=242: XE%=269: YE%=269: GOSUB 630
9171 RETURN
9172 '********************************************************
9180 A5%=3: INT1%=96: XB%=0: YB%=0: XE%=511:
YE%=511: GOSUB 630 9190 A5%=1: XB%=96: YB%=96: XE%=159:
YE%=159: GOSUB 630 9200 A5%=1: XB%=352: YB%=352: XE%=415:
YE%=415: GOSUB 630 9210 A5%=10: XB%=96: YB%=352: XE%=159:
YE%=415: GOSUB 630 9220 A5%=10: XB%=352: YB%=96: XE%=415:
YE%=159: GOSUB 630 9230 A5%=3: INT1%=24: XB%=224: YB%=224: XE%=287:
YE%=287: GOSUB 630 9240 A5%=12: INT1%=7: XB%=159: YB%=159: XE%=224:
YE%=224: GOSUB 630
9250 A5%=12 : INT1%=7 : XB%=287 : YB%=287 : XE%=352 :
YE%=352: GOSUB 630 9260 A5%=12: INT1%=7: XB%=159: YB%=352: XE%=224:
YE%=287: GOSUB 630
9270 A5%=12: INT1%=7: XB%=287: YB%=224: XE%=352: YE%=159: GOSUB 630
9271 RETURN
9272 /*******************************************************
9280 A5%=3: INT1%=96: XB%=0: YB%=0: XE%=511:
YE%=511: GOSUB 630 9300 A5%=12: INT1%=7: XB%=5: YB%=6: XE%=252:
YE%=253: GOSUB 630 9310 A5%=12: INT1%=7: XB%=259: YB%=260: XE%=506:
YE%=507: GOSUB 630 9320 A5%=12: INT1%=7: XB%=5: YB%=507: XE%=252:
YE%=260: GOSUB 630 9330 A5%=12: INT1%=7: XB%=259: YB%=253: XE%=506:
YE%=6: GOSUB 630 9340 A5%=12: INT1%=96: XB%=5: YB%=5: XE%=252:
YE%=252: GOSUB 630 9350 A5%=12: INT1%=96: XB%=259: YB%=259: XE%=506:
YE%=506: GOSUB 630 9360 A5%=12: INT1%=96: XB%=5: YB% * =506: XE%=252:
YE%=259: GOSUB 630 9370 A5%=12: INT1%=96: XB%=259: YB%=252: XE%=506:
YE%=5: GOSUB 630 9380 A5%=12: INT1%=24: XB%==5: YB%=4: XE%=252:
YE%=251: GOSUB 630 9390 A5%=12: INT1%=24: XB%=259: YB%=258: XE%=506:
YE%=505: GOSUB 630 9400 A5%=12: INT1%=24: XB%=5: YB%=505: XE%=252:
YE%=258: GOSUB 630 9410 A5%=12: INT1%=24: XB%=259: YB%=251: XE%=506:
YE%=4: GOSUB 630 9420 A5%=3: INT1%=7: XB%=0: YB%=0: XE%=511:
YE%=0: GOSUB 630 9430 A5%=3: INT1%=7: XB%=0: YB%=0: XE%=0: YE%=511: GOSUB 630
SUBSTITUTE SHEET
9440 511: YB%=0: XE%=511:
9450 0: YB%=511: XE%=511!
9460 1: YB%=1: XE%=510:
9470 1 : YB%=1 : XE%=1 :
9480 510: YB%=1: XE%=510:
9490 1: YB%=510: XE%=510:
9500 2: YB%=2: XE%=509:
9510 2: YB%=2 : XE%=2 :
9520 509: YB%=2 : XE%=509 :
9530 2: YB%=509: XE%=509:
9540 3: YB%=3: XE%=508:
9550 3 : YB%=3 : XE%=3 :
9560 508: YB%=3: XE%=508:
9570 3: YB%=508: XE%=508:
9580 =4: YB%=4: XE%=507:
9590 4; YB%=4 : XE%=4 :
9600 507: YB%=4: XE%=507:
9610 YB%=507: XE%=507:
9620 5: YB%=5: XE%=506:
SUBSTITUTE SHEET
9630 A5%=3 : INT1%=24 : XB%=5 : YB%=5: XE%=5:
YE%=506: GOSUB 630 9640 A5%=3: INT1%=24: XB%=506: YB%=5: XE%=506!
YE%=506: GOSUB 630 9650 A5%=3: INT1%=24: XB%=5: YB%=506: XE%=506:
YE%=506: GOSUB 630 9660 A5%=12: INT1%=7: XB%=192: YB%=128: XE%=319:
YE%=128: GOSUB 630 9670 A5%=12: INT1%=96: XB%=193: YB%=129: XE%=318:
YE%=129: GOSUB 630 9680 A5%=12: INT1%=24: XB%=194: YB%=130: XE%=317:
YE%=130: GOSUB 630 9690 A5%=12: INT1%=7: XB%=200: YB%=136: XE%=311:
YE%=136: GOSUB 630 9700 A5%=12: INT1%=96: XB%=201: YB%=137: XE%=310:
YE%=137: GOSUB 630 9710 A5%=12: INT1%=24: XB%=202: YB%=138: XE%=309:
YE%=138: GOSUB 630 9720 A5%=12: INT1%=7: XB%=208: YB%=144: XE%=303:
YE%=144: GOSUB 630 9730 A5%=12: INT1%=96: XB%=209: YB%=145: XE%=302:
YE%=145: GOSUB 630 9740 A5%=12: INT1%=24: XB%=210: YB%=146: XE%=301:
YE%=146: GOSUB 630 9750 A5%=12: INT1%=7: XB%=216: YB%=152: XE%=295:
YE%=152: GOSUB 630 9760 A5%=12: INT1%=96: XB%=217: YB%=153: XE%=294:
YE%=153: GOSUB 630 9770 A5%=12: INT1%=24: XB%=218: YB%=154: XE%=293:
YE%=154: GOSUB 630 9780 A5%=12: INT1%=7: XB%=224: YB%=160: XE%=287:
YE%=160: GOSUB 630 9790 A5%=12: INT1%=96: XB%=225: YB%=161: XE%=286:
YE%=161: GOSUB 630 9800 A5%=12: INT1%=24: XB%=226: YB%=162: XE%=285:
YE%=162: GOSUB 630
9810 A5%=12: INT1%=7: XB%=232: YB%=168: XE%=279:
YE%=168: GOSUB 630
SUBSTITUTE SHEET
233: YB%=169: XE%=278:
234: YB%=170: XE%=277:
240: YB%=176: XE%=271:
241: YB%=177: XE%=270:
242: YB%=178: XE%=269:
248: YB%=184: XE%=263:
249: YB%=185: XE%=262.
250: YB%=186: XE%=261;
255: YB%=192: XE%=256:
255: YB%=420: XE%=256:
250: YB%=426: XE%=261:
249: YB%=427: XE%=262:
248: YB%=428: XE%=263:
242: YB%=434: XE%=269:
241: YB%=435: XE%=270:
240: YB%=436: XE%=271:
234: YB%=442: XE%=277 :
233: YB%=443: XE%=278:
232: YB%=444: XE%=279:
10020 A5%=12 : INT1%=7 : XB%=226 : YB%=450 : XE%=285 :
YE%=450: GOSUB 630 10030 A5%=12: INT1%=96: XB%=225: YB%=451: XE%=286:
YE%=451: GOSUB 630 10040 A5%=12: INT1%=24: XB%=224: YB%=452: XE%=287:
YE%=452: GOSUB 630 10050 A5%=12: INT1%=7: XB%=218: YB%=458: XE%=293:
YE%=458: GOSUB 630 10060 A5%=12: INT1%=96: XB%=217: YB%=459: XE%=294:
YE%=459: GOSUB 630 10070 A5%=12: INT1%=24: XB%=216: YB%=460: XE%=295:
YE%=460: GOSUB 630 10080 A5%=12: INT1%=7: XB%=210: YB%=466: XE%=301:
YE%=466: GOSUB 630 10090 A5%=12: INT1%=96: XB%=209: YB%=467: XE%=302:
YE%=467: GOSUB 630 11000 A5%=12: INT1%=24: XB%=208: YB%=468: XE%=303:
YE%=468: GOSUB 630 11010 A5%=12: INT1%=7: XB%=202: YB%=474: XE%=309:
YE%=474: GOSUB 630 11020 A5%=12: INT1%=96: XB%=201: YB%=475: XE%=310:
YE%=475: GOSUB 630 11030 A5%=12: INT1%=24: XB%=200: YB%=476: XE%=311:
YE%=476: GOSUB 630 11040 A5%=12: INT1%=7: XB%=194: YB%=482: XE%=317:
YE%=482: GOSUB 630 11050 A5%=12: INT1%=96: XB%=193: YB%=483: XE%=318: YE%=483: GOSUB 630
11059 A5%=12: INT1%=24: XB%=192: YB%=484: XE%=319: YE%=484: GOSUB 630
11060 A5%=3: INT1%=24: XB%=248: YB%=248: XE%=263: YE%=263: GOSUB 630
11061 RETURN
11062 /********************************************************
11070 A5%=3: INT1%=7: XB%=0: YB%=0: XE%=511:
YE%=256: GOSUB 630 11080 A5%=3: INT1%=96: XB%=0: YB%=256: XE%=511:
YE%=511: GOSUB 630
S U B S
11090
12000
12010
12020
12030
12040
12050
12060
12070
12080
12090
13000
13010
13020
13030
13040
13050
13060
13070
SUBS ffiture sπε^
13080 A5%=12: INT1%=0: XB%=256: YB%=129: XE%=432:
YE%=129: GOSUB 630 13090 A5%=12: INT1%=0: XB%=352: YB%=128: XE%=352:
YE%=256: GOSUB 630 14000 A5%=12: INT1%=0: XB%=352: YB%=127: XE%=352:
YE%=255: GOSUB 630 14010 A5%=12: INT1%=0: XB%=352: YB%=129: XE%=352:
YE%=257: GOSUB 630 14020 A5%=12: INT1%=0: XB%=392: YB%=296: XE%=432:
YE%=256: GOSUB 630 14030 A5%=12: INT1%=0: XB%=392: YB%=295: XE%=432:
YE%=255: GOSUB 630 14040 A5%=12: INT1%=0: XB%=392: YB%=297: XE%=432:
YE%=257: GOSUB 630 14050 A5%=12: INT1%=0: XB%=432: YB%=256: XE%=432:
YE%=128: GOSUB 630 14060 A5%=12: INT1%=0: XB%=432: YB%=255: XE%=432:
YE%=127: GOSUB 630 14070 A5%=12: INT1%=0: XB%=432: YB%=257: XE%=432:
YE%=129: GOSUB 630 14080 A5%=12: INT1%=127: XB%=12: YB%=480: XE%=12:
YE%=496: GOSUB 630 14090 A5%=12: INT1%=127: XB%=12: YB%=496: XE%=16:
YE%=500: GOSUB 630 15000 A5%=12: INT1%=127: XB%=16: YB%=500: XE%=32:
YE%=500: GOSUB 630 15010 A5%=12: INT1%=127: XB%=32: YB%=500: XE%=36:
YE%=496: GOSUB 630 15020 A5%=12: INT1%=127: XB%=36: YB%=496: XE%=36:
YE%=480: GOSUB 630 15030 A5%=12: INT1%=127: XB%=36: YB%=480: XE%=32:
YE%=476: GOSUB 630 15040 A5%=12: INT1%=127: XB%=32: YB%=476: XE%=16:
YE%=476: GOSUB 630 15050 A5%=12: INT1%=127: XB%=16: YB%=476: XE%=12:
YE%=480: GOSUB 630 15060 A5%=12: INT1%=127: XB%=6: YB%=476: XE%=12: YE%=480: GOSUB 630
SUBSTITUTE SH ET
15070 A5%=12: INT1%=127: XB%=6: YB%=500: XE%=12:
YE%=496: GOSUB 630 15080 A5%=12: INT1%=127: XB%=12: YB%=506: XE%=16:
YE%=500: GOSUB 630 15090 A5%=12: INT1%=127: XB%=36: YB%=506: XE%=32:
YE%=500: GOSUB 630 16000 A5%=12: INT1%=127: XB%=42: YB%=500: XE%=36:
YE%=496: GOSUB 630 16010 A5%=12: INT1%=127: XB%=36: YB%=470: XE%=32:
YE%=476: GOSUB 630 16020 A5%=12: INT1%=127: XB%=12: YB%=470: XE%=16: -
YE%=476: GOSUB 630
16030 A5%=12: INT1%=127: XB%=42: YB%=476: XE%=36: YE%=480: GOSUB 630
16031 RETURN
16032 /*******************************************************
40000 END
S UBSTITUTE SHEET
LEGEND
I => INSTRUCTION
0 => OPERAND
SPATIAL DIMENSION CONFIGURATION TABLES
A SINGLE SPATIAL DIMENSION CONFIGURATION
1-1-1-1-0-1-1-1-1-0-1-1-1-1-0-1-1-1-1-0-I-I-I-ϊ-O-I-I-I- I-0-1-1-1-1-0-1-1-1-1-0-1-
B-Λ-Λ-A-B-B-Λ-Λ-Λ-B-B-Λ-A-A-B-B-A-Λ-Λ-B-B-Λ-A-Λ -B-B-Λ-Λ-A-B-B-A-A-A-B-B-A-A-A-B-B- SPEEDUP = 5B/(3A + 2B) = (5x3.5)(3x1 + 2x3.5) = 17.5/(3 + 7) = 1.75 TIMES
MULTIPLE SPATIAL DIMENSIONS CONFIGURATION INSTRUCTION SEGMENT AND DATA SEGMENT IN SAME DIMENSION (SAME AS IA ABOVE) I-1-1-1-0-1-1-1-1-0-1-1-1-1-0-1-1-1-1-0-1-1-1-1-0-1-1-1-1-0- 1-1-1-1-0-1-1-1-1-0-1-
B-Λ-Λ-A-B-B-Λ-A-Λ-B-B-Λ-Λ-Λ-B-B-Λ-Λ-A-B-B-Λ-Λ- Λ-B-B-A-A-A-8-B-A-A-Λ-B-B-A-Λ-A-β-B- SPEEDUP = 5B/(3A + 2B) = (5x3.5)(3x1 + 2x3.5) = 17.5/(3 + 7) = 1.75 TIMES
MULTIPLE SPATIAL DIMENSIONS CONFIGURATION
INSTRUCTION SEGMENT AND DATA SEGMENT IN DIFFERENT DIMENSIONS
I-I-I-I-O-I-I-I-I-0-1-1-1-1-0-1-1-1-1-0-1-1-1-1-0-1-1-1-1 -0-I-I-I-I-O-I-I-I-I-O-I-
A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A -A-A-A-A-A-A-A-A-A-A-A-A- SPEEDUP = 5BΛ5Λ + OB) = (5x3.5)(5x1 + 0x3.5) = 17.5/(5 + 0) = 3.4 TIMES
SUBSTITUTE SHEET
STAGGERED CONFIGURATION TABLES
A SINGLE STAGGERED SPATIAL DIMENSION CONFIGURATION
I-I-I-I-O-I-I-I-I-0-1-1-1-1-0-1-1-1-1-0-1-1-1-1-0-1-1-I-1 -O-J-I-I-I-O-X-I-I-t-0-1- B-A-A-A-B-B-Λ-A-Λ-B-B-Λ-Λ-A-B-B-A-A-A-B-B-A-A-A-B-B-A-A- A-B-B-A-A-A-B-B-A-A-A-B-B- SPEEDUP = 5B/(3A + 2B) = (5x3.5)(3x1 + 2x3.5) = 17.5/(3 + 7) = 1.75 TIMES
TWO STAGGERED SPATIAL DIMENSIONS CONFIGURATION
I-I-I-I-O-I-I-I-I-O-I-I-I-I-O-I-I-I-I-O-I-I-I-I-O-I-I-I-I -O-I-I-I-I-O-I-I-I-I-O-l- B-A-Λ-A-Λ-Λ-A-Λ-Λ-B-B-A-A-Λ-A-Λ-Λ-Λ-Λ-B-B-Λ-A-A- -A-A-A-A-B-B-A-A-A-A-Λ-A-A-A-B-B- SPEEDUP - 10B/(8A + 2B) ■ (10x3.5)(8x1 + 2x3.5) = 35/(8 + 7) = 2.3 TIMES
FOUR STAGGERED SPATIAL DIMENSIONS CONFIGURATION I - 1 - 1 - 1 -0- I-I-I-I-O-I-I-I-I -0- 1 - 1 - 1 - 1 -0- I-I-I-I-O-I-l-I-I-O-I-I-I-I-O-I-I-I-I-O-I-
B-A-A-A-A-A-A-Λ-A-Λ-A-A-Λ-A-A-A-Λ-Λ-Λ-B-B-A-A-Λ-A- A-Λ-A-A-A-A-A-A-A-A-A-A-A-A-B-B- SPEEDUP ** ■ 20B/(18A + 2B) = (20x3.5)(18x1 + 2x3.5) = 70/(18 + 7) = 2.8 TIMES
EIGHT STAGGERED SPATIAL DIMENSIONS CONFIGURATION I-I-I-I-O-I-I-I-I-O-I-I-I-I-O-I-I-I-I-O-I-I-I-I-O-I-I-I-I-O- I-I-I-I-O-I-I-I-l-O-I- B-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A-A- A-A-A-A-A-A-A-A-A-B-B- SPEEDUP = 40B/(38A + 2B) = (40x3.5)(38x1 + 2x3.5) = 140/(38 + 7) = 3.1 TIMES
SUBSTITUTE SHEE-
CONCLUSION From the above description it will be apparent that there is thus provided an invention of the character described possessing the particular features of advantage before enumerated as desirable, but which obviously is susceptible to modification in its form, method, mechanization, operation, detailed construction and arrangement of parts without departing from the principles involved or sacrificing any of its advantages. While in order to comply with the statute, the invention has been described in language more or less specific as to structural features, it is to be understood that the invention is not limited to the specific features shown, but that the means, method, and construction herein disclosed comprise the preferred from of various modes of putting the invention into effect, and the invention is, therefore, claimed in any of its forms or modifications within the legitimate and valid scope of the appended claims.
SUBSTITUTE SHEET
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