IMPROVED PHASE REFERENCE GENERATOR WITH

DRIVING POINT VOLTAGE ESTIMATOR

FOR RESISTANCE WELDING

PCT PRIORITY APPLICATIONS

[0001] The present application claims the benefit of priority of U.S. Provisional Application No. 60/727,425 filed October 17, 2005, the contents of which are incorporated herein by reference. The present application also claims the benefit of priority of U.S. Patent Application No. 11/517,747 filed September 8, 2006, entitled "Phase Reference Generator with Driving Point Voltage", and U.S. Patent Application No. 11/517,687 filed September 8, 2006, entitled "Method and System for Estimating Driving Point Voltage".

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT [0002] N/A

TECHNICAL FIELD

[0003] The invention generally relates to a system and method for providing improved thyristor timing in AC phase controllers, and more particularly to a system and method for providing improved timing for resistance welding operations.

BACKGROUND OF THE INVENTION

[0004] A phenomenon that can limit the performance of thyristor or silicon controlled rectifier (SCR) based phase controllers in general, and resistance weld controllers in particular, is the distortion of the observed voltage waveform caused by the presence of line impedance when current flows. In phase controlled resistance welders, precise control of current over a few line cycles is required in order to generate the energy profile required to establish a strong, secure weld. To accomplish this requires that the firing pulses which trigger the SCRs be timed precisely relative to the AC power source applied to it. A modern resistance weld control must therefore maintain an accurate internal time base with respect to the power source. This internal time base is referred to herein as a phase reference generator (PRG).

[0005] Traditionally, weld controls maintain an internal time base on which phase locked loop systems employ a phase discriminator based on the zero-crossings of an observed waveform to generate timing information on which an internal time base can be generated. However, this method is inadequate for generating a time base for resistance welding applications because the flow of current into the weld causes distortion in the zero-crossings of the voltage waveform as observed by the weld control at its terminals. [0006] Several attempts have been made to provide improved welding conditions. U.S. Patent Number 5,856,920 discloses a method of estimating the phase error between two independent time bases. In particular, this patent discloses a method of estimating the phase error between an internally maintained time base (phase reference generator), and an observed sinusoidal voltage. The method of estimating the phase error between the two independent time bases comprises dividing the time base of the internal phase reference generator into "quadrants", and integrating the volt-time area of the observed absolute value of the sinusoidal voltage over the quadrants. In one implementation, the phase estimator computes the ratio of the difference between the sum of the volt-time area of the first two quadrants and the sum of the last two quadrants, divided by the total sum of all quadrants. In another implementation, the volt-time area of two adjacent quadrants are used to estimate the phase error.

[0007] U.S. Patent Number 5,869,800 discloses the use of a phase distortion compensated time base for a welder control to improve the timing of firing the thyristors in a solid state phase controlled resistance welder control.

[000S] U.S. Patent Number 5,963,022 discloses a method and apparatus for synchronizing an internal time base to an observed line voltage based on observing the voltage, estimating the phase distortion generated by coupling of the AC line voltage source to the load as a result of the load being energized from the phase angle firing control in the presence of line impedance and adjusting the internal phase reference generator in response to the estimated phase distortion. This patent also discloses observing the line voltage waveform under a condition in which the system is not conducting current, freezing the phase reference generator frequency and phase for one or more line cycles in which the system is conducting current to observe the phase error resulting from estimating the phase under conditions of current flow without compensating for the observed phase error, then biasing the phase error in subsequent phase error samples by the observed amount while

compensating for the biased phase error. The method described in this patent makes a very noticeable improvement in the performance of a resistance weld control, especially when the intent of the control is to generate a sequence of current pulses of the same current. However, in certain circumstances, particularly those in which the current ramps from an initial value to a final value over a number of line cycles the performance, while better than a system without such compensation, is not as accurate as it could be.

[0009] U.S. Patent No. 6,013,892 discloses a phase controlled weld system that computes a firing sequence based on estimated models of line impedance, open circuit line voltage, and an estimated relation between the load current and conduction angle and the mathematical relation between firing angle, conduction angle and load circuit power. The system also uses measured values received in real time to modify the nominal firing angle. This system is also not as accurate as it could be.

[0010] The present invention is provided to solve the problems discussed above and other problems, and to provide advantages and aspects not provided by prior systems of this type. A full discussion of the features and advantages of the present invention is deferred to the following detailed description, which proceeds with reference to the accompanying drawings.

SUMMARY OF THE INVENTION

[0011] The present invention is a method and system for improved timing in AC phase controllers, such as resistance weld controllers. Specifically, the improved method and system can be used with an EQ5400 AC Resistance Weld Control. This weld control is utilized in resistance welding applications, including but not limited to automobile body assembly.

[0012] The present invention substantially improves the performance of a resistance weld control's ability to track the driving point voltage ( the open circuit voltage that would be observed if no current were flowing) by estimating in real time the driving point voltage waveform under all conditions. There is no longer the need to "freeze" the phase and frequency of the phase reference generator at initiation of a weld. The present system ' accomplishes this by assuming a simple circuit model for the power source and distribution system providing power to the weld control comprising an ideal, time varying driving point voltage source, a series line resistance and a series line reactance. Using the estimated parametric values of line resistance and line reactance, an estimated driving point volt-time

area is computed and used in the conventional manner as the basis for generating a phase reference generator that automatically tracks the power source under all conditions. [00133 According to one embodiment of the invention, the system estimates the driving point voltage magnitude and phase in an AC phase controlled resistance weld application relative to an internal phase reference generator. The system provides improved tracking of the driving point voltage phase while welding. This results in more accurate timing of thyristor firing points and consequently better current accuracy during a resistance welding operation. The system also provides improved run to run load impedance estimates, resulting in more accurate feed-forward control. The system also provides improved line voltage compensation while welding.

[0014] In accordance with another embodiment of the invention, a method and system for estimating a driving point voltage of a resistance weld system is provided. The method comprises the steps of periodically sampling a supplied voltage and a supplied current of a system to obtain a plurality of sets of a sampled voltage value and a sampled current value. The sampled voltage and current is utilized for creating a volt-time area of the sampled voltage, a current time area of the sampled current, and a current difference time area of the sampled current. The method further includes determining if current is one of flowing and not flowing, and taking a first set of a sampled voltage value and a sampled current value when the current is not flowing and taking a second set of a sampled voltage value and a sampled current value when the current is flowing. From these two sets of values, the method includes creating an estimated line resistance and an estimated line reactance of the system.

[0015] The method further comprises the step of using the volt-time area of the sampled voltage, the current time area of the sampled current, the current difference time area of the sampled current, the estimated line resistance and the estimated line reactance to create an estimated driving point voltage time area. The estimated driving point voltage time area is used to drive the firing of a thyristor of a resistance weld device.

[0016] The steps of creating a volt-time area of the sampled voltage, creating a current time area of the sampled current, and creating a current difference time area of the sampled current can be accomplished on a quadrant by quadrant basis. In this instance, the step of periodically sampling a supplied voltage and supplied current of a system comprises sampling the supplied voltage and current a set number of times for each quadrant.

[0017] The method can also include various provisions to ensure the estimated phase reference is in phase with the supplied voltage. In this regard, the method includes using the estimated driving point voltage time area to compute a phase error between the supplied voltage and an internal phase reference. The phase error can then be utilized in creating a driving point voltage waveform model in synch with the supplied voltage. [0018] Circuitry in a weld control of the resistance weld system, and components for measuring the supplied voltage and current, are utilized by the system to implement the method steps. The circuitry can include a digital signal processor having firmware and/or software necessary to implement the functions described.

[0019] In accordance with another embodiment of the invention, a method for estimating a driving point voltage for timing the firing elements of a resistance weld device comprises measuring a supplied voltage and a supplied current of a power distribution system at a plurality of predetermined intervals, estimating a line resistance and a line reactance based on the measured values of the supplied voltage and the supplied current, and estimating the driving point voltage based on the measured values of supplied voltage and the supplied current, and on the estimated line resistance and line reactance. The estimated driving point voltage is used by a phase reference generator as the timing basis for providing a firing signal to a thyristor of a resistance weld device.

[0020] The method can further include calculating a voltage time area of the supplied voltage from the measured values of the supplied voltage, calculating a current time area of the supplied current from the measured values of the supplied current and, calculating a current difference time area of the supplied current from the measured values of the supplied current. The voltage time area, the current time area and the current difference time area are used for estimating the driving point voltage.

[0021] The step of estimating a line resistance and a line reactance can comprise measuring a first set of a sampled voltage value and a sampled current value when the current is not flowing, measuring a second set of a sampled voltage value and a sampled current value when the current is flowing and, creating an estimated line resistance and an estimated line reactance of the system based on the first set of a sampled voltage value and a sampled current value and the second set of a sampled voltage value and a sampled current value. The estimated line resistance and line reactance can also be utilized in estimating the driving point voltage.

[0022] The method can further include estimating a phase error between the supplied voltage and the estimated driving point voltage. The estimated phase error can be used to determine the difference in phase between an internal time base and the phase of the estimated driving point voltage

[0023] In accordance with another aspect of the invention, a method for estimating a driving point voltage of a resistance weld system is provided. The method includes periodically sampling a supplied voltage and a supplied current of a system to obtain sets of a sampled voltage value and a sampled current value. This can include taking a first, second and third set of a sampled voltage value and a sampled current value, and computing a current difference value for each of the first, second and third sets. The method further includes creating an estimated line resistance and an estimated line reactance of the system based on the first set of a sampled voltage value, a sampled current value and computed current difference value, the second set of a sampled voltage value, a sampled current value and computed current difference value, and the third set of a sampled voltage value, a sampled current value and computed current difference value.

[0024] The method can also include taking one of the sampled sets when the current is not flowing (i.e., equals zero). This can include the steps of determining if the current is flowing or not flowing, and sampling the voltage when the current is not flowing. Choosing this data set can simplify some of the calculations involved in determining the driving point voltage.

[0025] In accordance with a further embodiment of the invention, a phase reference generator for tracking the driving point voltage waveform of a power distribution system for use in a resistance weld control is provided. The phase reference generator comprises a digital signal processor configured to include: a digital volt-time area generator to generate a volt-time area of an observed voltage; a digital current-time area and current-difference-time area generator to generate a current-time area of an observed current and a current-difference- time area of the observed current; a line impedance estimator; and, a driving point voltage area estimator configured to receive values from the digital volt-time area generator, the digital current-time area generator and current-difference-time area generator, and the line impedance estimator and generate estimates of the driving point voltage. The phase reference generator can be used to provide an output signal to fire a resistance welder.

[0026] The phase reference generator further comprises an analog to digital converter for converting each of the observed voltage and the observed current from an analog signal to a digital signal. The phase reference generator also includes an interval timer which. triggers an analog to digital conversion of the observed voltage and observed current. [0027] The phase reference generator can also include a phase error estimator. The phase error estimator is configured to estimate the phase difference between the estimated driving point voltage and a timing cycle generated by the phase reference generator. The phase error estimator is implemented in firmware of the digital signal processor once for every timing cycle generated by the phase reference generator.

[0028] The phase reference generator further comprises a compensator configured to adjust a frequency of the timing cycle to move the timing cycle toward a synchronous phase with the estimated driving point voltage. To accomplish this, the compensator either increases the frequency of the timing cycle when the timing cycle lags the estimated driving point voltage or decreases the frequency of the timing cycle when the timing cycle leads the estimated driving point voltage.

[0029] The phase reference generator can further include a quadrant generator. The quadrant generator is configured to provide an indication of a current quadrant of the timing cycle.

[0030] In accordance with another embodiment of the invention, a weld control for a resistance weld system is provided. The weld control comprises a phase reference generator configured to provide an estimated driving point voltage of a supplied voltage and generate a signal for firing a thryristor of the weld system during a welding operation. The weld control also includes a voltmeter function coupled to the phase reference generator and an input line to provide sampled values of the input line voltage and, a current-meter function coupled to the phase reference generator and the input line to provide sampled values of the line current. [0031] The phase reference generator can comprise a digital signal processor. The digital signal processor can include firmware and/or software configured to function as a digital volt-time area generator, a digital current-time area and current-difference-time area generator, a line impedance estimator and a driving point volt-area estimator. The digital volt-time area generator generates an estimate of the input line voltage based on the sampled values of the input line voltage. The digital current-time area and current-difference-time

area generator generates an estimate of the line current and the difference of the line current from the sampled values of the line current.

[0032] The digital signal processor further includes a line impedance estimator. The line impedance estimator is configured to generate an estimate of the line resistance and line reactance based on measured input line voltage, measured line current and computed first difference of the line current.

[0033] The digital signal processor further includes a driving point volt-time area estimator. The driving point volt-time area estimator is configured to provide an estimate of the driving point volt-time area based on the estimate of the input line voltage, the estimate of the line current and the difference of the line current, the line resistance and the line reactance.

[0034] The digital signal processor further includes a quadrant generator for providing a phase reference generator timing cycle having a frequency. Additionally, the digital signal processor includes a phase error estimator to estimate the phase error between the driving point voltage estimate and the internal system timing cycle. Based on the estimated phase error, the digital signal processor utilizes a compensator for adjusting the frequency of the timing cycle to bring the timing cycle in synchronization with the driving point voltage. [0035] In accordance with a further embodiment of the invention, a digital phase reference generator for use in a weld control is disclosed. The digital phase reference generator comprises an interval timer configured to trigger an analog to digital conversion of a sampled input line voltage and a sampled input line current on a reoccurring basis. The input line voltage and current are from a power distribution system. The digital phase reference generator further comprises a digital signal processor configured to run an interrupt routine initiated by each completion of the analog to digital conversion of a sampled input line voltage and a sampled input line current wherein a predetermined number of interrupt routines defines a timing cycle, the digital signal processor further configured to generate a volt-time area estimate of the input line voltage, a current-time area estimate of the input line current and a current-difference-time area estimate of the input line current, and a line impedance estimate. The digital signal processor is configured to provide a driving point volt-time area estimate of the input line voltage. The driving point volt-time area estimate is used as the basis for computing the error between the timing of the phase reference generator and the driving point voltage. The phase reference generator is used as the timing basis of for

the firing of thyristors of a resistance welding system. Unlike a prior art system in which the phase reference generator timing period is held constant for the first few cycles of welding while the system determines the phase error caused by the distortion of the driving point voltage due to line impedance, a system incorporating the invention disclosed herein can continue to track the driving point voltage even under conditions of rapidly varying weld current.

[0036] Other features and advantages of the invention will be apparent from the following specification taken in conjunction with the following drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

(0037] To understand the present invention, it will now be described by way of example, with reference to the accompanying drawings in which:

FIG. 1 is a block diagram of a phase reference generator in accordance with an embodiment of the present invention;

FIG. 2 is a diagram defining the quadrants of a phase reference generator cycle, when the phase reference generator is properly synchronized with the observed line voltage waveform;

FIG. 3 is a block diagram of a phase reference generator compensator control system utilized in the phase reference generator of FIG. 1 ;

FIG. 4 is a flow chart of a quadrant generator;

FIG. 5 is a block diagram of a digital volt-time area generator utilized in the phase reference generator of FIG. 1 ;

FIG. 6 is a block diagram of a digital current-time area generator utilized in the phase reference generator of FIG. 1 ;

FIG. 7 is a block diagram of a driving point volt-time area estimator utilized in the phase reference generator of FIG. 1 ;

FIG. 8 is a block diagram of a line impedance estimator utilized in the phase reference generator of FIG. 1;

FIG. 9 is a block diagram of a run to run (R2R) autoregressive filter utilized in the line impedance estimator of FIG. 9;

FIG. 10 is a logic flow chart of a line impedance supervisor utilized in the phase reference generator of FIG. 1 ;

FIG. 11 is a block diagram of a phase error estimator utilized in the phase reference generator of FIG. 1;

FIG. 12 is a state diagram of a phase reference generator state machine

FIG. 13 a table showing phase reference generator settings for a resistance weld control;

FTG. 14 is a quadrant diagram of a phase reference generator cycle showing the relation between the PRG and the input voltage sinusoid where the PRG is synchronized with the input voltage sinusoid;

FIG. 15 is a quadrant diagram of a phase reference generator cycle showing the relation between the PRG and an input voltage sinusoid where the PRG is not synchronized with the input voltage sinusoid;

FIG. 16 is a table of parametric values of a sampled data system;

HG. 17 is a stem plot showing sample values of the voltage waveform for parametric values in the table of Figure 16;

FIG. 18 is a circuit diagram of an ideal circuit model for a weld control;

FIG. 19 is a circuit diagram of a system model of a weld control with line impedance;

FIG. 20 is a table of parametric values for the circuit of Figure 19;

FIG. 21 is waveforms of the source volts, observed volts and weld current showing distortion caused by the presence of line impedance;

FIG. 22 is a lumped parameter circuit diagram of a resistance weld control and associated power distribution system;

FIG. 23 is a line voltage waveform as a function of time and a line voltage waveform as a function of observation angle;

FIG. 24 is a simplified model of a weld circuit assuming no line impedance;

FIG. 25 is a voltage waveform resulting from firing a thyristor with respect to time and a voltage waveform resulting from firing a thyristor with respect to an observed angle;

FIG. 26 is a current waveform resulting from applying the parametric values of the table of Figure 27 to a weld current equation; and,

FIG. 27 is a table of parametric values for a weld current equation.

DETAILED DESCRIPTION

[0038] While this invention is susceptible of embodiments in many different forms, there is shown in the drawings and will herein be described in detail preferred embodiments of the invention with the understanding that the present disclosure is to be considered as an exemplification of the principles of the invention and is not intended to limit the broad aspect of the invention to the embodiments illustrated.

[0039] Referring to Figure 1, a block diagram is disclosed of the components of a phase reference generator ("PRG") 10 for providing improved tracking of a line voltage to create more accurate firing points of a resistance welding device. The present invention is preferably implemented in connection with a resistance weld control, such as the EQ5400 AC Resistance Weld Control sold by the Square D Company, to create a PRG timing cycle to match the driving point voltage of a power supply and distribution system. The EQ5400 AC Resistance Weld control can be modified to include the features of the present invention as discussed below.

[0040] In an embodiment utilizing a EQ5400 AC Resistance Weld Control, a commercially available digital signal processor (DSP), preferably Model TMS320F2407A, manufactured by Texas Instruments, is employed to perform an analog to digital conversion of external voltage and current signals, digital signal processing, and timing generation. In this embodiment, PRG timing is controlled by a hardware interval timer included in the DSP, the interval of which can be set under software control. When the timer period expires, it begins timing a new period, and simultaneously triggers the analog to digital conversion of a sequence of selected signals, independent of the present processing being performed by the DSP. This includes signals responsive to the instantaneous weld current and the voltage observed at the input terminals of the weld control. Completion of analog to digital conversion sequence triggers an interrupt in the DSP, which then suspends it's processing for a time and executes a firmware interrupt routine. In this way, time critical operations can be accomplished in a timely manner and at regular intervals. A feature of the particular DSP employed is that the interval timer is "shadowed", meaning that when a new period is provided to the interval timer, this new period is applied at the expiration of the present interval.

[0041] In the EQ5400 AC Resistance Weld Control implementation, the PRG cycle is defined as the interval spanned by 128 interrupts generated by the DSP in accordance with

the above description. Each PRG cycle is divided into four quadrants, labeled ql, q2, q3 and q4 in Figure 2. Each quadrant represents an interval of 32 DSP interrupts. From the above discussion, it is clear that the time period of a PRG cycle is variable, and it is this feature that allows the PRG cycle to synchronize with an observed sinusoidal waveform as shown in Figure 2 and discussed below. As the system is designed, the interrupt interval is constant within a PRG cycle.

[0042] The objective of the PRG 10 is to synchronize the internal quadrants with the observed voltage source such that if the PRG cycle is synchronized with a purely sinusoidal voltage of constant magnitude, the quadrants correspond to the following (shown visually in Figure 2): Quadrant 1 represents the interval between the negative to positive zero crossing of the sinusoid and the positive peak of the sinusoid; Quadrant 2 represents the interval between the positive peak of the sinusoid and the positive to negative zero crossing of the sinusoid; Quadrant 3 represents the interval between the positive to negative zero crossing of the sinusoid and the negative peak of the sinusoid; and Quadrant 4 represents the interval between the negative peak of the sinusoid and the negative to positive zero crossing of the sinusoid.

[0043] Figure 1 is a top level block diagram showing the closed loop system of the present invention to model, estimate and track the driving point voltage. The various components shown can be implemented in the firmware and/or software of the DSP, and may include additional the use of additional circuitry, and are sometimes referred to herein as functions of the PRG. The index "n", appearing in various quantities refers to the nth PRG cycle after a reference cycle, normally the first cycle after the system is powered. It should be understood that this index, n, is a mathematical entity, incorporated to make use of difference equations in a standard, mathematical format. The value of the interrupt period, Ts(n+1), for the next PRG cycle is supplied by a PRG Compensator 1. Inputs to the PRG Compensator 1 are the phase error sequence e(n), generated by a Phase Error Estimator 2, and the "state" of the PRG, labeled PRGState(n), generated by a PRG State Machine 3. The PRG Compensator 1 is executed once per PRG cycle, sometime in the interval of quadrant 4 in Figure 2, when all inputs required to execute the PRG Compensator for the present PRG cycle are available

[0044] Interrupt period Ts(n+1), generated by the PRG Compensator 1, is furnished to a Quadrant Generator 4 which is a function resident in DSP firmware. Quadrant Generator 4 is

executed once per interrupt. It declares to the system the present quadrant value, q, in the set {ql,q2,q3,q4}. It also furnishes a universal logical semaphore, NQ, indicating the beginning of a new quadrant when set TRUE. The value of this logical semaphore is known universally to all functions in the PRG system. Quadrant Generator 4 also manages the timing of application of the new interrupt period, setting it at the transition between q4 of the present PRG cycle and ql of the next PRG cycle. The PRG quadrant value q is an input to the PRG State Machine 3, a digital volt-time area generator 5, labeled Digital VTA in Figure 1, and a digital current-time and current-difference-time generator 6, labeled Digital ITA Generator in Figure 1.

[0045] Digital VTA Generator 5 is executed once per DSP interrupt and generates an estimate of the observed volt-time area, V _wc TA(q,n) for each quadrant from the quantized, digitized samples of the continuous analog line voltage waveform V _wc (t) generated by the analog to digital converter function of the DSP. Digital VTA Generator 5 also generates an estimate of the observed absolute volt-time area, AV _wc TA(q,n) in a manner to be described subsequently.

[0046] Digital ITA Generator 6 is also executed once per DSP interrupt and generates quadrant by quadrant current-time estimates ITA(q,n) and estimates of the area of first difference of current, δITA(q,n), from the quantized, digitized samples of instantaneous current generated by the analog to digital converter function of the DSP. [0047] Driving Point VTA Estimator function 7 is executed once per quadrant and utilizes the V _wc TA(q,n) values furnished by Digital VTA Generator function 5 and the ITA(q,n) and δITA(q,n) values furnished by Digital ITA Generator function 6, along with estimated values of line resistance, R ^* _inc (/«) and X ^* _eq (in) , furnished by a Line Impedance Estimator function 8 to generate quadrant estimates of driving point volt-time area, V _dp TA(q.n). The significance of the index "m" in λ _; ^* _M (m) and X] _eq (m) will be discussed subsequently. The quadrant estimates of V _< j _p TA(q,n) are fed to a Phase Error Estimator function 2, executed once per PRG cycle when the driving point volt-time area estimates are available from quadrants 2 and 3. Phase Error Estimator 2 computes an estimate of phase error between the estimated open circuit source voltage waveform and the present timing of the PRG quadrants. The output of Phase Error Estimator 2 is a sequence of phase error values, e(n), one per PRG cycle, which feeds the PRG Compensator 1, closing the loop.

[0048] As described above, the estimated sequences of line resistance, R ^* n _ne (m) and reactance, X ie _q (m) are furnished by Line Impedance Estimator function 8. This Line Impedance Estimator function utilizes the outputs furnished by Digital VTA function 5 and Digital ITA function 6, along with an external knowledge of when to compute a new line impedance estimate furnished by a Line Impedance Supervisor function 9 to be described subsequently.

[0049] In the block diagram of Figure 1, the Line Impedance Supervisor function 9 furnishes a software semaphore command, LI_COMPUTE to Line Impedance Estimator function 8 to determine on which PRG cycles to compute a new estimate of line impedance parameters R n _ne (m) and X u _q (m). The index "m" in the line impedance parameter values refers to the mth such update of line impedance parameters from initialization of the system since power was first applied.

[0050] Figure 3 shows a system block diagram description of the PRG Compensator function 1 of Figure 1. In the EQ5400 AC Resistance Weld Control, this function is implemented totally in DSP firmware. PRG Compensator function 1 is executed once per PRG cycle, at a time when the most recent phase error estimate, e(n) is available, after quadrant q3, and in time for Quadrant Generator 4 to set the elementary sample rate for the next PRG line cycle., Ts(n+1).

[0051] PRG Compensator 1 attempts to drive the estimated phase error between the PRG timing cycle and the estimated driving point voltage signal by slightly increasing the internal PRG frequency to "catch up" with the estimated driving point voltage signal if the PRG timing cycle phase lags the estimated driving point voltage signal, or decreasing the internal PRG frequency to allow the estimated driving point voltage signal to "catch up" with the PRG timing if the estimated phase error shows the PRG timing cycle leads the external driving point voltage signal.

[0052] Mathematically, there are three internal state variables maintained by PRG Compensator function 1, labeled xθ(n), xl(n) and x2(n) in Figure 3. State variable x2(n) represents the accumulated sum of the phase error since the PRG Compensator 1 has been initialized in a manner to be described subsequently. The state variables xθ(n) and x(n) are incorporated to permit the response of the system to be completely controlled, accommodating for the fact that the phase error is estimated at a point that is at the center of a present PRG cycle, whereas the consequent adjustment in timing is made at the quadrant

transition between q4 of the present cycle and ql of the next cycle. Using well understood techniques of modern linear control theory, it can be shown that when coupled in to the system, such a system is completely controllable in a control system sense, and that the response of the system can be set to any reasonable value desired. [0053] In matrix format, the form of the state difference equations describing PRG Compensator function 1 are:

with the output Ts(n+1) given by:

Ts{n + l) = Ts _nom + [K2 Kl (2) where kxO, kxl, ki, kp, and K2 are control system parameters, and the value Ts _nOm represents the expected elementary sample period. The specific values of these constants are dependent upon the state of PRG Generator 10, furnished by PRG State Machine 3 in the state variable PRGState(n+l). Discussion of the actual parametric values used as a function of the system state is deferred to the description of the PRG State Machine.

[0054] Quadrant Generator 4 is also implemented in DSP firmware and is executed on each DSP interrupt of the system. Figure 4 is a flowchart showing the process of the Quadrant Generator 4. The Quadrant Generator 4 maintains an internal counter, SC, of DSP interrupts from the beginning of the present PRG quadrant. Upon entry at 401 on the kth DSP interrupt since the beginning of the present PRG quadrant, Quadrant Generator 4 first increments the value of the SC counter in process block 402. In decision block 403, the DSP compares the value of the counter SC to a constant value SPQ, indicating the number of DSP interrupts per quadrant. In the implementation of the EQ5400 AC Resistance Weld Control, SPQ is 32. If the value of SC is not greater than or equal to SPQ, control passes to control block 404, in which the new quadrant semaphore, NQ is set FALSE, indicating that this elementary sample does not represent the beginning of a new quadrant. The value of this semaphore is known universally to the system. Once the NQ semaphore has been set FALSE

in 404, the system sets the present quadrant value, q(k) to the previous value, q(k-l) in process block 405, since the quadrant has not changed.

[0055] In decision block 406, the Quadrant Generator 4 looks for the specific condition of the last DSP interrupt in quadrant q4. This condition is indicated by both of the following conditions true: q{k) = qA (3) and

SC = SPQ -I (4)

[0056] If either of these conditions is FALSE, the routine exits normally at 408. If both of these conditions are true, the Quadrant Generator 4 first loads the hardware interval counter of the DSP with the value Ts(n+1) obtained from PRG Compensator 1. This occurs in process block 407, prior to exiting normally at 408. As discussed previously, this new setpoint value will be loaded to set the DSP interrupt period the next time the interval counter reaches it's setpoint value, which is the correct instant to set the DSP interrupt period for the next PRG cycle.

[0057] Referring back to decision block 403, if the sample count SC is greater than or equal to the constant value SPQ, it is time to transition to a new quadrant and process blocks 409, 410 and 411 are executed sequentially. In process block 409, the counter SC is reset to zero. In process block 410, the value of the quadrant, q(k) is incremented. In process block 411, the value of the new quadrant semaphore, NQ is set TRUE, indicating to the rest of the PRG functions that this DSP interrupt represents the first DSP interrupt of a new quadrant. [0058] Control then passes to decision block 412 in which the quadrant value q(k), incremented in process block 410 is compared to determine if the new quadrant value falls within the range {ql, q2, q3, q4). If so, the routine exits normally at 408. If not, the quadrant value q(k) is set to ql, indicating the beginning of a new PRG cycle. Control then exits normally at 408.

[0059] Figure 5 is a block diagram of the Digital VTA Generator 5. The Digital VTA Generator 5 generates volt-time area estimates of the line voltage at the observed line input of the weld control for each quadrant q e {ql,q2,q3,q4} of the PRG, labeled V _wc TA(q,n) in Figure 1, as well as a quantity AV _wc TA(q,n) for each quadrant, formed by first taking the absolute value of the observed weld voltage and generating a trapezoidal accumulation. In

the EQ5400 AC Resistance Weld Control, the Digital VTA Generator function is implemented in a combination of analog electronic circuits, digital electronic circuits and digital signal processing firmware. The raw analog voltage line voltage input signal, V _wc (t), is that signal appearing at the power input of the weld control. This is a power line voltage signal, typically with a nominal value of 480 Volts RMS in an automobile body shop in the United States. The power system is also capable of supplying very large currents to anything connected to it. Accordingly, to both reduce the voltage observed by the system to the levels that low voltage digital and analog electronics can manage while simultaneously limiting the potential current that can flow into the digital VTA function to safe levels, a voltage attenuator circuit 21 is incorporated in the design. In the EQ5400 AC Resistance Weld Control, the voltage attenuator circuit comprises two commercially available precision high- voltage voltage divider networks, based on thick film technology. The output of the voltage attenuator circuit 21 is a signal V _wca (t), responsive to V _wc (t), but attenuated by a factor of approximately 125:1, so that a sinusoidal voltage signal of 480 V RMS at the input appears as a sinusoidal signal of about 3.84 V RMS at the output of the attenuator. [0060] The analog signal V _wca (t) feeds an anti-aliasing filter 23, which serves to band limit the signal that is fed to A/D converter function 25. It is well understood in the study of sampled data systems that to faithfully represent an analog signal as a sequence of digital samples, the sampled signal must be band limited to no more than half the sampling frequency, or the phenomenon commonly called aliasing will result, confounding the result. In the EQ5400 AC Resistance Weld Control, a six pole elliptical filter is implemented in analog hardware to band limit the sampled signal. The attenuated, band limited representation of the line voltage signal is labeled V _wcf (t) in Figure 5. [0061] Analog to digital converter function 25 is integral to the DSP, and samples the signal V _WCf {t), responsive to V _wc (0 once per DSP interrupt. The sample period for a given PRG cycle is Ts(n), computed by PRG Compensator 1 and set by Quadrant Generator 4. The analog to digital converter quantizes each sample into a 10 bit number in a form that can be used by the DSP. This numeric sequence is labeled V _wcs (k) in Figure 5. In the EQ5400 AC Resistance Weld Control, 128 such samples are taken per PRG cycle. [0062] The sampled and quantized sequence V _wcs (k) generated by the A/D converter function of the DSP feeds a functional block labeled trapezoidal integrator / accumulator 27 in Figure 5. This function is implemented in DSP firmware and estimates the volt-time area

of each quadrant by accumulating samples over the quadrant using the trapezoidal integration rule:

V _wc TA{q,n) = ₍₅₎ where the index j refers to the elementary samples V _wcs (k), but referenced to the beginning of the nth PRG cycle. This function creates four such estimates per PRG cycle. Previous quadrant estimates are complete and a new estimate begun upon receipt of the universal new quadrant semaphore NQ from Quadrant Generator 4. To generate the sequence AV _wc TA(q,n), supplied by the digital VTA function and used by PRG state machine 3, the mathematical absolute value of the sequence V _wcs TA(k) is first taken (shown by reference no.: 28). The output of this absolute value function, labeled AV _wcs TA(k) feeds another trapezoidal integrator 29 operating in a manner identical to that which generates the sequence V _wcs TA(k). The output of trapezoidal integrator 29 is the sequence AV _wc TA(q,n), shown in Figure 1.

[0063] Figure 6 shows a block diagram of Digital ITA Generator function 6 of the PRG system 10, to estimate the current-time area (ITA) and current time-difference area (δITA) of each PRG quadrant. As was the case with the Digital VTA Generator function 5, this function is implemented in a combination of electronic hardware and DSP firmware. In the EQ5400 AC Resistance Weld Control, weld current is passed through a commercially available passive AC current transformer 31 with an associated burden resistor. The current transformer 31 generates a secondary current proportional to the main weld current passing through it's aperture. When this current passes through the burden resistor attached across the transformer secondary, a voltage V _ct (t) is generated. As in the Digital VTA Generator function, the voltage V _c ,(t) is filtered by an analog 6 pole elliptical anti-aliasing filter 32. The resulting band-limited signal is labeled V _clf (t) in Figure 6.

[0064] The band-limited signal Vc^t), responsive to the instantaneous weld current, is sampled by the DSP analog to digital converter 33, which is a separate analog to digital channel from that of the Digital VTA Generator function 5, but which operates in an identical manner and is sampled essentially at the same instant as that of Digital VTA Generator function 5, at the rate Ts(n) established by PRG compensator 1 and Quadrant Generator 4.

The sequence of numbers resulting from this sampling and quantization process is labeled i(k) in Figure 6.

[0065] The sequence i(k) directly feeds trapezoidal integrator/accumulator 35, which operates in a manner identical to that described in the Digital VTA Generator function 5, producing quadrant estimates of current-time area ITA(q,n), with q e {ql, q2, q3, q4}, one per PRG quadrant. The sequence i(k) also feeds a current difference function 37, which generates the sequence δi(k), according to:

Ai(k) = i(k)-i(k -l) (6)

[0066] This signal is fed to another trapezoidal integrator/accumulator 39, which also operates in a manner identical to that described in the Digital VTA Generator function 5, producing quadrant estimates of current-difference-time area, δITA(q,n) with q e {ql, q2, q3, q4}, one per PRG cycle quadrant.

[0067] Figure 7 is a block diagram description of the operation of Driving Point VTA Estimator function 7. This function is executed once per quadrant on the transition of one quadrant to another to produce quadrant open circuit VTA estimates V _dP TA(q,n) used by Phase Error Estimator 2. Once all of the data is available, the system executes the mathematics of Figure 7, which implements the equation:

V _dp TA{q,n) = V _w JA{q,n) + [R; _mt (m)xITA(q,n)] + [x;jm)xAITA{g,n)] (7)

[0068] Figure 8 is a block diagram of the Line Impedance Estimator function 8, which furnishes the line impedance estimates R ^* jj _ne (m) and X ^* i _eq (m) to Driving Point VTA Estimator 7. Line Impedance Estimator function 8 is executed conditionally at certain times, to update the estimates of line resistance and reactance. The command to perform an update is represented by the logical assertion of a signal LI_COMPUTE, which is asserted at times to be discussed subsequently by Line Impedance Supervisor function 9. The index m in the values R ^* π _ne (m) and X ^* i _eq (m) refers to the mth such commanded update of line impedance values.

[0069] In the implementation of the EQ5400 AC Resistance Weld Control, Line Impedance Estimator 8 continuously maintains a memory of the previous value of the observed VTA estimates for quadrants 2 and 3. These signals are represented in Figure 8 as the outputs of unit delay blocks 81 and 82, and are labeled V _wc TA(q2,n-l) and V _wc TA(q3,n- 1) respectively. Upon command, Line Impedance Estimator 8 generates a new estimate of

the line impedance values R ^* ι, _ne (m) and X ^* i _eq (m), as determined by assertion of the DLCOMPUTE signal. On this nth line cycle, when the LI_COMPUTE signal is asserted the values ITA(q2,n), ITA(q3,n), δITA(q2,n) and δITA(q3,n), all furnished by Digital ITA Generator 6, as well as the values V _wc TA(q2,n) and V _wc TA(q3,n), furnished by Digital VTA Generator 5, and the delayed volt-time area values VwcTA(q2,n-l) and VwcTA(q3,n-l) described above feed estimator matrix 83. Estimator matrix 83 produces outputs R(m) and X(m) according to the equation:

where R(m) and X(m) are the instantaneous estimates of resistance and inductive reactance respectively for the mth estimate. The mathematics behind this matrix equation will be derived subsequently.

[0070] Assumptions made in computing the line impedance estimate are 1) there is one and only one device loading the weld bus at a time and 2) the driving point voltage is a sinusoid and remains constant over the intverval on which the computation is based. However, it is recognized that an individual weld control has no knowledge a-priori of the presence or activity of other devices which may be drawing current from the weld power bus, and the instantaneous estimate made using equation (8) above may be in error if other equipment is loading the weld bus over the line cycles in which the estimate is made, violating one or both of the above assumptions To help alleviate this condition, each of the values R(m) and X(m) are filtered utilizing run to run (R2R) filters 85 and 87. A block diagram of the form of these identical filters is shown in Figure 9. The filters are auto- regressive filters having the general form:

.r(m + I) = (I -K _f )x(m) + K _f u(m), 0 ≤ K _f ≤ l y(m) = x(m + l) where u(m) is the input to the filter (R(m) or X(m) in Figure 8), x(m) is the internal state variable, K _f the filter constant, 0 < K _f ≤ 1 , and y(m) is the output of the filter, Rii _ne (m) ^* or

X _eq (m) ^* respectively in Figure 8.

[0071] The run to run filters tend to "smooth out" the errors that might be made in individual impedance estimates, and result in a more consistent estimate than that which would result from using the individual estimates R(m) and X(m). In practice, using the

unfiltered individual estimates R(m) and X(m) directly (which can be done by setting K _f =l) has yielded excellent results - the run to run filters are not necessary for the invention to work and should not be considered a limitation on the invention. However, for operation in a noisy environment such as an automobile body shop, it has been found experimentally that inclusion of these run to run filters with K _f = 0.25 provides an added measure of noise immunity against the condition in which the assumptions above have been violated. [0072] The function of Line Impedance Supervisor function 9, is to determine on which cycles of the PRG to execute Line Impedance Estimator function 8. In the present embodiment, the objective is to execute Line Impedance Estimator 8 on the first cycle in which current is flowing, following several cycles in which current has not been flowing. In a typical automotive application, a resistance weld control is normally idle for several seconds, while a part or an- entire automobile is moved into position to be welded. During this period, where no current is flowing, the PRG 10 can acquire the undistorted, driving point voltage wavefoπn of the power system. If it is assumed that the voltage waveform of the power source does not vary much from one cycle to another, then it can be assumed that the voltage wavefoπn on the last line cycle before welding is representative of the driving point voltage waveform of the power source on the first cycle in which welding has begun. The function of Line Impedance Supervisor function 9 is to monitor the system for this condition and trigger execution of Line Impedance Estimator function 8 when the appropriate condition is detected.

[0073] Figure 10 is a flowchart of Line Impedance Supervisor function 9, which is a DSP firmware entity executed once per PRG cycle. Integral to Line Impedance Supervisor function 9 is a static IDLE counter, used by Line Impedance Supervisor function 9 to determine when the system has been idle for a sufficient period to ensure the PRG is solidly tracking the power source voltage waveform. Referring to Figure 10, upon entry into the firmware logic at 1401 during line cycle n, the Line Impedance Supervisor function 9 first determines in decision block 1403 whether the system is welding during line cycle n. Assuming the system is not welding during line cycle n, flow is transferred to process block 1405, where an integral IDLE counter is incremented by the DSP. Once the counter is incremented, in decision block 1407 the resulting count is compared against an integer number NLI which is a design parameter indicating the minimum number of non-welding cycles required to ensure the PRG is accurately tracking the power source voltage. If the

value in the idle counter is greater than Nu, then the prerequisite number of non-welding cycles has been satisfied and the value in the count is set to NLI in process block 1409. Row transfers to process block 1411 in which the LJ_COMPUTE semaphore is set to a logic FALSE value, indicating to the line impedance estimator 7 that no update of line impedance should be performed.

[0074] If in decision block 1407 Line Impedance Supervisor function 9 determines that the value in the IDLE counter is less than or equal to NLI, control transfers directly to process block 1411 and the LI-COMPUTE semaphore is set to a logic FALSE value as above. Once process block 141 1 is executed, the routine exits at 1413 until it is again executed at the next PRG cycle.

[0075] Referring back to decision block 1403, if it is determined that weld current is flowing on weld cycle n, control passes to decision block 1415, in which the value in the IDLE counter is compared against the value N _LI . If it is determined that the value in the IDLE counter is not exactly Nu, then an insufficient number of non-weld cycles were detected to warrant a new estimate of line impedance. This condition exists when a pause between individual welds of less than Nu line cycles occurred, or simply because the system is presently in the middle of executing a weld. In either case, if an insufficient number of non-weld cycles is detected by the routine, the LI_COMPUTE semaphore is set to a logic FALSE state in process block 1417, and the IDLE counter value is set to zero in process block 1419.

[0076] If, in decision block 1415, the IDLE counter value is equal to Nu, then the conditions to execute and update of the line impedance estimate are satisfied. Control passes to process block 1421, in which the LI-COMPUTE semaphore is set TRUE. Once this has occurred, control passes to process block 1419 where the IDLE counter value is set to zero as above. Once process block 1419 is executed, the routine exits as above at 1413 until it is again executed at the next PRG cycle.

[0077] Figure 11 is an expanded block diagram description of Phase Error Estimator 2 of the PRG system. This function is implemented in DSP firmware, and is executed once per PRG cycle, during quadrant q4, after the driving point voltage estimates V _dp TA(q2,n) and Vd _P TA(q3,n) from quadrants 2 and 3 have been made by Driving Point Voltage Estimator 7. For each line cycle, n, this block utilizes the open circuit volt-time estimates from quadrants 2 and 3, Vd _P TA(q2,n) and V _dP TA(q3,n), furnished by Driving Point Voltage Estimator 7 to

estimate the error between the internal time base (i.e., PRG timing cycle) and estimated driving point voltage. The block diagram in Figure 11 implements the mathematical expression:

^{K }} V _dp TA(q2,n) -V _dp TA(q3,n)

How this expression approximates the error will be discussed subsequently. [0078] PRG State Machine 3 determines the state of the PRG, and guides the PRG through the process of initialization, when nothing is known regarding the relation between the PRG timing and the actual power system timing, to the point where the PRG is declared "synchronized" with the power system and welding can begin. Figure 12 shows a system state diagram of PRG State Machine 3. The output of PRG State Machine 3 is the PRG state variable PRGState(n), which takes a value in the set { NOSYNC, SYNCING.SYNC}. [0079] PRG State Machine 3 is implemented in DSP firmware and is executed when the PRG is in quadrant q4, after Phase Error Estimator 2 has been executed for the present PRG cycle. From the power-on state, labeled PON in Figure 12, the system state is immediately set to NOSYNC. When the system is in the NOSYNC state, nothing is assumed regarding the relation between the PRG quadrants and the observed line voltage waveform. The objective of the PRG 10 in the NOSYNC state is to observe the line voltage V _wc (t) and align the PRG quadrants such that the positive to negative zero crossing of V _wc (t) occurs near the transition from quadrant q2 to quadrant q3. That this condition exists is determined by satisfaction of the following three conditions:

[0080] Condition 1 : The sum of the quadrant absolute volt-time areas from the previous line cycle, AV _wc TA(q,n-l), q = 1,2,3,4, henceforth referred to as AVTA(n-l) is greater than a minimum value. This condition is required to ensure that the system is indeed tracking an actual voltage delivered by the power system of a minimum value, and not just random noise as a result of an open circuit condition in the power system. In the actual design of the EQ5400 AC Resistance Weld Control, the minimum AVTA required to satisfy this condition is the theoretical value that would be obtained by applying a sinusoidal voltage input of 30 Volts RMS, when the line voltage is properly synchronized with the PRG (however, other voltages may be used).

[0081] Condition 2: The value VφTA(q2,n) is positive, and the value V _dp TA(q3,n) is negative. This indicates that the zero crossing of the power waveform to be "tracked" occurs somewhere between the present quadrants q2 and q3.

[0082] Condition 3: The error value computed by the phase error estimator, e(n) is "small enough" to allow the PRG to begin closed loop acquisition. In the EQ5400 AC Resistance Weld Control, this value is approximately 22.5 degrees. [0083] When in the NOSYNC state, the EQ5400 AC Resistance Weld Control is not allowed to conduct current. One intended consequence of this is that the driving point voltage is identical to that observed by the system at the input terminals of the EQ5400 AC Resistance Weld Control. To accomplish nominal alignment between the PRG 10 and the input sinusoid, the PRG Compensator constants kxO, kxl, ki, kp and K2, shown in Figure 3 are set to zero and the values of state variables xθ(n), xl(n) and x2(n) forced and maintained at zero when the system is in the NOSYNC state, so the PRG 10 does not modify the interrupt sampling period from a nominal value TS _n0πv This results in a fixed PRG cycle frequency while in the NOSYNC mode.

[0084] The nominal, operating line frequency voltage of the weld control system is assumed known a-priori. For instance, it is known that a system intended to operate in North America operates at a nominal line frequency of 60 Hz., and that frequency will be quite accurately regulated by the power utility generating the power - generally well within +/- 0.2 Hz. When in the NOSYNC mode, the EQ5400 AC Resistance Weld Control utilizes a value of TS _nom that will generate a PRG frequency 1 Hz. less than the expected operating frequency. For example, for a system intended to operate at 60 Hz, TS _nom is set to 132 microseconds, which results in a PRG cycle frequency of approximately 59 Hz. Accordingly, for a condition in which the positive to negative zero crossing of the actual, observed line voltage occurs outside of quadrants q2 or q3, on each subsequent PRG cycle the zero crossing of the line voltage will occur earlier in the PRG cycle than on the previous PRG cycle, and will occasionally "wrap around" to the next PRG cycle. Eventually, the zero crossing will occur near the transition between q2 and q3 of the PRG. For the given conditions, assuming the line frequency is the nominal value, the estimated phase error should change by only 6 degrees per PRG cycle, ensuring that if condition 1 can be achieved and assuming that the observed waveform is actually sinusoidal in nature, the remaining conditions can be satisfied within 1/3 second under normal conditions. For a system

operating nominally at 50 Hz, TS _n o _m is selected such that the nominal PRG cycle frequency is approximately 49 Hz.

[0085] Once the above conditions have been satisfied, the PRG state machine declares the PRG to be in the SYNCO state. In this state, the value of TS _nom remains fixed at the

NOSYNC setting, but the constant kxO, kxl, ki, kp, and K2 are set to their operating values.

The table in Figure 13 provides the parametric values of the PRG compensator 1 presently used in the EQ5400 AC Resistance Weld Control for 60 Hz operation.

[0086] The values of state variables xθ(n), xl(n) and x2(n), shown in Figure 3 are explicitly initialized to zero, when the SYNCO state is first entered. Unlike the NOSYNC state, however, they are not maintained at zero, but are allowed to assume values in accordance with the operation of the PRG Compensator 1 previously discussed.

[0087] When operated in a closed loop manner in accordance with the PRG system 10 described herein, the parametric values chosen provide excellent system response with good disturbance rejection, driving the estimated phase error sequence, e(n), toward zero in response to reasonable power system line voltages, and establishing the relation between the

PRG and the observed power voltage waveform desired in Figure 2.

[0088] Once the PRG constant values have been established, and state variables initialized to zero, the PRG 10 is allowed to operate in the SYNCO state, computing corrections to the interrupt period, Ts(n+1) until one of three events occur:

[0089] (1) The observed error, e(n) is below a fixed threshold value for more than a fixed number of consecutive PRG cycles. (2) The observed error, e(n) is greater than the fixed threshold value for greater than a fixed number of consecutive PRG cycles. In the EQ5400

AC Resistance Weld Control, this fixed number is 30 for both cases above. (3) The observed total AVTA for the previous line cycle is less than the minimum value given in the description of the NOSYNC state above.

[0090] In the EQ5400 AC Resistance Weld Control, the established error threshold for the SYNCO state is approximately 1 1.25 degrees. If condition 1 is satisfied first, the PRG transitions to the SYNC state. If either condition 2 or 3 is satisfied first, the PRG transitions back to the NOSYNC state. It is noted that under "normal" operating circumstances, requiring that the error threshold condition be satisfied for 30 consecutive cycles establishes a very small phase error by the time the transition to "SYNC" is made. For a system operating at 60 Hz., this corresponds to ¹ A second of stable operation under normal conditions.

[0091] Upon transition from the SYNCO to the SYNC state, the values of the state variables xθ(n), xl(n) and x2(n) shown in Figure 3 are initialized to zero, and the value TS _nom is set to TS(n), the last generated interrupt period value from the SYNCO state. Under normal conditions, this new value of TS _nom generates a PRG cycle period very close to that of the line voltage, so the system now need only make minor corrections to the interrupt sample period for the PRG to maintain synchronization with the line voltage.

[0092] In the SYNC state, the EQ5400 AC Resistance Weld Control is permitted to weld.

Once in the SYNC state, the PRG remains in that state until one of two conditions occur:

[0093] Condition 1: The magnitude of the error estimate, e(n), exceeds approximately 22 degrees for greater than 5 consecutive PRG cycles, in which case the system transitions back to the SYNCO state. This allows the PRG to ride through any minor disturbance that may occur in the power system, while disabling welding and attempting to re-acquire synchronization with the line voltage if the disturbance is large.

[0094] Condition 2: The observed total AVTA over the previous line cycle is less than the minimum AVTA described in the NOSYNC state discussion above. If this occurs, the

PRG drops immediately back to the NOSYNC state and the system is initialized and operates per the description of the NOSYNC state above.

[0095] The Phase Reference Generator 10 in the weld timer provides the timing basis for firing of the thyristors. It also drives the timing of the RMS voltage estimator function

(digital voltmeter), as well as the RMS current estimator function (digital current meter). The method of phase error estimation is based on integrating portions of the observed input line voltage to the system.

[0096] The following discussion explores the mathematics that is useful in understanding the operation of the present invention in an AC resistance welding application.

[0097] In a mathematical circuit model of the power distribution system, it is assumed that the voltage generated by the power generation and distribution system can be modeled as an ideal driving point voltage source V _dp (t) of the form:

[0098] V _dp (ή = V _m (ήsin (2πfi + φ) (11) where f is the frequency, φ is the phase of the sinusoid relative to a reference time t=0, V _m (/) is the peak voltage, denoted as a function of time. At this point in the discussion, it is

recognized that V _m (t) is a time varying modulation term. Assumptions on the behavior of V _m (t) will subsequently be made that will simplify the analysis.

[0099] The objective of the Phase Reference Generator 10 of the present invention is to generate an internal time base that can continuously track the driving point voltage V _dp (/) such that the following two conditions hold: Condition 1: The fundamental period of the phase reference generator, T, corresponds to f in equation (0.11), i.e. f = 1/T; and, Condition 2: The observed phase error between the PRG and the voltage source V _dP (t) is zero at the positive to negative zero crossing of the sinusoidal waveform.

[00100] Referring to Equation (11), a fundamental assumption in the present analysis is that the input power source to the weld control is a sinusoidal source of fixed and closely known frequency, but unknown and fixed phase relative to the internal phase reference generator 10. It is also assumed that the voltage modulation term, V _1n (t) in (11) above is slowly varying, and is effectively a constant over the interval over which the calculations are based.

[00101] Phase Reference Generator 10 does not generate a waveform per-se, but the timing of the PRG can be visualized as a square wave of frequency twice that of the fundamental period of the sinusoid it is attempting to track. In this representation, one PRG cycle comprises two cycles of the square wave. This visualization is employed because in the actual implementation of the PRG in a digital signal processor, or DSP it is possible for the

DSP to generate the square wave as an output, so it can be observed relative to the sinusoid using an oscilloscope.

[00102] Figure 14 shows such a representation, along with the input sinusoid, assuming that the phase reference generator is in complete synchronization with the sinusoid. In this visualization, one can see four "transitions" of the phase reference generator for each cycle of the sinusoid, dividing the sinusoid into quadrants, labeled ql, q2, q3 and q4 in Figure 14. It is important in what follows to keep in mind that the "quadrants" are defined relative to the

PRG which may or may not be synchronized with the sinusoid.

[00103] An analog to digital converter function of the EQ5400 AC Resistance Weld

Control is, by design, synchronized with the PRG and takes a constant number of evenly spaced, samples of the line voltage waveform per internal PRG line cycle. In the actual design of the EQ5400 AC Resistance Weld Control, the analog to digital converter generates

128 such digitized voltage samples per PRG cycle, or 32 samples per quadrant. Assume there is a function resident in the system capable of generating the true, mathematical integral of voltage over each quadrant of the PRG. Of interest in this analysis is the volt-time area over quadrants q2 and q3, which represent the shaded areas VTA2 and VTA3 in Figure 14. Because a sinusoid has odd symmetry about the 180 degree point, one can visualize from Figure 14, that when the PRG is synchronized with the sinusoid, the volt-time areas VTA2 and VTA3 are of equal, but opposite sign, so if they are added, the net sum of the volt-time area is zero.

[00104] This is not the case when the PRG is not synchronized. Figure 15 shows a condition in which the positive to negative zero crossing of the input voltage lags the transition from q2 to q3 of the PRG by an angle ε. In this case, it is readily seen that the volt- time areas represented by VTA2 and VT A3 are not of equal magnitude. Comparing Figure 15 with Figure 14, one can visualize that when the PRG leads the input voltage, the computed ,magnitude of VTA2 will be larger than that when the PRG is synchronized, and that the computed magnitude VTA3 will be smaller than when it is synchronized. Accordingly, when VTA2 and VTA3 are added as signed quantities with VT A2 positive and VTA3 negative, the result is a positive quantity, indicating the leading characteristic of the PRG with respect to the input voltage. Similarly, it can be envisioned that if the PRG lags the input voltage, the sum of VTA2 and VTA3 will be a negative quantity, indicating a lagging condition. [00105] It will now be demonstrated that for small values of phase error, ε, between the PRG and the input voltage sinusoid, a normalized sum of VTA2 and VTA3 provides a very good direct estimate of the phase error. With respect to Figure 15, the equation describing the input voltage waveform, V _dp (/), with time referred to the PRG is

K _P (ή = V _m sin(2πfl-ε) (12) where V _m is the fixed amplitude of the voltage sinusoid, f is the frequency of the sinusoid and ε is the phase error between the sinusoid and the PRG. To re-iterate, it is assumed that the frequency is known, and that all three of these values are constant As indicated above, positive ε indicates that the sinusoid lags the PRG or, equivalently, the PRG leads the sinusoid. The fundamental period of the PRG is denoted T, and if it is assumed that the PRG and sinusoid have the same fundamental frequency, T is related to f by:

T = j (13)

[00106] In Figure 15, the interval q2 is represented as the closed time interval [T/4,T/2]. The interval q3 is represented by the closed interval [T/2,3T/4]. With these intervals defined, the integral of the sinusoid over q2, denoted VTA2, is:

[00107] Using the relation from plane geometry: cos(α-£) = cos(α)cos(£>) + sin(α)sin(6) (15) equation (14) becomes simply:

VTA2 = — [cos(f)-sin(£)] (16)

[00108] Similarly, VTA3 is given by:

3774

VTA3 = J V sin(2π ft - ε)dt r/2

= ism ε +cos ε)

2πf ^κ '

[00109] Adding VTA2 and VTA3 yields:

VTAQ2 + VTAQ3 = -—sin (ε) (18) πf while subtracting VTA3 from VTA2 results in:

VTA2-VTA3 = -—cos(ε) (19)

[00110] Now, define the quantity E by

VT42 + VT43 VTA2-VTA3

Substituting (16) and (17) for VTA2 and VTA3 and simplifying yields: E = tan (ε) (21)

which, for small values of phase error, ε, becomes as an approximation: £ = tan(£) = £ ^" (22)

[00111] Thus, for small values of phase error, the quantity E, computed by taking volt- time areas provides a good estimate of the phase error (in radians) under the assumptions given. This phase error estimate can be used in a closed loop feedback system to drive the PRG into synchronization with the line voltage.

[00112] As mentioned above, the EQ5400 AC Resistance Weld Control is a sampled data system in which samples of the external continuous time signals are taken at discrete, fixed intervals of time using an analog to digital converter. These samples are, by design, synchronized to the timing of the PRG and, in fact, a PRG period is defined as the time required to obtain 128 such samples in the preferred embodiment. A continuous time signal, x(t) is approximated in a sampled data system by a sequence of discrete sample points, x(k) according to:

where T _s is the elementary sample period of the system - the DSP interrupt interval in the case of the EQ5400 AC Resistance Weld Control. In what follows, the value x(k) refers to the kth elementary sample of the entity x(t). For instance, applying this to the observed voltage waveform of (11) gives the sequence:

V _dp (k) = V _m sm (2πfkT _s + ψ), * = 0,l,- (24)

[00113] As an example of such a sequence, let the parametric values in (24) be those given in the table shown in Figure 16. This corresponds to sampling a 480 VRMS, 60 Hz wavefoπn at 128 samples per line cycle. The corresponding samples are shown as a stem plot in Figure 17.

[00114] In the EQ5400 AC Resistance Weld Control, the voltage is sampled at discrete intervals as described above, and a trapezoidal approximation to the volt-time area integral is performed. If the number of samples taken by the digital voltmeter function over an internal PRG period is N ₈ ., then there are N _s /4 samples taken over a quadrant. The estimates of volt- time area of quadrants 2 and 3, henceforth denoted V _wc TA(q2) and V _wc TA(q3) are generated using:

and

3N,

V _WC TA(φ) = T _S ∑ ^v _^ (J)+K _c ( ^j~ ι) ₍₂₆₎

λ\ 2

Here, the index "j" refers to the jth sample of the voltage waveform (DSP interrupt) within a PRG cycle as defined above.

[00115] In a resistance weld application, in which large currents are drawn for short periods, the presence of line impedance corrupts the "shape" of the observed voltage, so that it is no longer sinusoidal. The following develops the current equation for an AC phase controller, such as a resistance welder, and explores the effects of the line impedance on the observed sinusoid.

[00116] The mathematical solution is developed in two parts. First, the current equation of a stiff driving point voltage source driving a load that has both resistive and inductive components is explored. Next, resistive and inductive line impedance elements are introduced in series between the driving point voltage source and the point at which the voltage is actually observed, and the relation between the driving point voltage and the actual voltage observed by the weld control are explored.

[00117] Figure 18 shows an ideal circuit model for an AC phase control, such as a resistance welder, driving an inductive load. An ideal source of voltage, labeled Vd _P (t), provides the source voltage for the system. A switch, labeled SWl, closes and opens on demand, and represents the thyristors that form the solid state switching elements of the phase control. The load comprises a resistor, labeled R| _O0 d and an inductor, labeled L| _Oa d- The current flowing is labeled i(t), and the voltage applied to the load is labeled V| _Oa d(t)- [00118] As above, in this first scenario, Va _p (t) is a sinusoidal voltage source of the form:

where ω is the radian frequency of the sinusoid, related to the frequency in Hz. by: ω= 2πf (28)

[00119] When a semiconductor switch such as an SCR is used as the switching device, a simple model for this device is a switch closing at a commanded time τ from the zero

crossing of the sinusoidal voltage source. Once the switch is closed and current begins to flow, it continues to flow until the current naturally extinguishes itself, at which time the switch blocks voltage. Under this condition, the current flowing in the circuit is given as a function of time by:

(29) where φ is referred to as the "lag angle", related to the resistance and inductance by:

φ= tan ^"1 p ^t ssL (30)

and T is the conduction time, i.e. the time elapsed from the firing time until the current naturally extinguishes itself, expressed concisely mathematically by:

The function u(t) is the commonly known "unit step function", defined mathematically by:

(32)

^{V ;} [1, t >0

The origins of equation (29) and it's derivation will be discussed subsequently. [00120] In general, equation (29) cannot be solved in closed form for conduction time, but iterative methods can be used to derive approximations. Equation (29) can be normalized to be frequency and therefore time independent. Define the firing angle α, conduction angle, γ and impedance Zi _oa d of the phase control by: a = ωτ (33) γ = afT (34) and

(35) and let θ be the observation angle, i.e. the angle after the zero crossing of the sinusoid. Then (29) becomes:

(36)

This is the "normalized" form of the phase control equation.

[00121] Next, consider a more complex circuit model of the lumped parameter system that forms the mathematical basis for the present invention. In this model, shown in Figure 19, the source of weld power is not assumed "stiff as in the previous discussion, but contains three lumped circuit elements, namely: the original "stiff driving point voltage source V _dp (t), identical to that above and a series lumped line resistance, labeled Rr, _ne ; and series lumped line inductance, labeled Lj; _ne inserted between the driving point voltage source and the weld control.

[00122] This lumped parameter model of the power source combines the resistance from all sources between the assumed stiff voltage source and the input terminals of the weld control. It includes the winding resistance of the distribution transformer, the inductance of the transformer, the resistance and inductance of the power distribution system, such as wires, busway, switch contacts, etc. This line impedance can be significant with respect to the load impedance. In Figure 19, the voltage observed by the weld control is labeled V _wc (t) and, under conditions in which the weld control is firing under load, differs from V _dp (t) by virtue of the current flowing through Rji _ne and L|; _ne .

[00123] Referring to Figure 19, several things are apparent: both the line impedance and load impedance factor into determining the weld current, i(t); when there is no current flowing, and hence no voltage drop across the line impedance, the voltage observed by the weld control, V _wc (t), is equal to the source voltage, V _dp (t). However, when current is flowing in the circuit, the voltage observed by the weld control is not that of the voltage source, V _dp (t), because of voltage drops across the line resistance and line inductance. [00124] From elementary circuit analysis, one can write for the current:

(37) where Req arid L _eq are, in this case, the equivalent series resistance and inductance, given by:

and

4, = ^ _£ + £w (39) and <}), and T are computed per the equations describing the simple model of Figure 18, but using the equivalent values above. The voltage V _wc (t), observed by the weld control is related to the ideal voltage source modeled by Vd _P (t) by:

U0=M' ⁾ - ^J W(' ⁾ -*».^ ⁽⁴ ° ⁾

[00125] The voltage observed by the voltmeter function of the weld control becomes quite complex, and it is difficult to visualize the effect. However, Figure 21 shows simulation results showing the effect of the line resistance and line inductance on the observed voltage for the parametric values of the circuit in Figure 19, provided in the table shown in Figure 20. The simulation and charts presented were generated using MATLAB, a commercially available software package well suited to the task.

[00126] Comparing the voltage waveform of the driving point voltage source in Figure 21 (top) with the voltage waveform that would be observed by the voltmeter function of the weld control in Figure 21 (middle), the observed voltage waveform is a significantly distorted version of the source voltage. Under load, the weld control cannot directly observe the driving point voltage source, V _dP (t), because it is strictly a mathematical construct, and as such there is no specific point on which to apply connections to measure voltage. Even if one could find an appropriate point in the power distribution system to monitor the actual source voltage, the monitor point would likely be located some distance from the weld control, and it is desirable to have the weld control a localized, stand alone entity. The EQ5400 AC Resistance Weld Control observes the voltage at the input terminals. [00127] The voltage distortion shown in Figure 21 limits the performance of an AC resistance weld control in two ways without the benefit of the present invention. The first limitation is that applying the method of estimating phase discussed in detail above to the distorted waveform of Figure 21 (middle) generates an incorrect estimate of the phase relative to the driving point voltage source. For the example above, using the phase error estimation method provided above, it can be shown that if the phase reference generator were originally "locked" onto the line voltage source V _< j _p (t) (the term "locked" meaning zero phase error generated prior to welding), applying the same method to the observed weld control voltage, V _wc (t) of Figure 21 (middle) while welding, the phase error estimator gives a phase

error of approximately -7.7 degrees. If the PRG is allowed to react to this estimated error while welding, the timing of the system will be incorrect, and the system will generate the wrong firing points for the thyristors to achieve a target weld current. Even if closed loop control is employed to modify the firing points to obtain a constant current, reacting to the phase error generated above would at least cause a disturbance in the weld current. Since resistance welds are typically short (on the order of ten line cycles total), such a disturbance could have an effect on the metallurgy of the weld.

[00128] The second limitation is that the RMS voltage measured by the weld control in Figure 21 is less than that of the driving point voltage source model Vd _p (t). In the example given, whereas the RMS value of the voltage source is 480 Volts, the RMS voltage of the waveform in Figure 21 (middle) is 453 Volts. This is the waveform that is directly observed by the weld control. One feature of some prior art weld controls is the ability to automatically compensate for variations in observed voltage, attempting to maintain the current constant. From the above development of the weld current equation of a system with line resistance and reactance, it is clear that the current delivered for a given firing point of the thyristor is dependent upon the driving point voltage and the equivalent, lumped resistance and inductance, which include the load and line values.. Accordingly, using the observed line voltage (which differs from the driving point voltage when current is flowing) as the basis for voltage compensation presents a limitation to the weld control performance. Conversely, the ability to use the estimated driving point voltage described in the present invention, as the basis for line voltage compensation affords an important improvement in this regard.

[00129] The effectiveness of a weld control based on the circuit model of Figure 19 to generate appropriate thyristor firing points (timing) is dependent upon the accuracy upon which the PRG can estimate the relative phase error between itself and the mathematical model of driving point source voltage. As has been discussed, the very act of conducting current in a resistance weld distorts the voltage waveform observed by the weld control, and directly applying the method of discussed above to the observed voltage will cause errors in timing of the firing of the thyristors.

[00130] Suppose, however, that the parametric values of line resistance and line reactance (inductance) can be estimated. If this is so, then from equation (40), and an observation of the weld control voltage V _wc (t) at the input of the weld control, the load current i(t), and the

derivative of load current, di(t)/dt, an estimate of the open circuit ideal voltage source, V^ (t), can be made using:

[00131] Applying the mathematics above to estimate the source voltage V ^* (t) and subsequently using this estimated voltage in computing the phase error in the PRG should provide for more accurate timing of the PRG and hence the firing points of the thyristors, and would more generally facilitate use of the model of Figure 19 in a feed-forward control scheme. Accordingly, one feature of the present invention is a means to estimate the line resistance and line reactance of the power distribution system.

[00132] To proceed in developing the mathematics, one can solve equation (40) for V _dP (t) to obtain:

V _dp (t) = V _uc (ή ₊ R _lin j(t) ₊ L _liM ^l (42)

Note that this relation is independent of the values of the load impedance elements, R| _oad and Lioad. As discussed above, the weld control includes a digital voltage sampling function (analog to digital converter) that can estimate (measure) V _wc (t), at discrete intervals and a digital current sampling function that can similarly estimate the value of i(t) at discrete intervals. If values of Rπ _ne and Lπ _ne can be estimated, equation (42) indicates that the instantaneous driving point voltage, V _dp (t) can also be estimated. [00133] As stated previously, the EQ5400 AC Resistance Weld Control operates as a sampled data system, sampling the signals representative of voltage and current at discrete intervals, at the sequence of points {t^}, defined by: t _k = kT _s where T _s is the elementary sampling interval. Applying this to equation (42) yields a sequence of points, V _dP (k), with the kth sample in the sequence given by:

V _dp (kT _s ) = V _wc {kT _s ) + R _liπc i(kT _s ) + L _liM ^l, k = 0,l- _. (43)

[00134] Henceforth, it is understood that whenever the index "k" appears, the corresponding time of the sample is t=kT, k = 0,l,2,... _s . With this understood, the nomenclature in equation (43) above is simplified to yield:

[00135] The weld control provides sampling functions that provide estimates of the voltage sequence V _wc (k) and the current i(k), but not the derivative sequence di{k)/dt at each point. However, an approximation to the derivative sequence can be made by defining the first backward difference, δi(&) :

Ai(k) = i(k)-i(k -ϊ) (45) and approximating the derivative using

* (*) - *& (46)

substituting (46) into (44) gives:

V _φ (*) = V _lw (*) + λ _λw ι (*) + A _h .^. » = <U- (47)

[00136] Now, define X by:

where T _s is the known sample period of the system. Substituting this gives: y _dp (k) = V _wc {k) + R,j{k) + X _letl Ai{k), * = 0,l,- (49)

Some methods of estimating the assumed constant values of R|j _ne and Xi _eq are now explored. To accomplish this, the development will begin with a general approach and preferred method evolved. Examining equation (49), at a given sample, k, there are three quantities that can be "known" to the system via measurements, namely 1) V _wc (k) which can be measured using the digital voltmeter function, 2) i(k), which can also be measured using the digital current meter function, and 3) δi(k) which can be computed from a knowledge of i(k) and i(k-l) according to equation (45). There are also three unknowns in the equation, namely V _d p(k), Run _e and X| _eq . None of these are directly observable when current is flowing, and the sequence Va _p (k) is not necessarily constant. There are several ways in which one can proceed to generate an estimate of R|; _ne and Xi _eq , but in each case some assumptions must be made regarding the nature of Vd _P (k) which is also not directly observable.

[00137] One possible method to estimate the constant values of Ri; _ne and Xi _eq is to suppose the system has obtained observations of the measurable quantities at distinctive sample times kθ, kl and k2 (not necessarily in monotonic increasing order), and further suppose that that there is a known, constant mathematical relation between the values of V _dp (kl), V _< j _p (k2) and Vd _p (k3) that can be expressed as:

where Mi and M ₂ are known constants. With this established, one can write the following matrix equation for the three samples:

V~(*o) ^" -i(kθ) -Ai(kO) 1 -i(kl) -Ai (kl) M ₁ (51)

K. _c (*2) -i(k2) -Ai(k2) M ₂ v+ (*° ⁾ which is of the form:

V = A*U (52) where V is the matrix of measured voltage points:

U is the matrix of unobservable quantities (two of which, R|j _ne and Xieq are the object of this estimation):

and A is a matrix of observable and known quantities relating V and U according to (51):

If the matrix A is non-singular, the mathematical inverse of A exists and one could solve (51) to obtain:

^R linc -i(kθ) -Ai (kO) 1 V _wc {k0) -i(kl) -Aϊ(kl) M ₁ Ke («) (56)

M*o) -/(£2) -δi(*2) M ₂ Kc (*2) and thus obtain an estimate of Rπ _ne and X| _eq . Equation (56) will also yield the value of

V _dp (kO), but the most important quantities for the present invention are the line resistance and reactance.

[00138] One interesting variation on this method is to assume that the sequence Va _P (k) is periodic in k with an integer period N _s , such that:

V _dp {pN _s k) = V _dp {k) (57)

For values of p in the set of natural numbers, i.e. p = { 1,2,... }. This is interesting from the perspective of the present invention because 1) it is already assumed that the driving point voltage is periodic, and 2) as discussed earlier a PRG period comprises N _s samples (DSP interrupts). Thus, if the PRG is already synchronized with the driving point voltage this periodic relation exists and is known. If kO, kl and k2 are related by:

IS PI 2T ^* * ⁰ ' ^{plp2≠l pl≠ p2 (58)}

With pi and p2 both natural numbers, then from (57) this yields Mi = I and M ₂ = 1 in equation (56). Practically, this method implies that the samples are taken at the same relative "place" in different PRG cycles. Of course, being able to set Mi and M ₂ = 1 in equation (56) does nothing to guarantee that the matrix is non-singular and can be inverted, so this method may not work in a general case. In particular, if the system employing such a method is operating in the "steady state", such that the current and current difference taken at the same at each sample point, the matrix will definitely be singular and the method will not produce useful estimates of R|j _ne and Xi _eq .

[00139] To explore a different, and more practical means for estimating R|j _ne and X| _eq , rewrite equation (49) in the form:

V _d » (k) -V _m (k) = R _Unt i(k) + X _lt9 &i(k), k = l,~ (59)

Now, one can write in matrix form for the three data samples:

V _dp (k0)-V _wc (k0) ^' i(kθ) i(kl) Jc = I,- (60) V _φ (k2)- V _κc (k2) i(k2)

Significant simplification in the mathematics above can be made if one assumes that during one of the samples, say kθ, the current and current difference are both zero. If this is the case, from equation (60), one can write directly:

*U* ⁰ ) = M* ⁰ ) ⁽⁶ 1 ⁾ and if (57) still applies, one can write

Which can be solved for the line resistance and reactance:

This too assumes that the matrix of current and current difference is non-singular, but is only a 2x2 matrix.

[00140] The assumption that a line cycle can be found in which current does not flow and has not been flowing (so the current and current difference are both zero at the point kl) is a reasonable one in a resistance welding application in which the application of weld current is normally preceded by a period in which current does not flow while the mechanical weld "tips" force the metal to be joined together. Furthermore, once current begins to flow, it can be reasonably certain that the current flowing in the first line cycle of weld will differ from subsequent line cycles of current because this forcing of metal together is normally not perfect and the steady state will not be reached until the metal actually begins to melt. [00141] To continue the evolution, if it is assumed that samples can be taken on a PRG cycle in which current is known to not be flowing, and in other PRG cycles in which current is known to be flowing, there is no need to constrain all the samples by equation (57), provided samples can be taken in pairs (ka,kb), such that

K = pN _s k _a (64)

In particular, assume there are two pairs of data points, (koi,ki) and (ko ₂ ,k2), such that: and k ₂ = P ₂ N _s k _ϋ 2> P ₂ ≠ 0 (66)

And that koi and ko ₂ are samples taken from a PRG cycles in which current is not flowing, and k) and k ₂ are taken from PRG cycles in which current is flowing, and furthermore assume that (57) applies for each pair (koi.ki) and (ko ₂ ,k ₂ ),. Then one can write by inspection:

assuming again that the matrix inverse in (67) exists. This method permits (but does not require) the estimation of Rπ _ne and X _leq to be made from distinct DSP samples within two line cycles, one in which current is not flowing, and one in which current flows. Allowing this greatly enhances the likelihood that the matrix inverse in (67) will exist. [00142] In a factory environment, the magnitude of the actual driving point voltage does change over time, and such a change is one factor that can affect the accuracy of the estimates of line resistance and line reactance. The farther apart in time the line cycles are chosen in the above discussion, the more likely the driving point voltage magnitude will differ significantly. Therefore, in the preferred embodiment of the invention disclosed herein, adjacent line cycles are chosen such that the line cycle in which current flows and is measured is adjacent to a sequence of line cycles in which current has not been flowing for a substantial number of line cycles. It is understood in what follows that this particular embodiment does not limit the usefulness of the invention and in particular, one can readily envision an embodiment in which the line resistance and line reactance are computed using a sequence in which current is flowing in a particular line cycle and does not flow in a subsequent line cycle. The embodiment of the invention disclosed herein is preferred because if current has not been flowing for significant number of line cycles prior to conducting current, the PRG should be accurately synchronized with the driving point voltage when current begins to flow. Because there is a natural lag in response of one line cycle in the PRG implementation disclosed, the current samples taken from the first line cycle in which current flows after a long interval in which current is not flowing cannot affect the PRG until after the measurements are taken. This is the ideal condition in which to obtain samples. [00143] Proceeding again, make the following assumptions: (1) the system has not been welding for a period of time, so that the observed weld control voltage, V _wc (/) is identical to that of the source voltage, V _dp (/), i.e.

⁽⁶⁸⁾

and (2) over the period of any two line cycles, the modulation term of the driving point voltage, V _1n (/) is constant, and can be represented as:

M') = K, sin {2πfή (69) as above.

[00144] Consider two sample points taken exactly one period apart under these conditions: one in which weld current is not flowing, and another, exactly one PRG period apart where current does flow. Recall again from above that there are N ₅ samples (DSP interrupts) per PRG period. Under the assumptions above, one may write:

Kp (*) = V _dp (* - N ₁ ) = Kc (* - N, )|,(*- ₀ =o (70)

%(*-l)=0

[00145] Applying this to equation (49), one can write: for the particular case in which current does not flow during one line cycle and does flow on the subsequent line cycle. If one can select two sets of samples from adjacent line cycles, say at samples kl and k2 (kl not equal to k2) in which the current and current difference values are non-zero and are distinctly different from one another, one can write in matrix form:

(72) which can be solved in matrix form to obtain:

-I i

^' R l ₁ ine i(kl) Ai (kl) l" K _C (*1 - N _X ) - V _WC (kl) ^'

(73)

X teq _ i(k2) Ai (k2) V _κc ( ^k2 - ^N _* ) -K _c (k2) provided the inverse matrix is non-singular. Equation (73) provides one means in which the line impedance parameters could be estimated.

[00146] A potential limitation with using individual points to make the line impedance parameter estimates is that the observed signals are generally "noisy", especially in a factory environment where there is a lot of switching on and off of control and power circuits, and other switching elements. The computed values of line resistance and line reactance are sensitive to the actual values of current and voltage used in Equation (73).

[00147] A more robust means of estimating the parameters is now presented. As set forth above, the system generates for each quadrant the VTA with trapezoidal integration employed to give the quadrant estimate. It is well understood in the study of stochastic

processes that if signals are corrupted by uncorrelated, zero-mean noise, taking the average over a sum of many samples reduces the variance of the estimate. The volt-time area, current-time area and current-difference area can be used to compute such an estimate. For a general sequence x(k), define the general "X-time area", XTA(q.n) of x(k) over quadrant q, q = ql, q2, q3, q4 , and PRG line cycle n by:

where j is the index of the sequence x(k), but indexed from the beginning of the PRG cycle, i.e. j = 0 corresponds to the transition from q4 to ql of the PRG function 10. With this definition, the estimated volt-time area of the observed weld voltage over quadrant q, V _wc TA(q,n) is

VjTλM- ± ^y -U-'> (75,

which is exactly the sum used to compute the volt-time area of the quadrants employed in the PRG function 10. Now, In an exactly analogous manner, define V _dp TA[q,n) , lTA[q,n) and

AITA(q,n) by:

and

[00148] Next, observe that equation (49) is a linear equation that, for each sample n relates the driving point voltage sample V ₄ , (k) to the observed weld voltage sample, V^ (k) , current

sample i{k), and first current difference Ai (k) . Since it is a linear relationship, the relationship also applies equally to the quantities XTA(q):

V _dp TA{q,n) = V _wc TA{q,n) + R _tmc JTA{q,n) + X _Uq MTA{q,n) (79) with R _lltU! and X _leq assumed constant parameters.

[00149] Selecting q2 and q3 as the quadrants to be used to estimate the parameters, one obtains (in matrix form):

where the nomenclature Rl _ne and X _t ^* _eq refer to the estimates of power distribution system resistance and inductance respectively, and the indices (q2,n) and (q3,n) mean the quadrant estimates from quadrants 2 and 3 of the present line cycle in which current is flowing, and (q2,n-l)and (q3,n-l) designate the quadrants 2 and 3 from the previous line cycle, in which current was not flowing. Again, one can solve for the estimated parameters to obtain:

_

(81)

This important result is the method utilized in line impedance parameter estimation in the EQ5400 AC Resistance Weld Control to compute the values R ^* i, _ne (m) and X ^* i _eq (m) in Figure 8 above.

[00150] A closed form solution to the weld current delivered by an AC resistance weld control is now developed using Laplace Transform techniques. The analysis assumes a stiff driving point voltage source and ideal thyristor switches. Results are presented both as a function of time as well as observation angle. The conditions determining the time or angle of conduction of the thyristor as a function of the firing point and load impedance are also presented.

[00151] Figure 22 is a simplified Jumped parameter circuit model for a resistance weld controller and associated power distribution system and weld load, which will be used to derive mathematics of the weld controller. The lumped parameter model comprises a weld power source 11, the weld controller 20 and weld load impedance 30. The weld power source 11 is modeled as two circuit elements, a voltage source V _s (t) 12, which is assumed to

be an ideal voltage source having no series impedance and a serially connected lumped line impedance, Zγ _tne , which is assumed to be ideal and linear and which generates a voltage drop between the ideal voltage source and the weld control proportional to the weld load current. The weld timer 20 is capable of observing the load current I| _oa d via a current transformer 24 and the voltage applied at its input terminals, V _wc (t). Utilizing solid state thyristor switches 22, the weld timer generates a weld voltage Vi _oa d(t) at its output terminals, with a corresponding weld current Ii _oa d(t)- The weld load impedance 44 comprises the weld transformer 20, workpiece, tooling 22, fixtures and other sources of impedance. To simplify the mathematics, the impedance of all these elements are lumped into a single impedance quantity reflected at the output terminals of the wekTcontrol as Zioad- When the weld control applies the voltage Vi _oa d(t) upon the load impedance, the resulting current is I| _Oa d(t). [00152] In what follows, the line impedance Z _\me is assumed to be zero and the voltage source, V _s (t) is considered to be an ideal source of the form: v,(t) = V sm(2≠) (82) where V is the magnitude of line voltage and f is the line frequency (in Hz.) of the line voltage source. This sinusoidal waveform as a function of time is shown in Figure 23 (top). Note that the zero crossings of this waveform occur at points for which the following holds:

/ =~, « = 0,1,- (83)

[00153] To remove the dependence upon frequency, timing in the resistance weld application is usually expressed as angles in degrees rather than time. In this analysis, the observation angle (corresponding to time) is designated as θ. Figure 23 (bottom) shows the voltage waveform as a function of observation angle, with zero degrees referenced to a negative to positive zero crossing of the sinusoid. Note that in this case, the zero crossings of the sinusoid are at the angles:

[00154] The thyristor switches are assumed to be ideal switches having no voltage drop. The load impedance, reflected to the primary side of the weld transformer, can be reasonably modeled as a lumped load resistance, R| _oad and a series load inductance, Lj _oad as shown in Figure 24.

[00155] The effect of firing the solid state thyristor welding contactor is to close the switch in Figure 24 at a time t=τ (or at an angle α) with respect to the zero crossing of the voltage

source as shown in Figure 23. Figure 25 shows the voltage waveform resulting from firing the thyristor. Once the switch is thrown and current begins to flow in the load, the switch remains closed until the current is again zero at a time t = τ+tc _Ond as shown in Figure 25 (top), or at an angle θ =α+γ as shown in Figure 25 (bottom). The actual value of t _cond or γ is dependent upon the firing point and the load circuit parameters and will be derived herein. Mathematically, the voltage applied to the load is of the form:

VW (0 = V sin(2^) * [«(/ - v) - u(t ~ {τ + t _cond ))/] (85) where u(t) is the unit step function.

[00156] The purpose of this analysis is to develop the closed form solution for the weld current resulting from firing the thyristor switch at a time τ with respect to the zero crossing of the source voltage v _s (t) as given in (82) above and shown in Figure 23. Additionally, the form of the current waveform will be developed that is a function of the angle of observation, θ as described in Figure 23 (bottom). Another important quantity is the resulting conduction time, tc _ond , or its equivalent conduction angle, γ, which is defined as the angle over which the thyristor conducts, or alternatively, the angle over which current flows as a result of firing the thyristor.

[00157] The following assumptions are made to simplify the analysis of weld current:

1. The voltage source, v _s (t) is assumed ideal and hence "stiff'. There is no line impedance.

2. The frequency of the voltage source remains constant.

3. The thyristor switches are assumed to be ideal, having no voltage drop. Once triggered, a thyristor conducts until the current flowing through it is exactly zero.

4. The load impedance, comprising a load resistance and load inductance, reflected to the primary, is assumed constant throughout the weld. This results in a linear, time invariant system.

[00158] Under these assumptions, the closed form solution to the load current iio _ad (t) resulting from firing the thyristor at a time τ with respect to the zero crossing of the sinusoidal input voltage is:

(86) where

V is the magnitude of the sinusoidal input voltage;

R is the resistance of the weld transformer, gun and tooling reflected to the primary of the weld transformer;

L is the inductance of the weld transformer, gun and tooling reflected to the primary of the weld transformer; ω is the radian frequency of the line voltage source; φ is the lag angle of the load impedance, defined by: φ = tan -i — ⁰ ^- (87) and, τ is the time at which the thyristor is fired relative to the zero crossing of the line voltage as shown in Figure 25. [00159] Expressed in terms of the observation angle θ, the load current i(θ) is:

*) u(θ-a) (88) where θ is the observation angle, measured from the negative to positive zero crossing of the sinusoidal voltage source; φ is the lag angle of the load impedance as given by equation (87) above; α is the firing angle, related to τ by a = ωτ (89) and,

|Zioad| is the magnitude of load impedance given by:

(90)

[00160] The conduction time, t _c0nd and analogous conduction angle, γ are those values for which the following holds:

' ^< - %,>ή)J ^< - ^{τ} (9l)} and

[00161] Assuming a stiff weld source allows for a simple presentation of the voltage waveform presented to the load. Referring to Figure 22, when there is no line impedance present, the voltage V _wc observed by the weld control is identically that of the voltage source, V _s . If there is line impedance present, the line voltage observed by the weld control, V _wc will be reduced from that of V _s by the current flowing through the line impedance. [00162] For purposes of analyzing the effect of the line impedance on the weld current, one could readily lump the line impedance and load impedance into a single entity. Assuming that the line impedance is also inductive in nature (ignoring the capacitance of the distribution system), equivalent resistance and inductance can be defined by:

K = ^R ^ ^{+ R} l°a* (93) and

K = L _linc + L _lmi (94)

If these values are substituted into the various equations above, the resulting current would be an accurate estimate of what is actually transpiring in the weld control. [00163] A fixed radian line frequency ω is required to make the assumption that the system is linear and time invariant. Without this assumption, the use of Laplace transform techniques would not be possible. Fortunately, this assumption is realized to a very high degree in application.

[00164] An ideal thyristor is assumed for simplicity. A model of a thyristor comprising a fixed voltage drop, or any linear model for the thyristor could also have been employed. If a model incorporating a fixed voltage drop is employed, it would be modeled as a DC voltage source. In a linear system model, the resulting weld current could be expressed as the superposition of the response to the sinusoid, as expressed in the equations above, and a DC voltage source impressed upon the system at the firing time.

[00165] A constant load impedance is required to permit analysis of the lumped parameter model as a linear, time invariant system. The inductance is primarily determined by the

geometry of the tool and the work piece, and as such can change as the geometry of the tooling changes. An example of this is that the shunts and cables have a tendency to "jump" upon initiation of a weld. The resistance is usually pretty constant over the course of a half- cycle. It should be cautioned that during expulsion, a phenomenon in which molten metal is expelled from the weld tips and is usually observed as the shower of sparks emanating from the weld tips when too much heat is applied, the resistance can change very rapidly. In this case, the form of weld current will probably not follow the above equations well. [00166] The basic form of the weld current can be derived as discussed below. Writing the loop equation for the circuit of Figure 24 gives:

Taking the Laplace Transform of equation (0-67) gives

or

v _ha M (97) [00167] From Figure 24 one may write

(98) which when solved for I(s) results in

(99)

[00168] To get the Laplace Transform of the load current, one multiplies equation (99) by equation (97) to obtain:

(100) which can be written in the form:

Ve l{s) = F(s)[ssm ^' (ωτ) + ωcos(ωτy] (101)

with F(s) given by:

(102)

[00169] Now, note the following properties of the Laplace Transform:

1. The term e ^'sτ implies a time delay, that is:

4/(t-r)} = β-"4/(/)} (103)

2. The Laplace transform of the derivative of a function is of the form:

[00170] Examining equation (101) in the light of (103) and (104), if the inverse Laplace transform of F(s) is f(t), the load current i(t) can be written as:

[00171] Thus, if f(t) can be found from (102), equation (105) shows how to derive the weld current. F(s) can be expanded into partial fraction representation of the form:

(106)

[00172] Cross-multiplying and gathering terms in (106) results in:

(107)

[00173] Equation (107) is a polynomial in 's'. To satisfy (107) over all values of s, the coefficients of each term of the polynomial must be zero. This gives the following relations between a, b and c: a +b = 0 (108)

and

[00174] Solving for 'a' in (106) gives:

(111)

[00175] From (108), 'b' is found to be:

[00176] Solving (109) for 'c' yields

[00177] Substituting ( 111 ) and simplifying results in

[00178] Substituting (111), (112) and (114) back into (106) gives:

(115)

[00179] Taking the inverse Laplace transform of (115) gives:

-cos(ύ)t)+ sin(άfl) \u(t) f ill

(116)

[00180] Taking the derivative of (116) gives

(117) [00181] Substituting (116) and (117) into (105) gives:

(118) Rearranging terms gives:

(119)

[00182] Two trigonometric identities that can be used to simplify (119) are: sin(λ ± B) = sin(λ)cos(β)±cos(λ)sin(β) (120) and cos(i4 ± B) = cos(λ)cos(5) + sin(A)sin(#) (121)

[00183] Applying these identities to (119) results in

(122)

[00184] A fundamental concept of AC circuit analysis is that of the lag angle of an R-L circuit, denoted by φ and defined as: φ = tan ^" (123)

R from which the following relations can be written: ω sin(φ) = (124)

V* ² +K) ² and

[00185] To facilitate the use of these relations, first multiply through (122) by the quantity IVL = 1 and rearrange the terms to give:

(126)

[00186] Now, applying ( 124) and ( 125) yields

(127) [00187] Applying (120) to (127) gives

(128)

[00188] Equation (128) is the normal form for the equation of weld current as a function of time for parametric values of firing time, τ, with respect to the zero crossing of line voltage, the radian line frequency ω and the equivalent load resistance R and load inductance L reflected to the primary of the weld transformer.

[00189] The point at which the Thyristor switch is fired is normally expressed in terms of a firing angle, α, rather than a firing time. The firing angle, α, is related to the firing time, τ, and the radian line frequency ω by: a = ωτ (129)

Similarly, we can define the observation angle, θ, by θ = ox (130)

[00190] With these two quantities defined, one may rewrite the exponential in (128) as g H∞ά — β ^ωL taiJ

(131) Applying (123), (130) and (129) to (131) gives _e J ' _{= e} <»(•>) (132)

[00191] Also, the magnitude of the AC load impedance of the R-L circuit is recognized as:

(133) [00192] Substituting (133), (132), (129) and (130) into (128) gives:

as an expression of weld current in terms of the firing angle, α, circuit lag angle, φ and observation angle θ. Figure 26 is a plot of the current waveform resulting from applying the parametric values shown in Figure 27 to Equation (134).

[00193] Once the thyristor fires and current begins conducting, the thyristor continues to conduct current until the current naturally extinguishes itself at a zero crossing. Using equation (128), the time at which the thyristor switches off satisfies:

where i(t) is given by (128) above. Equation (135) is the mathematically rigorous statement that the conduction time is the interval between the firing of the thyristor (at t = τ), and the first time the weld current again passes through zero. There is no closed form solution for t _cond , but equation (128) can be solved ϊteratively to a high degree of precision. Similarly, the conduction angle, γ, is that angle that satisfies: γ = min (θ- a) (136)

' &>o. .(<?)=o ^v '

[00194] A closed form solution for the weld current can be found assuming a linear lumped parameter model of the weld circuit. While the analysis presented herein makes a great many assumptions, some of which may be considered suspect in an actual weld application, the results presented have been generally accepted as "the solution" for weld current and have been referenced repeatedly in the literature. A more accurate modeling of the system can be readily achieved incorporating a model for the source impedance presented by the weld voltage source, and effects of the thyristor can also be readily explored assuming linear models for each.

[00195] While the specific embodiments have been illustrated and described, numerous modifications come to mind without significantly departing from the spirit of the invention, and the scope of protection is only limited by the scope of the accompanying Claims.