AN IMPROVED RFID DEVICE FIELD OF INVENTION

The. present invention relates to a radio frequency identification ("RFID") device, and more particularly to an RFID transponder . The present invention has been developed bearing in mind that, in many practical applications of RFlD technology, interrogating signals received by the RFID device are not always reliable or consistent in strength. A. very specific exemplary application relates to the identification of RFID transponders attached to conveyer fed-luggage where the transponder data is used to controf the automatic sorting of the luggage. However, the invention is not limited to this particular field of use. For example, various aspects of the invention are applicable to RFID devices and systems based on passive and/or active RFID devices, and to applications other than luggage sorting systems.

It will be convenient to hereinafter describe the invention in relation to a RFID transponder, however it should be appreciated that the present invention is not limited to that use only. BACKGROUND ART

Throughout this specification the use of the word "inventor" in singular form may be taken as reference to one (singular) or all (plural) inventors of the present invention.

The discussion throughout this specification comes about due to the realisation of the inventor and/or the identification of certain prior art problems by the inventor. Accordingly, the inventor has identified the following art.

In prior art RFID systems there are problems in that either due to the nature of the powering field (eg in UHF applications) or the need to rotate or switch the field (eg in HF Tunnel Reader Programmers (TRPs), and also other reader configurations), there is a likelihood that tags may lose power for at least brief periods of time during operation, and in particular during times, where it is important not to lose the current state information in the tag. in an example prior art system, transponders may be read by interrogation fields within TRPs".

Typically, the orientation and position of transponders as they enter the TRP, for example, are random and unknown. Accordingly, the TRP must switch its interrogation fields between orthogonal directions so that the transponders can be

interrogated independently of their orientation. US Patent No. 5,258,766 provides an example of such a system.

There are a number of specific issues arising from the practical use of RFID transponders, in, say, luggage handling situations. These issues include the facts that, for example:

1. A mechanical means, such as a conveyor, moves luggage (and thereby .transponders) through the TRP.

2. one or more transponders may be attached to a single item.

3. one or more transponders may be in the interrogation field at the one time. Where a mechanical means, such as a conveyor, moves items with attached transponders through the TRP, the determination of the order of items on the conveyor is an essential requirement for allowing automated processing of the items, for example, to ascertain the contents of boxes. The determination of the order in which transponders enter a TRP is advantageous for determining the order of items on the conveyor. In prior art systems transponder order is normally . inferred from the order in which they are identified. However, where multiple transponders are present, the identification messages from these transponders may clash and thus cause a number of the transponders to fail to be identified. When messages clash a further time interval will be required to correctly identify the transponders. During this time the transponders are moved further into the TRP by the conveyor. It is possible that a subsequent transponder or transponders may enter the TRP before the first transponder is identified. It then becomes possible that ' one or more of the subsequent transponders may be identified before the first transponder. Consequently, the order of items may incorrectly be inferred from the order of transponder identification.

In order to alleviate this problem, the interrogation fields may be switched causing the transponders to power down for a short time. For example, PCT/AU2003/01072 entitled 'An identification Device and Identification System ¹ (M29). However, the inventor has also realised that other problems need to be addressed when switching the field, such as identifying tags in the order in which they enter the powering field.

Generally, in some prior art systems, when a RFID device looses its power, temporary data stored in volatile memory on board the transponder may be tost. Such data can include configuration information or temporary data stored in registers. If this data is lost, the configuration information or temporary settings required for transponder operation must be- regenerated in the transponder after each switching of the interrogation field. This data may need to be read out of the transponder's memory or may have to be transmitted (again) to the transponder by the TRP. This is undesirable because of the time delay involved. Moreover, in some cases, the data may no longer be available. Furthermore, in applications where there are many tags present in the field at one time it can be important to have information concerning whether a tag has already been identified (and has subsequently been instructed to "keep quiet" or temporarily cease transmitting). If this information is lost at each power break, previously identified tags may start transmitting again when they should remain "quiet" , and this can significantly reduce system performance.

Any discussion of documents, devices, acts or knowledge in this specification is included to explain the context of the invention. It should not be taken as an admission that any of the material forms a part of the prior art base or the common general knowledge in the relevant art in Australia or elsewhere on or. before the priority date of the disclosure and claims herein.

An object of the present invention is to provide an RFID device having improved storage for data.

A further object of the present invention is to alleviate at least one disadvantage associated with the prior art. SUMMARYOF INVENTION

The present invention provides, in one aspect of invention, in an RF(D device, a method of storing data, the method comprising providing a data storage cell, and substantially isolating at least a portion of the data storage cell from leakage in the event that power is removed from the data storage cell. The present invention provides, in another aspect of invention, a data storage cell for an RFID device, the data storage cell comprising a data cell adapted to store data, and isolation means coupled to the data cell and being

adapted to substantially isolate at least a portion of the data storage cell from leakage in the event that power is removed from the data storage cell.

The present invention provides, in a further aspect of invention, a method of restoring data in a data storage cell of an RFID device, the method comprising the steps of, upon power being restored, reading data as stored in the data cell, and refreshing the data cell using the data read,

The present invention provides, in another aspect of invention, a method of storing data in a data store for an RFID device, the method comprising adapting the data store to operate in any one or any combination of the following 'states': • In a first state, load data into the data cell, the data being substantially the data presented to the store device,

• In a second state, refresh data already loaded in the data cell by using the data stored in the data cell,

• In a third state, isolate the data cell from a 'leakage path ¹ when power is removed from the data store device,

• In a fourth state, sensing the third isolated state based on the information stored in the cell after restoring power to the data store and before the second refresh state replenishes the data stored within the cell.

In a preferred embodiment, in the fourth state the information stored in the cell may be stored by a capacitor.

The present invention provides, in still further aspect of invention, a RFID device, a data storage cell and or memory for storing data as herein disclosed.

Other aspects and preferred aspects are disclosed in the specification and/or defined in the appended claims, forming a part of the description of the invention.

In essence, the present invention in accordance with aspects of the present invention: a. the data store celi(s) is substantially isolated from a power leakage

'path'. In effect, the storage node is preferably substantially isolated from any conduction path. This may be done by creating a high impedance in the path between the cell and a 'power source ¹ (the power supply and / or ground).

Preferably, the cell is isolated from a power supply even though in embodiments it may still be referred to ground. b, Upon power being restored, the invention restores a data state into the data cell using the data stored in (read from) the cell. c. Multi-function data store device for an RFID device is provided, the data store being adapted to operate in any one of the following 'states':

In a first state, to load data into the data cell, the data being substantially the data presented to the store device,

In a second state, refresh data already loaded in the data cell by using the data stored in the data cell, and

In a third state, isolate the data cell from a 'leakage path' when power is removed from the data store device.

Throughout this specification:

• the data storage cell, may be a single cell, an array, or any other form of memory, whether dynamic, static, volatile, non-volatile, persistent or non- persistent. Preferably, the contents of the data storage cell decay over a predetermined period of time upon removal of supply power;

• the RFID. device may be any type of RFID device, comprising without limitation a transponder, a tag, a token, a label, etc The present invention has been found to result in a number of advantages, such as: « Providing for a period of time, a persistent data store

• Enabling information within an RFID device to be retained in the event of a power interruption • Avoids the need to re-read or re-send information to an RFID device being interrogated

• By retaining the state while a tag is unpowered for relatively short durations, the features of tag ordering and knowledge of identification state may be enabled. By reference to prior art systems (eg, using CMOS registers), these prior systems retain state without power for short durations of nanoseconds to microseconds, however, embodiments of the present invention retain data for periods of milliseconds, seconds or longer.

Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, whiie indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

Further disclosure, objects, advantages and aspects of the present application may be better understood by those skilled in the relevant art by reference to the following description of preferred embodiments taken in conjunction with the accompanying drawings, which are given by way of illustration only, and thus are not limitative of the present invention, and in which:

Figure 1 illustrates an embodiment of the present invention, suitable for ASIC implementation. DETAILED DESCRIPTION

FIGURE 1 shows a preferred embodiment of a data storage cell for storing data according to the present invention. An RFID device may comprise one or more of these 'cells' corresponding to the type and/or amount of data which is to be stored. The circuit illustrated may form an addressed cell used for storing one bit of data, a plurality of which addressed cells form a dynamic (temporary) memory array within an RFID device.

The illustrated circuit includes a tri-state inverter X1 , an active-low tri-state inverter X2, a transistor MN1 , a low-threshold Schmitt trigger X3, and a capacitor G1 , which components are interconnected as shown in Figure 1. A low-leakage node N ₁ depicted as "storage" in Figure 1 , is present between the capacitor C1 and the transistor MN1. The tri-state inverter X1 receives an input Ie and an input d. The input Ie is also applied to the active-low tri-state inverter X2. The transistor MN1 receives an input tloaden. The signal tloaden is an "operate" or "isolate" control signal. When tloaden is asserted, the circuit behaves as a "normal" data latch as described herein. When tloaden is de-asserted, the storage node is isolated and acts as a dynamic storage of the signal. If power is applied while tloaden is de-asserted, the Schmitt trigger X3 senses the dynamically stored signal and makes a decision on its value as described herein.

Then when tloaden is re-asserted, the sensed signal is replenished onto the capacitor C1 to refresh the stored voltage to its original value, in other words, the value at the time when power was removed. The low-threshold Schmitt trigger X3 generates an output q. One reason for preferably using a low threshold inverter is that the retention time is longer.

The tri-state inverter X1 inverts the input d when the input Ie is 1 , and has high impedance when the input Ie is 0. The active-low tri-state inverter X2 inverts the output of the low-threshold Schmitt trigger X3 when the input Ie is 0, and has high impedance when the input Ie is 1. The low-threshold Schmitt trigger X3 senses voltage stored on the capacitor C1 after power-up of the TRAM circuit and before latch functionality of the circuit is enabled, that is, before tloaden is asserted. In one form, it is noted that data storage circuit may be referred to as a TRAM (Temporary RAM) circuit. Assertion of the input tloaden enables latch functionality of the circuit. MN1 isolates the capacitor C1 responsive to removal of power to the circuit; The capacitor C1 dynamically stores a present state of a signal on the low-leakage node N (i,e., a present latch state) when the input tloaden is low. It is noted that there is an advantage in driving tloaden to a voltage higher than VDD so that the voltage subsequently stored on the capacitor storage node can approach VDD (for a logic 1 ), rather than storing a degraded signal VDD-VthN which would result in reduced storage 'time or failure to operate depending upon VDD and the H channel threshold Voltage VthN.

When the RFID device, or at least the data cell/array is powered and the input tloaden is asserted high, the transistor MN1 is turned on and the circuit behaves like a conventional data latch. In other words:

1) the output q follows the input d when the input Ie is asserted high; and

2) the output q holds the state of the input d when the input Ie is de- asserted. The signal tloaden is preferably asserted when power ^' is applied so that the latch behaves like a conventional data latch. The signal tloaden is de-asserted when loss of power source/supply is detected and is- not restored until a short delay after power is restored (to allow the sensing circuit to make a decision).

Accordingly, the latch functionality of the circuit is disabled (i.e., a so-called broken latch results) and the latch present state is stored on the low-leakage node N. Since the low-leakage node N has low leakage and no connections to forward-biased diodes (e.g., no PFET connected to the low-leakage node N) ₁ a signal representing the present latch state remains stored on the low-leakage node N, even if the power has been removed from the circuit.

The relatively iow-feakage characteristic of the low-leakage node N and the absence of a connection of the capacitor C1 to forward-biased diodes cause a signal representing the present latch state to remain stored on the low-leakage node N for a period of time even if power is removed from the RFID device and/or data cell. A storage time of the signal on the fow-leakage node N is determined by a value of the capacitance C1 , a reverse bias leakage of the drain of the transistor MN1 , and a source-drain leakage of the transistor MN1 with zero bias on its gate. In the example of an NFET, it is the drain of the transistor having the reverse bias leakage during the time that power is removed from the chip, because it will be at the higher potential but as drain and source are symmetric, this may not really matter. This time may be predetermined by design or otherwise configured according to well known data cell design principles. The circuit according to the present invention stores the signal on the capacitor C1 regardless of whether power is applied to the RF(D device. In practice, it may be quite difficult to accurately predict the retention time because the leakage is process dependent and very temperature dependent (leakage doubles every 9 degrees C). This is why the concept of re-awakening silenced (muted) tags when they enter a reader with a new reader ID is an effective application of these TRAM circuits as it means that only a nominal (minimum) retention time may be required, noting that a longer retention time is also possible.

When power is restored to the circuit, the latch functionality of the circuit is ^' still disabled (ie, the latch is still broken); however, the low-threshold Schmitt trigger X3 senses a voltage on the capacitor C1 to determine the state of the signal stored thereon. The signal represented by the voltage stored on the capacitor C1 is regenerated as a logic signal by the Schmitt X3 and the regenerated value is provided for use by the RFID chip. Accordingly, the signal stored on the capacitor C1 is restored even though there is no latch functionality

of the circuit. The voltage stored on the capacitor is not restored to the circuit as such until the tloaden signal is asserted once more, but the output from the latch circuit (q) and the feedback node dn may be correctly re-estabfished (assuming the power-off period is not too long) when power is restored and whilst tloaden is still de-asserted

When the input tloaden is re-asserted, the latch functionality of the circuit is enabled. If the input Ie is de-asserted when the input tloaden is re-asserted, the active-low tri-state inverter X2 restores the low-leakage node N to its initial condition (i.e., its condition before leakage started) and, if the input Ie is asserted when the input tloaden is asserted, a signal present on the input d is stored to the capacitor C1.

In one further embodiment, a VALID TRAM bit is a replica of the other TRAM bits with the exception that it uses a smalier storage capacitor. When data is written to a TRAM cell, a "high" voltage is also stored on the capacitor within the VALID TRAM cell. When power is removed from the RFID chip, the voltage stored on the capacitor of the VALID TRAM cell discharges at a higher rate than bits in other TRAM cells (assuming the same leakage for all cells). When power is restored, the contents of the VALID TRAM storage is checked. If the VALID TRAM storage node capacitance was still deemed to be "high", preferably, the contents of all other TRAM cells is assumed to be valid. However, each cell may be tested or checked separately; if desired. However, it is to be noted that unless a VALID TRAM bit is used, there may be no way of knowing if "low" data in a TRAM cell is due to the voltage having decayed too far, or if the original stored data was "low". If the VALID TRAM storage node capacitance was deemed to have discharged to a "low" voltage, the contents of all other TRAM cells is deemed to be invalid (and may be reset at this point).

It is also noted that while the schematic of figure 1 is a simplified implementation, in practice, TRAM cells may have non-inverting input and output stages so that a "1" on the data input results in a positive voltage being stored on the storage capacitor; and TRAM cells may also comprise a reset signal so that they can be easily reset (e.g., when deemed invalid). In further embodiments, TRAM based flip-flops may be constructed as well as TRAM based latches.

The signal input tloaden is used to determine just how "substantially" the data stored in the data cell is a copy of the input data. If tloaden is simply a logic signal driven to the same voltage supply that is used by the data latch, there .may be a degradation of the applied signal once it is in the storage cell, due to the threshold voltage drop of the isolating transistor. This may still be effective, but the retention time may be reduced. If, tloaden is driven to a threshold voltage above the latch power supply, there is substantially no signal degradation as it is stored.

It would be recognised by the person skilled in the art that although embodiments of the present invention substantially isolate at least a portion of the data storage cell from leakage, leakage in some small form may be ever-present.

Effectively, embodiments of the present invention function to isolate the data storage node from any "normal" discharge paths so that substantially the only cause for discharge of the storage node is due to parasitic leakage (in the preferred embodiment due mainly to sub-threshold conduction of the isolating transistor and leakage from a reverse biased diode formed by the drain of the isolating transistor). The drain is preferably kept as physically small as possible. to minimise such leakage.

A preferred embodiment of the present invention implements the use of NMOS devices for the isolating switch MN1 and also for the capacitor C1. C1 is typically implemented as an NMOS transistor with drain, source and bulk connected to substrate, and with the gate tied to the storage node N. It should be noted however, that the capacitor may also be implemented successfully using a

PFET transistor. Using a PFET transistor in a similar circuit configuration may provide an improved capacitor, per se, than an NMOS transistor because it operates in accumulation and has close to a voltage-independent capacitance, whereas an NFET capacitor's capacitance may drop to about 50% as the voltage stored on it passes through the NFET threshold. However, it is preferred to use

NMOS technology in a preferred embodiment because PFETs in an NWELL process may require additional NWELL spacing, leading to inferior area usage on the chip.

Data state restoration into the storage cell is not necessarily immediate when power is applied. This is because it is necessary to give the cell time to

decide what value to restore. In a preferred embodiment, the process is as follows:

1. When power is applied to the chip, the tloaden signal is driven to a suitable voltage (e.g. VDD + VthN,) so that when the data latch is loaded with data, an accurate representation of the data signal is stored on the storage node.

2. When the source of power is lost (but power is still available on the chip: stored in power supply decoupling capacitors), the tloaden signal is immediately de-asserted, causing the storage node to become isolated, thereby storing the signal temporarily.

3. The chip's power supply may drop rapidly because there are many conduction paths, whereas the cell storage latch decays slowly because it is substantially isolated from as many leakage paths as is possible.

4. When power is re-applied to the chip, tloaden is not re-applied immediately, but instead is delayed for a short time while the sensing circuit (the Schmitt trigger) determines what value was previously stored by determining if the voltage on the storage node is above or below it's sensing threshold.

5. After the short delay (determined by a timing circuit triggered by the release of the chip's reset signal), the tloaden signal is once again reapplied, and, assuming there is no attempt to load the fatch from an external source at the same time, the feedback circuit of the latch restores the original signal to its full value on the storage node.

While this invention has been described in connection with specific embodiments thereof, it will be understood that it is capable of further modification(s). This application is intended to cover any variations uses or adaptations of the invention following in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains and as may be applied to the essential features hereinbefore set forth. For example, the TRAM circuit of a preferred embodiment of the present invention restores its own value

(when tloaden is asserted), however, the inventor envisages that it may also

rather than restoring its own previously stored value, "re-store" a value that is passed to it by an external source.

As the present invention may be embodied in several forms without departing from the spirit of the essential characteristics of the invention, it should be understood that the above described embodiments are not to limit the present invention unless otherwise specified, but rather should be construed broadly within the spirit and scope of the invention as defined in the appended claims. Various modifications and equivalent arrangements are intended to be included within the spirit and scope of the invention and appended claims. Therefore, the specific embodiments are to be understood to be Illustrative of the many ways in which the principles of the present invention may be practiced. In the following claims, means-pius-function clauses are intended to cover structures as performing the defined function and not only structural equivalents, but also equivalent structures. For example, although a nail and a screw may not be structural equivalents in that a nail employs a cylindrical surface to secure wooden parts together, whereas a screw employs a helical surface to secure wooden parts together, in the environment of fastening wooden parts, a nail and a screw are equivalent structures.

"Comprises/comprising" when used in this specification is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof." Thus, unless the context clearly requires otherwise, throughout the description and the claims, the words 'comprise', 'comprising', and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to".