In particular the invention relates to frequency discriminators implemented in such frequency lock loops for achieving frequency lock. The invention also relates to applications for frequency lock loops that utilise such frequency discriminators.

BACKGROUND TO THE INVENTION Telecommunications equipment utilises stable frequency standards for a range of purposes and these are typically implemented with a temperature compensated crystal oscillator (TCXO). For example, frequency synthesisers, which are a core component of telecommunications devices such as FM transmitters and receivers, require a TCXO to facilitate the generation of stable output signals. In practice the TCXO provides a stable frequency standard to ensure the synthesiser functions correctly over a wide range of ambient conditions. Usually TCXO's have a fixed output frequency which can limit their use in certain applications. While voltage controlled crystal oscillators (VCXO) are available their stability characteristics are not adequate for many applications.

For example, typically a frequency synthesiser utilises a phase lock loop (PLL) to synthesise a stable output frequency based on a reference frequency obtained by dividing down the TCXO frequency standard. The output frequency can be adjusted as required to a multiple of the reference frequency by adjusting a divider value in a feedback path of the PLL. The constraint of a PLL is that the output frequency can only be adjusted to a frequency resolution determined by the division ratio of the frequency divider and the choice of frequency reference. Therefore it is not possible to adjust the output frequency to an arbitrarily fine resolution. To increase the output frequency resolution of the PLL it is possible to use a divider which facilitates a larger division ratio in conjunction with a lower reference frequency. One of the drawbacks of this approach is that the smaller the reference frequency, the longer it takes the PLL to achieve phase lock.

One solution is to use a reference signal source which has an adjustable output frequency. In this way the reference frequency can be increased when coarse frequency adjustment is appropriate to achieve a fast phase lock time. The reference frequency source may then be adjusted to interpolate in between the course frequency steps of the frequency synthesiser.

However, the stability characteristics of conventional adjustable crystal oscillators which provide the reference frequency are not always adequate for some synthesiser applications.

Therefore it may be advantageous to have telecommunications devices and equipment, in which the reference signal is adjustable to provide arbitrarily fine resolution, and in which the reference signal has suitable stability characteristics. It would also be desirable to have a reference signal source which provides a stable output frequency which is adjustable to an arbitrarily fine resolution.

SUMMARY OF INVENTION It is an object of the invention to provide an apparatus which can be utilised to provide a stable and adjustable output frequency.

Alternatively, it is an object of the invention to provide an apparatus for providing a stable and adjustable carrier frequency that can be modulated.

It will be appreciated by those skilled in the art that in this context, frequency discrimination relates to the generation of an error signal which indicates the difference in frequency between two signals. The frequency discriminator can form a functional block of a frequency lock loop (FLL) which generates a stable output frequency based on a reference frequency.

The FLL also facilitates adjustment or offset of the output frequency, by way of a DC input.

As well as being adjustable to provide a frequency offset from the"free running"frequency of a signal generator, the output frequency is modulatable by a varying signal. The term"stable" is used to refer to when the nominal output frequency is stable. This is the frequency when the free running output signal is"locked"with the reference frequency of the FLL, including any offset due to a DC input

In one aspect the present invention may be said to consist in a frequency lock loop including: a phase discriminator for generating a phase error signal indicative of phase error between a feedback signal and reference signal, a filter for extracting from the error signal, a interim signal relating to frequency difference between the feedback and reference signals, a differentiator for differentiating the interim signal to obtain a frequency error signal, an integrator for generating a control signal for a signal generator from the frequency error signal, and a signal generator for producing an output signal with a frequency adjusted by the control signal, wherein the feedback signal is or is derived from the output signal.

In another aspect the present invention may be said to consist in a frequency discriminator for frequency lock loop including: a phase discriminator for generating a phase error signal indicative of phase error between two input signals, a filter for extracting from the error signal, a interim signal relating to frequency difference between the input signals, a differentiator for differentiating the interim signal to obtain a frequency error signal.

In another aspect the present invention may be said to consist in an apparatus for generating a frequency modulated output signal including: a frequency synthesiser for producing an output signal with a nominal frequency, including a feedback loop to stabilise the nominal frequency based on its relationship with a reference frequency, an modulation input for introducing a signal to modulate the output signal, and a frequency lock loop for generating the reference frequency, including a offset input for adjusting the reference frequency to an arbitrary resolution.

In another aspect the present invention may be said to consist in an apparatus for generating a frequency modulated output signal including: a frequency synthesiser for producing an output signal with a nominal frequency, including a feedback loop to stabilise the nominal frequency based on its relationship with a reference frequency, a modulation input for introducing a modulating signal to modulate the output signal, and a frequency lock loop input for generating the reference frequency, the frequency lock loop including: a phase discriminator for generating a phase error signal indicative of phase error between a feedback signal and input reference signal, a filter for extracting from the error signal, a interim signal relating to frequency difference between the feedback and input reference signals, a differentiator for differentiating the interim signal to obtain a frequency error signal, an integrator for

generating a control signal for a signal generator from the frequency error signal, and a signal generator for producing the reference frequency as an output signal with a frequency adjusted by the control signal, wherein the feedback signal is or is derived from the reference frequency output signal.

In another aspect the present invention may be said to consist in an apparatus for generating a frequency modulated output signal including: a first phase discriminator for generating a phase error signal indicative of phase error between a first feedback signal and input reference signal, a filter for extracting from the error signal, a interim signal relating to frequency difference between the feedback and reference signals, a differentiator for differentiating the interim signal to obtain a frequency error signal, an integrator for generating a first control signal from the frequency error signal, a first signal generator for producing a reference frequency output signal with a frequency adjusted by the first control signal, wherein the first feedback signal is or is derived from the frequency reference output signal, a second phase discriminator for generating a phase error signal indicative of phase error between the reference frequency output signal and a second feedback signal, a filter for generating a second control signal from the phase error signal, a second signal generator for producing an output signal with a frequency adjusted by the second control signal, wherein the second feedback signal is or is derived from the output signal.

BRIEF LIST OF FIGURES Preferred embodiments of the invention will be described with reference to the accompanying drawings of which: Figure 1 is a block diagram of a frequency lock loop according to the invention, Figure 2a is block diagram of a first embodiment of a phase discriminator utilised in the frequency lock loop, Figure 2b is a timing diagram showing waveforms at various points in the frequency lock loop utilising the first embodiment of a phase discriminator, Figure 2c is a block diagram of one possible embodiment of the multiplier and signal processing block shown in Figures 1 and 2a for generating a frequency difference signal, Figure 3a is block diagram of a second embodiment of a phase discriminator utilised in the frequency lock loop, Figure 3b is a timing diagram showing waveforms at various points in the frequency lock loop utilising the second embodiment of a phase discriminator, Figure 4a is block diagram of a third embodiment of a phase discriminator utilised in the frequency lock loop, Figure 4b is a timing diagram showing waveforms at various points in the frequency lock loop utilising the third embodiment of a phase discriminator, Figure 5a is a block diagram of a phase lock loop frequency synthesiser utilising a frequency lock loop according to the invention, and Figure 5b is a conventional single phase lock loop frequency synthesiser.

DETAIL DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the drawings it will be appreciated that FLLs, frequency discriminators and their applications according to the invention can be implemented in various forms. The following examples are given by way of example only. The function of phase lock loops will be known to those skilled in this area of technology and will therefore only be briefly described here.

Figure 1 shows a block diagram indicating the overall functional structure of a FLL 1 according to the invention. The FLL 1 generates an output signal 19 that has a frequency

"locked"to or dependent upon a reference frequency 17. The reference signal may originate from any suitable stable frequency source such as a temperature compensated crystal oscillator (TCXO) 20. A phase discriminator 11 receives the reference signal 17 at an input along with a feedback signal 18. The feedback signal may either be the output signal 19 of the FLL 1 or alternatively a signal derived from the output signal 19. For example, a variable divider 10 may optionally be placed in the feedback path to make the feedback signal 18 a fraction of the output signal 19. In this case the output signal 19 frequency will be Nv times the reference signal 17 frequency. In another optional alternative a variable divider 10 is placed between the TCXO 20 and phase discriminator 11 (Could be Or or AND). The phase discriminator generates a phase error signal corresponding to the phase error between the reference signal 17 and the feedback signal 18. This error signal is fed into a low pass filter 12 which extracts the difference frequency components to generate a signal, the slope of which contains information relating to the frequency difference between the reference signal 17 and the feedback signal 18. This signal is then differentiated by differentiator 13 to generate a frequency error signal with an amplitude proportional to the difference between the feedback 18 and reference 17 signal frequencies. The phase discriminator 11, low pass filter 12, differentiator 13 and subsequent signal processing block together form the frequency discriminator 2 of the FLL 1.

As can be seen in Figure 1 a modulating signal can be added to the frequency error signal by way of an adder 14. Adding a modulating signal to the frequency error signal enables modulation of the output signal 19 down to DC. Therefore a DC voltage can be added to synthesise a frequency offset in the FLL 1 output signal 19. This enables a nominal output frequency of the FLL 1 to be adjusted to an arbitrarily fine resolution. Arbitrarily fine resolution is intended to mean that the level of precision of frequency adjustment is not limited by the reference frequency or divider characteristics. If a varying modulating signal is added, this will modulate the nominal output frequency which is determined by the DC component. The nominal frequency will remain stable due to the feedback loop arrangement.

The frequency error signal, and modulating signal if added, is then passed to an integrator 15 which integrates the signal to generate a control signal for a signal generator 16, such as a voltage controlled oscillator (VCO) or voltage controlled crystal oscillator (VCXO). The control signal adjusts the signal generator 16 such that the output signal 19 has a frequency which tracks that of the reference frequency by way of negative feedback, adjusted by any DC

modulating component, as described above. If the output frequency waivers from the reference frequency (or a multiple of the reference frequency if a divider is used) then a frequency error signal is generated indicative of the frequency difference between the signals which in turn is used to adjust the signal generator such that the output frequency is returned to the required value. Further if the divider value Nv is altered, then the FLL 1 automatically adjusts the output frequency 19 such that it settles at a frequency Nv times the reference frequency, plus any offset due to a DC input adjustment.

Figure 2a is a block diagram of a preferred embodiment of a phase discriminator 11 employed in the frequency discriminator 2 portion of the FLL 1. Figure 2b shows the waveforms present at various locations in the phase discriminator 11 during operation. This quadrature exclusive-or phase discriminator includes a first exclusive-or gate 21a and a second exclusive-or gate 21b. Figure 2a also shows the discriminator including a VCO, reference signal generator, two low pass filters and two differentiators. Strictly speaking these are not part of the discriminator 11 but rather are the VCO 16, reference signal 17, low pass filter 12 and differentiator 13 of the FLL 1 in Figure 1. However they are shown as part of the discriminator 11 for clarity.

In this embodiment of the discriminator the signal generator 16, which is part of the FLL 1, is a VCO which outputs a square wave signal 19 as two 1 : 1 mark space ratio square 19a, 19b wave quadrature components with a 90° phase relationship. These then form the feedback signal 18. It will be appreciated that in FLL 1 embodiments which incorporate a divider in the feedback path, the feedback signal 18 will not necessarily be the same as the VCO output signal 19. However in this embodiment there is a direct coupling between the VCO 16 and phase discriminator and therefore the square wave outputs 19a, 19b become feedback signals 18a, 18b. (An equivalent discriminator is also achieved if the reference signal, rather than the VCXO signal, is arranged to provide the two square wave phase quadrature waveforms). The in-phase (I) component signal is fed into the first exclusive-or gate 21a and the quadrature- phase (P) component signal is fed into the second exclusive-or gate 21b. The reference signal 17 is a 1: 1 mark space ratio square wave which is generated by a reference signal generator 20. The signal 17 is passed to both the first 21a and second 21b exclusive-or gates. The output of each exclusive-or gate 21a, 21b is passed into a respective low pass filter 12a, 12b, both of which form the low pass filter 12 shown in Figure 1. The output of both filters 12a,

12b are then passed to a respective differentiator 13a, 13b which form the differentiator 13 shown in Figure 1.

Operation of the phase discriminator will now be described with reference to the timing diagrams in Figure 2b. The I component 18a of the VCO 16 output is exclusive-ored with the reference signal 17 to produce an in phase beat frequency 25a indicating the phase difference between the two signals 18a, 17. Similarly the Q component 18b of the VCO 16 output is exclusive-ored with the reference signal 17 to produce a quadrature phase beat frequency 25b indicating the phase difference between the two signals 18b, 17. Each beat frequency signal 25a, 25b is passed through the respective low pass filter 12a, 12b to extract the difference frequency component. This generates respective symmetrical triangular waveforms 26a, 26b which are shown superimposed on beat frequency signals 25a, 25b in Figure 2b. These waveforms 26a, 26b are in phase quadrature relationship, either plus or minus 90°, dependent on whether the VCO signal 18 frequency is high or low in respect to the reference signal 17.

The magnitude of the slope of the triangular waveforms 26a, 26b are proportional to the frequency difference between the reference signal 17 and the VCO output signal 18. The relative phase difference between the two quadrature phase triangular waveforms indicates which of the signals 17, 18 has a higher frequency.

To determine this information each triangular waveform 26a, 26b is passed to a respective differentiator 13a, 13b to determine the slope of the respective waveforms. dI/dt and dQ/dt are calculated by the respective differentiators 13a, 13b to produce square waves 27a, 27b from which the frequency difference, and relative sense, between the reference signal 17 and output signal 18 can then be determined. This information is derived in the signal processing block after the differentiators 13a, 13b. One possible embodiment of the signal processing block is shown in Figure 2c. The dI/dt waveform 27a is multiplied by the sign, 1, of the Q triangular waveform 26b to produce a DC voltage offset 28b proportional to the frequency offset and polarised to the direction of the VCO output offset. Similarly, the dQ/dt waveform 27b is multiplied by the sign, 1, of the I triangular waveform 26a to produce a DC voltage offset 28a. These DC voltages 28a, 28b may either be combined by subtraction or individually processed to provide the frequency discriminator 2 output signal or function..

This in turn can be passed to the integrator 15 shown in Figure 1 to provide the VCO control

line signal for input into the VCO. This can take place in a DSP. 16. The associated ripple voltage produced by the frequency discriminator 2 is substantially zero.

Figure 3a shows a second embodiment of a phase discriminator for the frequency discriminator 2 of the FLL 1. Figure 3b shows the associated timing diagrams. The edge triggered RS flip flop shown functions as a phase discriminator. A feedback clock edge signal 18 from the VCO sets the RS flip flop and clock edge signal 17 from the reference, resets the RS flip flop. The Q output of the RS latch 30 is passed to a first low pass filter 12a (shown Figure 2a) that generates a triangular waveform 31. Figure 3b shows the resulting square waveform 32 at the Q output with the superimposed positive ramp filtered sawtooth waveform 31 when fv>fr. This becomes a negative sawtooth ramp 33 when fv<fr and therefore the ambiguity of the sense of the FLL 1 present with the exclusive-or gate is removed. Both the frequency error and the sense of the loop are fully defined by the slope of the ramp of the filtered sawtooth waveform. However with this type of phase discriminator the discontinuity associated with the fast edge of the sawtooth needs to be removed from the differential output.

Figure 4a is a block diagram of a third embodiment of a phase discriminator 11 employed in the frequency discriminator 2 portion of the FLL 1 and employs four D-type flip flops 40a- 40d. The two D-type flip flops 40c and 40d are optional. Flip flop 30c outputs the beat frequency when fv>fr, and flip flop 40d outputs the beat frequency when fv<fr. The cross coupled nand gate 41a and 41b indicates fv>fr with a logic high at the output of gate 41a and a logic low when fv<fr. Figure 4b shows the waveforms present at various locations in the phase discriminator 11 during operation. The D inputs of the first and second flip flops 40a, 40b are held high. The feedback signal 18 which is a square wave output signal 19 from the VCO 16 in the FLL 1 is fed into the clock inputs of the first and third flip flops 40a, 40c while the reference signal 17 is fed into the clock inputs of the second and fourth flip flops 40b, 40d. The Q output of the first and second flip flops 40a, 40b are fed into a NAND gate 42 and the resulting signal fed into the reset input of the first and second flip flops 40a, 40b.

The Q outputs of both the first and second flip flops (Q1, Q2) are fed into a low pass filters 12a, 12b, which form the low pass filter 12 shown in Figure 1.

Operation of the phase discriminator is similar to the RS flip flop of Figure 3 a. However with this arrangement a filtered positive ramp sawtooth waveform appears at the output of the filter 12a when fv>fr and at the output of filter 12b when fv<fr. There are a number of options for subsequent signal processing but, similar to the RS-flip flop, unambiguous beat frequency information is defined by the slope of the filtered sawtooth waveforms. Operation will now be described in more detail with reference to the timing diagram in Figure 4b. The first two D flip flops 40a, 40b receive at their respective reset inputs feedback from their Q outputs via the NAND gate 42. This produces a beat frequency square wave at one of the Q outputs indicating the phase difference between the feedback signal 18 and the reference signal 17.

The beat frequency signal appears at the Q output of the D type flip flop 40a, 40b which has the highest frequency input signal. For example if the frequency of the feedback signal 18 (fv) is greater than the frequency of the reference signal 17 (fr) then the beat frequency output appears at the output of the first flip flop 40a (Q1). In this case narrow spikes appear at the output of the second flip flop 40b (Q2) at the frequency fr. Similarly if fv < fr then the beat frequency output appears at Q2 and narrow spikes appear at Ql at frequency fv. The complements of these waveforms appear at outputs Q1'and Q2'.

For example as shown in Figure 3b, the VCO feedback signal 18 (the transition edges of which are shown) has a frequency which is less than the reference signal 17 frequency (the transition edges of which are also shown). Therefore the quad D type phase discriminator outputs the beat frequency resulting from the square wave 43b at Q2, while a spiked waveform 43a at frequency fv appears at Q1. The output of low pass filter 12b is the beat frequency sawtooth waveform 45 (superimposed on the square waveform 43b) which contains information regarding the frequency difference between the reference signal 17 and the feedback signal 18. More particularly the slope of the triangular waveform 45 is proportional to the frequency difference between the reference signal 17 and the feedback signal 18. Due to symmetry, it will be appreciated that where the feedback frequency 18 is greater than the reference frequency 17 then the sawtooth waveform appears at the output of the low pass filter 12a coupled to output Q1.

When implemented in the FLL 1, the quad D-type discriminator 11 can generate the frequency difference information in several ways. For example, the two sawtooth waveforms

appearing at the outputs of the filter 12a and 12b may be subtracted to produce a combined sawtooth waveform similar to the edge triggered RS phase discriminator solution.

The optional D type flip flops 40c and 40d produce a square wave beat frequency at Q4 when fv<fr, as shown in Figure 4b, and a Q3 when fv>fr. The level triggered RS nand gates 41 a and 41b further process Q3 and Q4 outputs to sense the frequency difference. Nand gate 41 a output is high when fv>fr and nand gate 41b is high when fv>fr. Both the square wave beat frequency and the frequency sense are available for optional signal processing.

When implemented in the FLL 1 the quad D flip flop discriminator 11 can generator the frequency difference function in one of several ways. The filtered output from either Q1 or Q2, (we will assume Q2 for this explanation for consistency with the case shown in Figure 3b) is passed to the corresponding differentiator 13b which outputs a waveform 45 that is the slope of the filtered waveform and indicates the frequency difference between the reference signal 17 and the feedback signal 18. The outputs of the RS flip flop may be used to add sense information to the raw frequency difference function 45. The resultant waveform can then be passed to the integrator 15 in the FLL 1. Alternatively the frequency difference function including sense information can be obtained by combining the filtered output Q2 signal with the filtered output Q1'signal to produce a sawtooth waveform which incorporates sense information. This waveform is then passed to the differentiator 13 to produce the frequency difference function for passing to the integrator 15.

The FLL 1 embodiments can be implemented using any suitable electronics technologies. At least part of the frequency discriminator 2 and or remainder of the FLL 1 are implemented in a DSP. Some or all of the phase discriminators 11 filters 12, differentiators 13 and/or subsequent processing can be implemented in a DSP, as well as the integrator 16 and divider.

In a preferred embodiment, the differentiators 12 and subsequent processing are implemented in a DSP.

Another preferred embodiment of the invention is shown in Figure 5a which provides frequency synthesis to an arbitrary level of resolution and also frequency modulation. It enables fine control of the carrier frequency, while still ensuring the nominal frequency of the output (without modulation) meets stability requirements for telecommunications purposes.

Figure 5a shows utilisation of the FLL 1 as a stable and adjustable reference signal source for a PLL. The PLL shown is a simplest form of a frequency synthesiser according to the invention. It could, if required, be replaced by more complex forms of frequency synthesisers, as will be appreciated by those skilled in the art. The adjustability of the FLL 1 enables finer control of the output frequency of the PLL than if a fixed frequency reference source is used.

The FLL 50 and PLL 51 portions are shown in dashed outlines in Figure 5. The FLL 50 is as described in relation to Figure 1 although the phase discriminator 11, low pass filter 12 and differentiator 13 have been combined into one frequency discriminator 53 block for clarity.

The phase discriminator 11 could be any suitable discriminator, such as those described in relation to Figures 2a to 4b. The PLL 51 arrangement is known to those in the art can be any suitable configuration. In this embodiment the PLL includes a divider 54 for down converting the FLL 50 output signal frequency 19. The signal is then passed to a phase discriminator 55 along with a feedback signal. The phase discriminator 55 generates an error signal indicative of the phase difference between the feedback signal and the output signal frequency 19. This is passed to a loop filter 56 to generate a control signal for a VCO 57 of the PLL. The control signal adjusts the output signal phase of the VCO 57 so that is reaches phase lock based on the output signal frequency 19. The output of the VCO 57 is passed to a variable divider 58 the output of which forms the feedback signal.

The arrangement in Figure 5a enables triple point modulation, wherein a modulating signal can be injected at the adder 14, input to the FLL VCXO 16 and/or the input to the PLL VCO 57. The signal amplitude contribution at each of the three injection points has the same phase and equal modulation contributions. The modulating signal injected at the adder 14 can modulate the output signal from the VCO 57 down to DC to generate a frequency offset. This enables the output frequency of the VCO 57 to be adjusted to an arbitrarily fine resolution as required. This will be explained more fully by way of the following example.

Figure 5b illustrates a conventional single loop frequency synthesiser employing two integer frequency dividers Nf and Nv (fixed and variable). It is well known that the VCO frequency fo=fsNv/Nf where fs here the TCXO frequency. The frequency resolution fr=fs/Nf, since if Nv is changed by one, fo changes by fr. For example, suppose the required VCO frequency is 400MHz, the TCXO is 12. 8MHz, and fr=6. 25kHz. It follows that Nf=12. 8MHz/6. 25kHz=2048 and Nv=400MHz/6. 25kHz=64000. If the variable divider Nv is

incremented by one, the VCO frequency changes to 400. 00625MHz. Note that this corresponds to an increment in the VCO frequency, in parts per million, of 6250/400=15. 63ppm. Note also that if the TCXO is in error by lppm, ie 12.8Hz, the VCO will be the same lppm error or 400Hz.

The invention as described in relation to Figure 5a incorporating a frequency locked loop enables fine frequency resolution to be achieved, ie <fr, and to enable baseband modulation of the VCXO via the FLL. For example, suppose the requirement is to increase the VCO frequency of 400MHz by 3.125kHz which is not available from the synthesiser by changing Nv. The increment required in ppm is 3125/400=7.81ppm. The VCXO has to be incremented by the FLL by 7. 81ppm, or 100Hz to 12800100Hz. Suppose within the FLL frequency discriminator sensitivity is 25ppmlV. This means that if the VCXO frequency exceeds the TCXO by 25ppm, the voltage appearing at the output of the frequency discriminator will be 1V. Therefore to synthesise the required 3.125KHz from the VCO, the required 7. 81ppm and will require a DC voltage applied to the adder in the FLL of 1Vx 7. 81ppm/25ppm=0. 31V. Note that if 3.125KHz increment is now required from the VCO at 500MHz, Nv=500MHz/6. 25kHz=80000, and the required ppm reduces by 400/500 or 3125/500=6. 25ppm or a DC voltage of 1V x 6.25/25=0. 25V. The required DC input voltage is therefore VCO frequency dependent and the required computation illustrated above may be implemented within a DSP.

The gain of the FLL is a function of the frequency discriminator gain and the VCXO gain both conveniently measured in ppm/volt. These parameters determine the modulation bandwidth of the FLL which for noise reasons is typically limited to well below full audio bandwidth. For this reason modulation which is applied to the FLL is typically applied both to the adder input as discussed and added to the VCXO control line. With such an arrangement the theoretical modulation bandwidth of the FLL is unlimited. However, the main frequency synthesiser PLL has similar modulation bandwidth constraints, this time dependent on the parameters which include VCO sensitivity, the division ratio Nv, the phase discriminator gain, and the loop filter gain. Frequency synthesisers alone frequently employ dual-point modulation where the TCXO is substituted by a VTCXO, voltage controlled temperature compensated crystal oscillator. This option is not illustrated but essentially the similar to Figure 5a. Here the frequency modulating signal is applied both to the VTCXO

and VCO control line. Again the modulation bandwidth can be extended, theoretically, without limit. Triple-point modulation as illustrated in the diagram is used in the synthesiser according to the invention.

It will be appreciated that other applications of the FLL according to the invention are also possible. The invention is not just restricted to the embodiments described, and can include a range of applications that provide frequency synthesis and frequency modulation. The FLL can provide a reference frequency in other applications where a stable but adjustable signal is desirable.