MICROPHONES

BACKGROUND

[0001] Embodiments of the invention relate to independently adjustable positive and negative charge pumps for a differential microphone.

[0002] Mechanical and electrical variations in sense-capacitors (or microphone electrodes), namely the mechanical sensitivity and total capacitance, can be compensated for by adjusting a bias voltage on the sense-capacitor in order to achieve optimal microphone performance. For a differential microphone utilizing positive and negative biasing two separate sense-capacitors are required, each having their own mechanical and electrical variations.

SUMMARY

[0003] Independent adjustment of the positive and negative biasing circuits allows for each sense-capacitor to be optimized individually.

[0004] Thus, one embodiment provides a microphone system. The microphone system includes a positive adjustable charge pump, a positive sense capacitor, a negative adjustable charge pump, a negative sense-capacitor, and a differential amplifier. The positive adjustable charge pump is configured to generate a positive bias voltage. The positive sense-capacitor is configured to receive acoustic pressure from a first direction and the positive bias voltage. The positive sense-capacitor is also configured to generate a positive sense voltage based on the acoustic pressure and the positive bias voltage. The negative adjustable charge pump is configured to generate a negative bias voltage. The negative sense-capacitor is configured to receive the acoustic pressure from the first direction and the negative bias voltage. The negative sense-capacitor is also configured to generate a negative sense voltage based on the acoustic pressure and the negative bias voltage. The differential amplifier is configured to receive the positive sense voltage and the negative sense voltage. The differential amplifier is also configured to generate a differential voltage based on the positive sense voltage and the negative sense voltage. [0005] Another embodiment provides a method of generating independent adjustable bias voltages for a differential microphone. The method includes generating, via a positive adjustable charge pump, a positive bias voltage based on a positive reference voltage and a positive input voltage. The method also includes applying the positive bias voltage to a positive sense- capacitor. The method further includes generating, via the positive sense-capacitor, a positive sense voltage based on the positive bias voltage and acoustic pressure from a first direction. The method also includes generating, via a negative adjustable charge pump, a negative bias voltage based on a negative reference voltage and a negative input voltage. The method further includes applying the negative bias voltage to a negative sense-capacitor. The method also includes generating, via the negative sense-capacitor, a negative sense voltage based on the negative bias voltage and the acoustic pressure from the first direction. The method further includes generating, via a differential amplifier, a differential voltage based on the positive sense voltage and the negative sense voltage.

[0006] Other aspects of the invention will become apparent by consideration of the detailed description and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Fig. 1 is an overhead-cutaway view of a differential microphone, in accordance with some embodiments.

[0008] Fig. 2 is a cross-section side view of the differential microphone of Fig. 1.

[0009] Fig. 3 is a schematic diagram of a differential microphone system, in accordance with some embodiments.

[0010] Fig. 4 is a schematic diagram of a positive Dickson charge pump, in accordance with some embodiments.

[0011] Fig. 5 is a schematic diagram of a negative Dickson charge pump, in accordance with some embodiments. [0012] Fig. 6 is a schematic diagram of a positive voltage doubler, in accordance with some embodiments.

[0013] Fig. 7 is a schematic diagram of a positive MOS charge pump, in accordance with some embodiments.

[0014] Fig. 8 is a schematic diagram of a negative voltage doubler, in accordance with some embodiments.

[0015] Fig. 9 is a schematic diagram of a negative MOS charge pump, in accordance with some embodiments.

[0016] Fig. 10 is a schematic diagram of a positive Dickson charge pump, in accordance with some embodiments.

[0017] Fig. 1 1 is a schematic diagram of a negative MOS charge pump, in accordance with some embodiments.

[0018] Fig. 12 is a schematic diagram of a circuit architecture for generating positive and negative reference voltages, in accordance with some embodiments.

DETAILED DESCRIPTION

[0019] Before any embodiments of the invention are explained in detail, it is to be understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the following drawings. The invention is capable of other embodiments and of being practiced or of being carried out in various ways.

[0020] Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising" or "having" and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. The terms "mounted,"

"connected" and "coupled" are used broadly and encompass both direct and indirect mounting, connecting and coupling. Further, "connected" and "coupled" are not restricted to physical or mechanical connections or couplings, and can include electrical connections or couplings, whether direct or indirect. Also, electronic communications and notifications may be performed using other known means including direct connections, wireless connections, etc. In addition, the terms "positive" and "negative" are used to distinguish one entity or action from another entity or action without necessarily requiring or implying any such attribute of the entity or action.

[0021] It should also be noted that a plurality of hardware and software based devices, as well as a plurality of different structural components may be utilized to implement the invention. Furthermore, and as described in subsequent paragraphs, the specific configurations illustrated in the drawings are intended to exemplify embodiments of the invention. Alternative

configurations are possible.

[0022] Fig. 1 illustrates a differential microphone 5 that includes a CMOS-MEMS device layer 10. The CMOS-MEMS device layer 10 is constructed primarily of silicon or other materials and includes both CMOS circuitry elements and one or more micro-electro-mechanical structures (MEMS devices) formed directly within the CMOS-MEMS device layer 10. The CMOS-MEMS device layer 10 of Fig. 1 includes a positive sense-capacitor 15 (or MEMS microphone electrode) and a negative sense-capacitor 20 (or MEMS microphone electrode). In the illustrated embodiment, the positive and negative sense-capacitors 15 and 20 are formed on the same package according to the same process. Therefore, acoustic pressures (i.e., sound) directed toward the top surface of the CMOS-MEMS device layer 10 cause substantially the same motion and deflection of the positive and negative sense-capacitors 15, 20.

[0023] Fig. 2 illustrates the same differential microphone 5 from a cross-sectional perspective. A lid 25 is positioned above the CMOS-MEMS device layer 10 to form an acoustic channel 30. An opening (or acoustic port) 35 in the lid 25 allows acoustic pressures (sounds) to enter the acoustic channel 30 and cause mechanical deflection of the positive and negative sense- capacitors 15, 20. As shown in Fig. 2, the positive and negative sense-capacitors 15, 20 are arranged equidistant from the acoustic port 35. Therefore, deflections of the positive and negative sense-capacitors 15, 20 caused by acoustic pressures entering through the acoustic port 35 are substantially the same in both the positive and negative sense-capacitors 15, 20. Below the CMOS-MEMS device layer 10 is a back-volume 40 component that allows the positive and negative sense-capacitors 15, 20 to move back and forth (or up and down) in response to the acoustic pressures.

[0024] Although the examples described herein refer to a CMOS-MEMS device layer 10, other constructions may include a MEMS device chip and a separate CMOS chip. In such constructions, the positive and negative sense-capacitors 15, 20 may be formed on the same chip (i.e., the MEMS chip). However, in still other constructions, the microphone system package can include two separate MEMS chips - one for each sense-capacitor - as long as the MEMS chips are arranged and manufactured such that a phase (or direction) of both the positive and negative sense-capacitors 15, 20 are the same. Furthermore, in other constructions, the position of the positive and negative sense-capacitors 15, 20 relative to the acoustic port 35 may be different than as illustrated in Fig. 2. For example, the positive and negative sense-capacitors 15, 20 can be sized and arranged so that they are both positioned directly below the acoustic port 35. In some embodiments, the positive and negative sense-capacitors 15, 20 are positioned such that they are not equidistant from the acoustic port 35.

[0025] Fig. 3 illustrates a differential microphone system 45 that uses dual polarity biasing with separately adjustable positive and negative charge pumps 50, 55 to provide biasing voltages for the positive and negative sense-capacitors 15, 20 of the differential microphone 5. Using separately adjustable positive and negative charge pumps 50, 55 enables the positive and negative bias voltages to be optimized for each sense-capacitor.

[0026] A first voltage source 60 generates a positive input voltage (VINp). The positive charge pump 50 receives the positive input voltage and a positive reference voltage (VREFp). The positive charge pump 50 generates a positive bias voltage (VBIASp) for the positive sense- capacitor 15 based on the positive input voltage and the positive reference voltage. A high- impedance device 62 is coupled between the positive charge pump 50 and the positive sense- capacitor 15. As used herein, a high-impedance device can include one or more electronic components designed to increase impedance between a voltage source and a mechanical or electronic component (e.g., the positive sense-capacitor 15). In some embodiments, the high- impedance device 62 includes, among other components, a pair of anti-parallel diodes 64 and a switch 65. The positive sense-capacitor 15 is coupled to a reference node 67 via a high- impedance device 70. In some embodiments, the high-impedance device 70 includes, among other components, a pair of anti -parallel diodes 72 and a switch 73. The positive sense-capacitor 15 is also coupled to a first terminal of a differential amplifier 75. In some embodiments, the positive input voltage is equal to a voltage of the reference node 67. In some embodiments, the reference node 67 is a ground node (e.g., earth ground).

[0027] In some embodiments, a second voltage source 80 generates a negative input voltage (VINp), as illustrated in Fig. 3. In other embodiments, the first voltage source 60 also generates the negative input voltage. The negative charge pump 55 receives the negative input voltage and a negative reference voltage (VREFN). The negative charge pump 55 generates a negative bias voltage (VBIASN) for the negative sense-capacitor 20 based on the negative input voltage and the negative reference voltage. A high-impedance device 85 is coupled between the negative charge pump 55 and the negative sense-capacitor 20. In some embodiments, the high-impedance device 85 includes, among other components, a pair of anti-parallel diodes 87 and a switch 88. The negative sense-capacitor 20 is coupled to the reference node 67 via a high-impedance device 90. In some embodiments, the high-impedance device 90 includes, among other components, a pair of anti-parallel diodes 92 and a switch 93. The negative sense-capacitor 20 is also coupled to a second terminal of the differential amplifier 75. In some embodiments, the negative input voltage is equal to the voltage of the reference node 67.

[0028] During a power-on-reset phase, the positive bias voltage is applied to the positive sense-capacitor 15. At the same time, the negative bias voltage is applied to the negative sense- capacitor 20. After the power-on-reset phase, incident positive sound pressure causes capacitances across both the positive and negative sense-capacitors 15, 20 to increase in value. A positive sense voltage (VSENSEp), applied to the first terminal of the differential amplifier 75, increases with respect to the reference node 67 due to the increase in capacitance and positive charge across the positive sense-capacitor 15. Similarly, a negative sense voltage (VSENSEN), applied to the second terminal of the differential amplifier 75, increases with respect to the reference node 67 due to the increase in capacitance and the negative charge across negative sense-capacitor 20. The positive and negative sense voltages are combined by the differential amplifier 75 to produce a differential voltage (VDIFF) that represents the difference between the positive and negative sense voltages at any given time.

[0029] Adjusting the positive bias voltage (e.g., with the positive charge pump 50) enables compensation for mechanical stiffness, geometry, and capacitance variation in the positive sense- capacitor 15. The mechanical stiffness and capacitance variation can be caused by process variations in the manufacturing of the positive sense-capacitor 15. Adjusting the positive bias voltage allows for setting a desired sensitivity of the positive sense voltage in order to maximize signal swing and the signal-to-noise ratio (SNR) of the positive sense-capacitor 15. The negative sense-capacitor 20 may have a different mechanical stiffness, geometry, and capacitance variation than the positive sense-capacitor 15. The negative charge pump 55 enables

independent adjustment of the negative bias voltage in order to set a desired sensitivity of the negative sense voltage and maximize the signal swing and the SNR of the negative sense- capacitor 20. The positive and negative bias voltages can further be adjusted to compensate for geometrical differences between the positive and negative sense-capacitors 15, 20.

[0030] The acoustic performance of the positive sense-capacitor 15 can be measured by setting the high-impedance device 90 to a low impedance state. In some embodiments, the high- impedance device 90 is set to the low impedance state when the switch 93 is closed. In some embodiments, a non-volatile memory element (e.g., a polysilicon fuse) is used adjust the positive bias voltage in order to set a desired performance of the positive sense-capacitor 15. Similarly, the acoustic performance of the negative sense-capacitor 20 can be measured by setting the high- impedance device 70 to the low impedance state. In some embodiments, the high-impedance device 70 is set to the low impedance state when the switch 73 is closed. In some embodiments, a non-volatile memory is used to adjust the negative bias voltage in order to set a desired performance of the negative sense-capacitor 20.

[0031] Various charge pump structures can be used generate the positive and negative bias voltages. In one embodiment, the positive and negative charge pumps 50, 55 include a Dickson charge pump.

[0032] Fig. 4 illustrates a positive Dickson charge pump 100 for generating the positive bias voltage. After a rising edge of a CLK signal, diode 105 becomes forward biased and capacitor 1 10 at node A is charged to the positive input voltage (VINp). After a falling edge of the CLK signal, diode 105 becomes reverse biased and the voltage of capacitor 1 10 at node A is boosted to the positive input voltage plus a positive reference voltage (VREFp). Also, diode 1 15 becomes forward biased and the capacitor 120 at node B is charged to the same voltage as capacitor 1 10 at node A. Each positive Dickson stage follows this operation with capacitor 125 at node D switching between VIN _P + (4 X VREFp) and VIN _P + (3 X VREFp). In the configuration illustrated in Fig. 4, the positive bias voltage is VIN _P + (4 X VREFp). Neglecting inter-stage leakage currents and the output load current, the positive Dickson charge pump 100 produces a positive bias voltage of:

VBIASp = VINp + (n X VREFp); where n indicates the number of positive Dickson stages in the positive Dickson charge pump 100.

[0033] Fig. 5 illustrates a negative Dickson charge pump 130 for generating the negative bias voltage. After a falling edge of a CLK signal, diode 135 becomes forward biased and a capacitor 140 at node A is charged to the negative input voltage (VINN). After a rising edge of the CLK signal, diode 135 becomes reverse biased and the voltage of capacitor 140 at node A is boosted to the negative input voltage plus a negative reference voltage (VREFN). Also, diode 145 becomes forward biased and capacitor 150 at node B is charged to the same voltage as capacitor 140 at node A. Each negative Dickson stage follows this operation with capacitor 155 at node D switching between VIN _N - (4 X VREF _N ) and VIN _N - (3 X VREF _N ). In the configuration illustrated in Fig. 5, the negative bias voltage is VIN _N — (4 X VREF _N ) . Neglecting inter-stage leakage currents and the output load current, the negative Dickson charge pump 130 produces a negative bias voltage of:

VBIAS _N = VIN _N - (n X VREF _N ); where n indicates the number of negative Dickson stages in the negative Dickson charge pump 130. [0034] In some embodiments, the diodes in the positive and negative Dickson charge pumps 100, 130 are replaced with pairs of complementary metal-oxide semiconductor (CMOS) devices configured as a voltage doubler. Fig. 6 illustrates a positive voltage doubler 160 (or positive MOS stage). The positive voltage doubler 160 includes, among other components, NMOS transistors 165 and 170, and PMOS transistors 175 and 180. The NMOS transistors 165 and 170 turn on after a rising edge of a CLK signal to either node A or node B due to the low impedance at their source terminal. Similarly, the PMOS transistors 175 and 180 turn on after a falling edge to node A or node B. At any given time, either the NMOS transistors 165 and 170 are turned on or the PMOS transistors 175 and 180 are turned on. After a falling edge of the CLK signal, NMOS transistor 165 is turned on and node B will charge to the positive input voltage (VINp). When the clock switches and a rising edge of the CLK signal occurs, the voltage at node B will increase to VI N _P + VREF _P and will be transferred to the positive output (VOUTp) through PMOS transistor 175. The same operation occurs on the other side during the other half of the clock cycle.

[0035] Fig. 7 illustrates a positive MOS charge pump 185. The positive MOS charge pump 185 includes, among other components, a series of positive voltage doublers 160 (or positive MOS stages). The positive voltage doublers 160 are coupled in a series configuration to produce the positive bias voltage. Neglecting inter-stage leakage currents and the output load current, the positive MOS charge pump 185 produces a positive bias voltage of:

VBIASp = VINp - (n X VREFp); where n indicates the number of positive MOS stages 160 in the positive MOS charge pump 185.

[0036] Fig. 8 illustrates a negative voltage doubler 190 (or negative MOS stage). The negative voltage doubler 190 includes, among other components, NMOS transistors 195 and 200, and PMOS transistors 205 and 210. The PMOS transistors 205 and 210 turn on after a falling edge of a CLK signal to either node A or node B due to the low impedance at their source terminal. Similarly, the NMOS transistors 195 and 200 turn on after a rising edge of the CLK signal to node A or node B. At any given time either the PMOS transistors 205 and 210 are turned on or the NMOS transistors 195 and 200 are turned on. After a rising edge of the CLK signal, PMOS transistor 205 is turned on and node B will charge to the negative input voltage (VINN). When the clock switches and a falling edge of the CLK signal occurs, the voltage at node B will change to V7N _W — VREF _N and will be transferred to the output through NMOS transistor 195. The same operation occurs on the other side during the other half of the clock cycle.

[0037] Fig. 9 illustrates negative MOS charge pump 215. The negative MOS charge pump 215 includes, among other components, a series of negative voltage doublers 190 (or negative MOS stages). The negative voltage doublers 190 are coupled in a series configuration to produce the negative bias voltage. Neglecting inter-stage leakage currents and the output load current, the negative MOS charge pump 215 produces a negative bias voltage of:

VBIAS _N = VIN _N - (n X VREF _N ); where n indicates the number of negative MOS stages 190 in the negative MOS charge pump 215.

[0038] Both Dickson charge pumps and MOS charge pumps operate on the same principles of charging one plate of a capacitor while the other plate is held to voltage of the reference node 67 during one clock phase. During the other phase, the charging capacitor is disconnected from a low impedance voltage source while the bottom plate of the capacitor is driven to a new reference voltage. The similarity in operation can also be seen in the similarity of the equations used to represent the positive and negative bias voltages (included above). Therefore, the Dickson and MOS charge pumps offer similar means of adjusting the bias voltage.

[0039] In some embodiments, the positive and negative bias voltages are adjusted by disabling a number of stages in the charge pump string. A sufficient number of stages are needed to achieve the largest desired bias voltage when all the stages are enabled. Smaller bias voltages are produced by either shorting stages out through a switch or not clocking certain stages. This provides a very coarse trimming resolution since n in the equations (included above) only include integer values. Fig. 10 illustrates an exemplary 4-stage positive Dickson charge pump 220 which can be converted to a 3 stage charge pump by shorting out a diode 225 (or positive Dickson stage). In other embodiments, the input to the second stage is switched to a new reference voltage or the reference node 67, as illustrated with the negative MOS charge pump 230 in Fig. 11. Furthermore, the clock signal to any given stage could be disabled by replacing the inverters with logic gates.

[0040] In some embodiments, the positive and negative bias voltages are adjusted by adjusting the positive and negative references voltages used to create the clock signal to each stage of the positive and negative charge pumps 50, 55. In some embodiments, the positive and negative reference voltages are derived from a power supply and temperature independent reference. Fig. 12 illustrates a circuit architecture 235 for generating the positive and negative reference voltages, according to one embodiment of the invention. A positive voltage regulator 240 generates the positive reference voltage and a negative voltage regulator 245 generates the negative reference voltage. The positive and negative reference voltages are generated based in part on a process, voltage, and temperature independent reference 250. Both the positive and negative reference voltages can be independently adjusted by adjusting (e.g., trimming) the value of either resistor RN or resistor RP. In other embodiments, other methods can be used to generate the positive and negative reference voltages for the positive and negative charge pumps. In some embodiments, the positive reference voltage is equal to the negative reference voltage.

[0041] In the presence of leakage currents, both the clock frequency and the size of the charge pump stage capacitor will affect the efficiency of the structure. In some embodiments, the positive bias voltage is adjusted by adjusting (e.g., trimming) a frequency of the CLK signal for the positive charge pump 50 and the negative bias voltage is adjusted by adjusting (e.g., trimming) a frequency of the CLK signal for the negative charge pump 55.

[0042] In some embodiments, the large capacitors in the positive and negative charge pumps 50, 55 are replaced by a bank of smaller capacitors to alter the efficiency of the positive and negative charge pumps 50, 55 by switching in or out the total number of smaller capacitors making up the large capacitor.

[0043] Thus, embodiments of the invention provides, among other things, systems and methods of independently adjusting positive and negative bias voltages for positive and negative sense-capacitors 15, 20 in a differential microphone 5. Various features and advantages of the invention are set forth in the following claims.