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Patent Searching and Data


Title:
INDUCTOR ARRAY CHIP AND DC-DC CONVERTER
Document Type and Number:
WIPO Patent Application WO/2013/157161
Kind Code:
A1
Abstract:
Provided is an inductor array chip that is not prone to structural defects during firing, and is easily manufactured in a stable manner. The inductance array chip (40) is provided with a magnetic layered laminate (41), and a plurality of inductors (L1, L2). The magnetic layered laminate (41) has a plurality of laminated magnetic layers (42). The plurality of inductors (L1, L2) is disposed inside the magnetic layered laminate (41). The inductance values of the plurality of inductors (L1, L2) differ from one another. Each of the plurality of inductors (L1, L2) has a plurality of coiled conductors (43a, 43b), and via-hole conductors (44a, 44b). Each of the plurality of coiled conductors (43a, 43b) is disposed between the magnetic layers (42). The via-hole conductors (44a, 44b) electrically connect the plurality of coiled conductors (43a, 43b). The plurality of inductors (L1, L2) includes a plurality of inductors in which the thickness of the plurality of coiled conductors (43a, 43b) differs.

Inventors:
KUBOTA YOSHIHIRO (JP)
NOMA TAKASHI (JP)
Application Number:
PCT/JP2012/079495
Publication Date:
October 24, 2013
Filing Date:
November 14, 2012
Export Citation:
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Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H01F17/00; H01F27/00; H02M3/155
Domestic Patent References:
WO2004019352A12004-03-04
Foreign References:
JP2000353619A2000-12-19
JPH0424911A1992-01-28
JP2007180435A2007-07-12
JP2006032425A2006-02-02
Attorney, Agent or Firm:
MIYAZAKI & METSUGI (JP)
Patent business corporation Miyazaki and table-of-contents patent firm (JP)
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