Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
INFORMATION PROCESSING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/029766
Kind Code:
A1
Abstract:
An information processing circuit has a calculation circuit that receives an input signal and a checking circuit that receives the input signal, wherein the calculation circuit outputs a numerical solution calculated on the basis of the input signal to the checking circuit, and the checking circuit restores the numerical solution received from the calculation circuit to a restored input signal, determines whether an error exists or not on the basis of the restored input signal restored and the received input signal, and outputs a determination result that shows existence/nonexistence of the error, with the result that it is possible to perform error detection with less circuit amount as compared to the case of doubling the circuit.

Inventors:
MOTOYA TORU (JP)
KANNO YUSUKE (JP)
YAMAOKA MASANAO (JP)
SAEN MAKOTO (JP)
Application Number:
PCT/JP2015/073429
Publication Date:
February 23, 2017
Filing Date:
August 20, 2015
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
HITACHI LTD (JP)
International Classes:
G06F11/16; G06F17/12
Foreign References:
JP2009266230A2009-11-12
JPH0520348A1993-01-29
JPH0981610A1997-03-28
JP2012521591A2012-09-13
Other References:
TAKAO SAKURAI ET AL.: "Development and Evaluation of Sparse Matrix Solver with Numerical Policy Interface", INFORMATION PROCESSING SOCIETY OF JAPAN SYMPOSIUM, HIGH PERFORMANCE COMPUTING TO KEISAN KAGAKU SYMPOSIUM (HPCS, 19 January 2011 (2011-01-19), pages 109 - 117
HIROSHI HIRAYAMA: "Double-double Type Quadruple Precision Arithmetic Library for C++ Languages and its Application", IPSJ SIG NOTES, HIGH PERFORMANCE COMPUTING (HPC), 2014-HPC-143, 24 February 2014 (2014-02-24), pages 1 - 7
Attorney, Agent or Firm:
TSUTSUI & ASSOCIATES (JP)
Download PDF: