Title:
INFORMATION PROCESSING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2021/161496
Kind Code:
A1
Abstract:
An information processing circuit 80 including a first information processing circuit 81 for executing layer computation in deep learning, a second information processing circuit 82 for executing layer computation in deep learning on input data through use of a programmable accelerator, and a merge circuit 83 for merging the computation result of the first information processing circuit 81 and the computation result of the second information processing circuit 82 and outputting a merge result. The first information processing circuit 81 includes a parameter value output circuit 811 in which deep learning parameters are built into circuitry, and a product-sum circuit 812 for performing product-sum computation using the input data and parameter values.
Inventors:
TAKAHASHI KATSUHIKO (JP)
TAKENAKA TAKASHI (JP)
TAKENAKA TAKASHI (JP)
Application Number:
PCT/JP2020/005733
Publication Date:
August 19, 2021
Filing Date:
February 14, 2020
Export Citation:
Assignee:
NEC CORP (JP)
International Classes:
G06N3/063
Other References:
ALHAMALI ABDULRAHMAN; SALHA NIBAL; MORCEL RAGHID; EZZEDDINE MAZEN; HAMDAN OMAR; AKKARY HAITHAM; HAJJ HAZEM: "FPGA-Accelerated Hadoop Cluster for Deep Learning Computations", 2015 IEEE INTERNATIONAL CONFERENCE ON DATA MINING WORKSHOP (ICDMW), IEEE, 14 November 2015 (2015-11-14), pages 565 - 574, XP032859264, DOI: 10.1109/ICDMW.2015.148
Attorney, Agent or Firm:
IWAKABE Fuyuki et al. (JP)
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