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Patent Searching and Data


Title:
INFORMATION PROCESSING DEVICE, DATA CACHE DEVICE, INFORMATION PROCESSING METHOD, AND DATA CACHING METHOD
Document Type and Number:
WIPO Patent Application WO/2015/064048
Kind Code:
A1
Abstract:
Provided is an information processing device capable of handling large volumes of data at high speed. The information processing device is characterized by: comprising a data cache device having a cache memory therein and a management device having a large-capacity memory therein that has a larger capacity than the cache memory; the data cache device comprising a data cache control means that performs control such that data having prescribed conditions and stored in the cache memory is arranged in the large-capacity memory when a read request or a write request is received from outside the information processing device; and, if the received request is a write request, the data cache control means writing data to be written, into the cache memory in accordance with the write request and, if the received request is a read request, writes data read in accordance with the read request into the cache memory.

Inventors:
INOUE HIROAKI (JP)
TAKENAKA TAKASHI (JP)
Application Number:
PCT/JP2014/005311
Publication Date:
May 07, 2015
Filing Date:
October 20, 2014
Export Citation:
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Assignee:
NEC CORP (JP)
International Classes:
G06F12/00; G06F12/08; G06F12/0813; G06F12/0866
Foreign References:
JP2013164660A2013-08-22
JP2003173294A2003-06-20
Other References:
SAI RAHUL CHALAMALASETTI ET AL.: "An FPGA Memcached Appliance, FPGA", 13 PROCEEDINGS OF THE ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD PROGRAMMABLE GATE ARRAYS, February 2013 (2013-02-01), pages 245 - 254
KEVIN LIM ET AL.: "Thin servers with smart pipes: designing SoC accelerators for memcached", ISCA '13 PROCEEDINGS OF THE 40TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, June 2013 (2013-06-01), pages 36 - 47
Attorney, Agent or Firm:
SHIMOSAKA, NAOKI (JP)
Naoki Shimosaka (JP)
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