Title:
INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM
Document Type and Number:
WIPO Patent Application WO/2018/066073
Kind Code:
A1
Abstract:
An architecture candidate generation unit that: specifies, for each of a plurality of function modules extracted from program code, either a processor or a hardware device other than a processor, as a device to implement each function module; and generates, as architecture candidates, a plurality of computer architecture candidates that implement the plurality of functions and each have different device combinations. An architecture candidate selection unit selects an architecture candidate having required attributes required by the computer architecture, from among the plurality of architecture candidates generated by the architecture candidate generation unit.
Inventors:
MURANO KOKI (JP)
MINEGISHI NORIYUKI (JP)
YAMAMOTO RYO (JP)
MINEGISHI NORIYUKI (JP)
YAMAMOTO RYO (JP)
Application Number:
PCT/JP2016/079512
Publication Date:
April 12, 2018
Filing Date:
October 04, 2016
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
G06F17/50
Other References:
YOHEI KOJIMA ET AL.: "A hardware/software partitioning system with design navigation for system LSIs design", IEICE TECHNICAL REPORT, vol. 105, no. 644, 2 March 2006 (2006-03-02), pages 19 - 24
YOSHINORI JODAI ET AL.: "A Hardware/Software Partitioning Method for Process-level System Specification in VHDL", IEICE TECHNICAL REPORT, vol. 98, no. 449, 11 December 1998 (1998-12-11), pages 63 - 70
YOSHINORI JODAI ET AL.: "A Hardware/Software Partitioning Method for Process-level System Specification in VHDL", IEICE TECHNICAL REPORT, vol. 98, no. 449, 11 December 1998 (1998-12-11), pages 63 - 70
Attorney, Agent or Firm:
MIZOI, Shoji et al. (JP)
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