Title:
INFORMATION PROCESSING DEVICE, PARALLEL COMPUTER SYSTEM, AND COMPUTATION PROCESSING DEVICE CONTROL METHOD
Document Type and Number:
WIPO Patent Application WO/2012/137339
Kind Code:
A1
Abstract:
An information processing device (2) which configures a parallel computer system (1) comprises: a memory (6) which retains data; and a processor (3), further comprising a memory cache (5) which retains a portion of the data which is retained in the memory (6), and a processor core (4) which carries out a computation using the data which is retained in either the memory (6) or the memory cache (5). Additionally, the information processing device (2) further comprises a communication device (10) which assesses whether data which is received from another information processing device (2a) is data which the processor core (4) is waiting for, and if the received data is assessed to be the data which the processor core (4) is waiting for, stores the received data in the memory cache (5). Note that if the communication device (10) assesses that the received data is not data which the processor core (4) is waiting for, the communication device (10) stores the received data in the memory (6).
More Like This:
| JP3257824 | CACHE MEMORY DEVICE |
| JP2001043204 | CACHE MEMORY CONTROLLER |
| JP4790283 | Storage subsystem and storage system |
Inventors:
AJIMA YUICHIRO (JP)
INOUE TOMOHIRO (JP)
HIRAMOTO SHINYA (JP)
INOUE TOMOHIRO (JP)
HIRAMOTO SHINYA (JP)
Application Number:
PCT/JP2011/058832
Publication Date:
October 11, 2012
Filing Date:
April 07, 2011
Export Citation:
Assignee:
FUJITSU LTD (JP)
AJIMA YUICHIRO (JP)
INOUE TOMOHIRO (JP)
HIRAMOTO SHINYA (JP)
AJIMA YUICHIRO (JP)
INOUE TOMOHIRO (JP)
HIRAMOTO SHINYA (JP)
International Classes:
G06F12/08; G06F12/0802; G06F12/0813; G06F12/0815; G06F12/0817; G06F12/0888; G06F15/17; G06F12/084
Domestic Patent References:
| WO2007110898A1 | 2007-10-04 |
Foreign References:
| JP2002278834A | 2002-09-27 | |||
| JP2002185470A | 2002-06-28 | |||
| JPH06314239A | 1994-11-08 | |||
| JPH1139214A | 1999-02-12 |
Other References:
See also references of EP 2696289A4
RAM HUGGAHALLI; RAVI IYER; SCOTT TETRICK: "Direct Cache Access for High Bandwidth Network I/O", ISCA '05 PROCEEDINGS OF THE 32ND ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
RAM HUGGAHALLI; RAVI IYER; SCOTT TETRICK: "Direct Cache Access for High Bandwidth Network I/O", ISCA '05 PROCEEDINGS OF THE 32ND ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
Attorney, Agent or Firm:
SAKAI, HIROAKI (JP)
Hiroaki Sakai (JP)
Hiroaki Sakai (JP)
Download PDF:
Claims: