This application claims the benefit under 35 U.S.C. 1 19(e) of Provisional

Application Ser. No. 62/798,646, filed January 30, 201 , entitled“Initialization Method for Precision Phase Adder,” the entire contents of which are incorporated herein by- reference .

TECHNICAL FIELD

Embodiments generally relate to ethods for initializing and/or calibrating a phase adder circuit,

BACKGROUND

A general method for the distribution of phase coherent signals over long electrical distances is described in a patent by Mthai Ban» and Vladimir Prodanov “Method and System for Multi-point Signal Generation with Phase Synchronize Local Carriers” US Patent No 8,553,826, published October 8 , 2013, die disclosure of which is incorporated herein by reference in its entirety. One applicat ion of thi s method is the distribution of a local oscillator (LO) signal in the acti ve arrays as described In in a patent by Mihai Banu, Yiping Feng, and Vladimir Prodanov“Low Cost, Active Antenna Arrays” US Paten 8,611,959, published December 17, 2013, the disclosure of which is incorporated herein by reference in its entirety. Another application is high-speed clock distribution in very large silicon chips.

The method of US Patent 8,553,826 uses two tree distribution networks and a plurality of circuits called“S-Clients y which detect a fixed global network parameter called Synchronization flight time”. Based on this parameter, the S-Clients generate signals, which are substantially phase coherent (practically identical phases). The quality of these S-Clients is critical for the precision of the entire system. In other words, in order to have small phase errors between the signals generated by the S-Clienis, the latter must operate close to ideal S-Clieots. When sinusoidal signal (single tones) are used, the generation of the phase coherent signals reduces to the simple operation of adding the phases of two signals propagating on the branches of the dual tree distribution networks.

Therefore, phase adders form a class of simple S-CSiesit circuits.

Conceptually, in terms of phase processing, a phase adding circuit is equivalent to an ideal single-side-band analog multiplier. A single-side-hand analog multiplier accepts two tones at its two inputs and generates a single tone at its output . The phase of the outpu t tone is the sum of the phases of the inpu t tones. This is the result of simple trigonometry: the multiplication of two sinusoidal signals equals the sum of two terms; one with added phases and one with subtracted phases. Each term represents a single- side-hand analog multiplier and tire sums of both terms represent a double-side-band analog multiplier. in prac tice, the realization of a single-side-hand analog multiplier with ideal or close to ideal characteristics is difficult, especially if the input signals are at high frequencies. First, non-linear effects usually present in practice (enhanced at high frequencies), generate undesired spurious signals producing output phase errors. Second, all practical analog multipliers are double-side-band analog multipliers and removing one sid band is prone to introducing additional output phase errors. Therefore, the application of the technique in US Patent 8,553,826 with sinusoidal signals is limi ted by the quality of phase adders that: can be realize in practice.

SUMMARY

Phased arrays consist of a plurality of antennas distributed over a surface area.

Tire plurality of antennas functions as a cohesive unit to send or receive a plurality of communication channels to different specific regions of space. Each of the antennas contributes a small portion of these communication channels. The coordination of transmitting or receiving sign als over the surface area of the phased array requires a uniform timing reference. Pro viding a uniform timing r eference over a surface area that has X and Y dimensions of typically many wavelengths of a carrier frequency of the communication channels is required . Phase adder cir cuits couple to the network of the tree distribution signals of US Patent No. 8,553,826 provide this uniform riming reference by generating a reference product component for each of the plurality of antennas.

A phased army comprises a plurality of phase adder circuits coupled into the network of the tree distribution signal, where the network lias fixed global network parameter called ^{^} synchronization flight time” that is constant extending over the X and Y dimensions of the area of the phased array. Each instance of any of the plurality of phase adders that couples to the network and that uses this global network parameter generates a reference product componen that has substantially the same phase and frequency as the copies of the reference product component generated by all remaining phase adders coupled to the network within the phased array The plurality of reference product components generated by the phase adders provides a uniform timing reference for each of the antennas of t e phased array.

In general, in one aspect, the invention features a method for initializing a phase adder circuit for use with a signal distribution network having a first line carrying a first signal of a frequency fb and a second line carrying a second signal of the frequency f„.

The phase adder includes a multiplier circuit with a first input electrically connected to the first line of the distributio network and a second input electrically connected to the Second line of the distribution network, a mixer circui t electrically connected to the multiplier circuit, an amplifie circuit, a low pass loop filter, and a voltage controlled oscillator (VCO) with an input and an output. The method includes: during a first phase of operation, determining a reference voltage which when applied to the input of the VCO causes the VCO to produce at its output a signal having a frequency of nil·, where a is a positive integer; during a second phase of operation, supplying a signal of frequency nil , to a firs input of the mixer; supplying a signal of frequency (nfo+Af) to a second input of tire mixer, wherein n is an integer greater than zero, and Af is a frequency that \s smaller than i and determining an adjustment signal which when applied to the amplifier circu t ani es the amplifier circuit to output a signal having DC component equal to the reference voltage; and during a third pha se of operation, forming a primary phase locked loo (PLL) circuit including the mixer, the amplifier circuit, the low pass loop filter and the VCO; an applying the adjustment signal to foe amplifier circuit. Oilier embodiments include one or more of d e following features. Determining the reference voltage during the first phase of operation involves forming an initialization PLL circuit including the VCG, tile loop filter, and a phase detector having a first input, a second input, and an output, with the first input of the phase detector electrically connected to the first line of the signal distribution network, the second input of the phase detector electrically connected to the output of the VCO, and the output of the phase detector electricall connected to an input of the to pass loop filter. Supplying the signal of frequency (nf«+Af to the second input of the mixer during the second phase of operation involves: electrically disconnecting the input of the loop filter from the output of the phase detector; and electrically connecting the input of the loop filter to a signal source providing a frequency selection signal that causes the VCO to output a signal of frequency (h£ _> ·Dί). Determining the adjustment: signal during the secon p ase of operation involves incrementally adjusting a bias level that is supplied to the amplifier circuit until a target value is found at which die amplifier circuit outputs the signal having a DC component substantially equal to the reference voltage, wherein the target value is the adjustment signal. The amplifier circuit has an input node an wherein tire bias level that is supplied to the amplifier circuit is a bias current that is supplied to the input node of the amplifier circuit Forming the primary phase locked loop (PLL) circuit during the third phase of operation involves: electrically disconnecting the input of the loop filter from the signal source providing the frequency selection signal; and electrically connecting the input of the loop filter to the output of the amplifier circuit. The number o is equal to 2 The quantity Af is much smaller than ik The method also involves;

implementing the multiplier circuit as a double balanced triode interface; implementing the mixer circuit as a double balanced Gilbert mixer; and implementing the amplifier circuit as a folded caseode amplifier. The first and second signals are sinusoidal signals Tire signal of frequency nfr that is supplied to a first : input of the mixer during the second phase of operation is a sinusoidal signal and the signal of frequency (o£ _> -f ) that is supplied to the second input of the mixer during the second phase of operation is a sinusoidal signal. The signal that is produced at the output of the VCO daring the first phase of operation is a sinusoidal signal having a frequency of Mo BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a distribution network with coheren output signals as described in US Patent 8,553,826.

FIG, 2 depicts a block diagram of a phase adder used as an S-CIient for the network in FIG. 1.

FIG, 3A depicts a conventional analog multiplier multiplying two tones each having a different frequency and a description of the intet odulaiian products produced by the non-linear operation of the analog multiplier,

FIG. 3B depicts a conventional analog multiplier multiplying two tones each having the same frequency and a descr iption of the mtermodutetion products produced b die non-linear operation of the analog multiplier

FlG. 4A depicts the I- V curves for a MOS transistor highlighting the transfer curves in the triocle and saturation regions.

FIG 4B depicts an embodiment of an MOS device configured to operate in the triode region

FIG 4€ depicts an embodiment of an MOS device configured to operate as a multiplier while operated in the triode region.

FIG. 4D depicts an embodiment of a circuit block representation of the triode transistor in FIG 4C.

FIG. 4B depicts an embodiment of an ideal multiplier multiplying two tones each having the same frequency and a description of the Mtermodulation products produced by the operation of the triode multiplier.

FIG. 5 depicts an embodiment of a circuit diagram of a differential triode multiplier formed with bipolar j unction transistors (BIT) and a passive load along with the intermodulation products. FIG. 6 depicts a» embodiment of a circuit diagram of a differential triode multiplier formed with MOS transistors and passive load along with the

iotennodu! ation products.

FIG. 7 depicts an embodiment of block diagram of a differential triode multiplier.

FIG. 8A depicts an embodiment of a block diagram of a differential triode multiplier configured to eliminate the leakage component.

FIG. SB depicts the elimination of the leakage component of the intermodulation products of FIG. 8A.

FIG . 9 depicts an embodiment of a circuit diagram a differential triode multiplier configured to eliminate the l eakage component of the mtermodulation product s

FIG. iOA depicts an embodiment of a block diagram a differential triode multiplier configured to eliminate th leakage component and DC component of the iutermodulatioa products.

FIG 10B depicts only the reference product component of the intermodulation products remaining at the output of FiG. I0A.

FIG. 11 depicts an embodiment of a circuit diagram of a differential triode multiplier configured to eliminate the leakage component and DC component of the intennodulation products

FIG. 12 depicts an embodiment of a block diagram of a differential triode multiplier configured to eliminate the leakage component of the imermodulation products and adjust the DC level of the differential outputs.

FIG. 13 depicts an embodiment of a circuit diagram of a triode multiplier formed with MOS transistors using two triode interfaces, a passive load, and AC coupling configured to eliminate the leakage component and adjust the DC level of the differential outputs. FIG. .14 depicts an embodiment of a block diagram of another differential triode multiplier configured to eliminate the leakage componen t of th Irrtermodulatioo products and adjust the DC· level of the differential outputs.

FIG. 15 depicts a embodiment of a circuit diagram of FIG. 14 formed with MOS transistors configured to eliminate the leakage component and adjust the DC level of the differential outputs.

FIG. 16 depicts another embodiment of a circuit diagram of FIG. 14 formed withMOS transistors configured to eliminate the leakage component and adjust the DC level of the differential outputs.

FIG. 1? depicts a embodiment of a block diagram of two triode interfaces coupled to a folded cascode configured to eliminate the leakage component of the differential outputs.

FIG. 18 depicts an embodimen t of a ci rcuit diagram of t he folded cascode configured to eliminate the leakage component of the differential output.

FIG. 19 depicts an embodiment of a diagra of the folded cascode and feedback configured to eliminate the leakage component and adjust the DC level of the differential output.

FIG. 20 depicts another embodiment of a diagram of the folded cascode and feedback configured to eliminate the leakage component and adjust the DC level of the differential output.

FIG. 21 depicts an embodiment of a circuit diagram of a differential triode multiplier in a differential triode multiplier formed with BJTs where an active load eliminates the DC component and the l eakage componen t of the mtermodalation products.

FIG. 22 depicts an embodiment of a circuit diagram of a differential triode multiplier in a differential triode multiplier formed with MOS transistors where an active load eliminates the DC component and the leakage component of the mtermodulatlon products.

FIG. 23 depicts an embodiment of a triode multiplier multiplying two equal tones with the resultant tone at twice the frequency mixed in a mixer with a second tone having twice the frequency along with each respective frequency spectrum.

FIG . 24A depicts the mixer of FIG 23 used in forming a phase locked loop (PLL) to eliminate all higher order frequency components.

FIG. 24B depicts the mixer of FIG. 23 used hi formin a phase locked loo (PLL) with a buffer to eliminate all higher order frequenc components.

FIG. 25 depicts an embodiment of an equivalent eircuit/bloek model representing foe multiplier and mixer of FIG. 23.

FIG. 26 depicts an embodiment of an equivalent eircui /bloek model using an amplifier representing the multiplier and PLL of FIG. 24A.

FIG. 27 depicts an embodiment of an equivalent eircuit/bloek model using a folded cascode representing the multiplier and PLL of FIG. 24A

FIG 28 depicts an embodiment of an equivalent eircuit/bloek model using a folded cascode representing the multiplier and PLL which includes the buffer of FIG. 24B

FIG. 29 depicts an embodiment of an equivalent eircuit/bloek model for low voltage operation using a folded cascode representing the multiplier and PLL which includes the buffer of FIG. 24B

FIG. 30A depicts a first s witch configuration to prepare the generation of the bop voltage for a PLL including the voltage controlled oscillator (VCO) operating at 2i¾.

FIG. 30B depicts a second switch configuration to apply the determined loop voltage to a PLL within the multiplier circuit. FIG. 30C depicts a third switch position for configuring the phase adder circuit

FIG. 31 A depicts a first switch configuration to prepare the generation of the loop voltage for a PLL including the voltage controlled oscillator (VCO) operating at 4fi>.

FIG, 31B depicts a second switch configuration for FIG, 31A to apply the determined loop voltage to a PLL within the multiplier circuit.

FIG. 31 C depicts a third switch position for configuring the phase adder circuit.

FIG. 32 depicts one embodiment of the feedback loop of FIG. 30 and FIG. 1.

FIG. 33 depicts another embodiment of die feedback loop of FIG. 30 and FIG. 31.

FIG. 34 depicts a flowchart of another embodiment of adjusting die loop voltage of FIG. 30 and FIG. 31.

In the preceding figures, like elements and like components may be identified with like reference numbers.

The details of one or more embodimen ts of the Invention are set forth in die accompanying drawings and the description below. Other features, objects, and advantages of die invention wilt be apparent from the description and drawings, and from the claims.

DETAILED DESCRIPTION

Use of Phase Adders for Coherent Distribution of Signals

FIG. I shows an embodiment of the signal distributio concept described in US Patent 8,553,826. The generator 1-1 excites two tree distribution networks (DTNs): distribution network 1-2 and distributio network 1-3. The two tree distribution networks are constructed such that at every place where S-G tents 1-4 sit, the stun of the signal travel times from the generator to each S-Chent through both tree networks is a network constant called synchronization flight time. The S -Clients detect the synchronization flight time and generate globally phase coherent signals whose phases are functions of the synchronization flight time.

In the case where the signals generated by genera tor I -I in FIG I are non- modulated earners (periodic signals), the S-Clients need only add the phases of the local signals detected from the two tree distribution networks to generate globally coherent signals, F IG. 2 shows an implementation of the S-Qient circuit. The phase adder 2-3 adds the phases of the si gnals traveling on the branch 2- 3 of the first distribution tree and on the branch 2-2 of the second distribution tree. The phase of the output signal2-4 is a constant corresponding to the constant synchronization flight time of the network.

The implementation of the phase adder 2-3 in F.IG. 2 is conceptually simple if the signals traveling on the two tree networks are single tones (sinusoidal). In this case, the phase adder can be a single-side-band analog multiplier.

Phase Errors in Conventional High Frequency Analog Multipliers

Active devices, such as transistors and diodes, are non-linear devices.

Conventional analog multipliers that use these non-linear devices generate

mtennoduladon distortion when a first input signal multiplies a second input signal. The intermodulation distortion generates higher order harmonics of each of these two input signals, sums and differences between the frequencies of these input signals, and integer multiples of sums and differences between the frequencies of the two input signals. An analog multiplier typically generates the product component, which corresponds to the sum of the frequency of the two input signals. Fi ltering techniques attempt the removal all of the remaining components. However, filtering may not be able to eliminate all of die components. Some of the integer multiples of sums and differences between the two input frequencies can have a resultant frequency that is very near to the desired product component, or worst, overlaps the desired product component These components of the intermodnlation distortion generated by conventional analog multipliers introduce phase errors in the desired product component.

The intermodnlation components that overlap or are very near tire product component are spurs and degrade the quality of the product component. A filter may remove some of these ifflermodulation components near tire product component.

However, the filter may need a v ry' shar response requiring the need for a high order Slier, which tends to be very cosily . Secondly, these filters introduce their own phase error. The intermodulation components drat overlap the desired product component are not removable and introduce phase error into the desired product component Therefore, an analog multiplier with improved linear characteristics that reduces o eliminates foe intermodulation distortion forming spurs would be very desirable.

Another type of multiplier is the single side band multiplier. The single side hand multiplier uses image rejection to remove foe intermodulation product of the difference between the frequencies of the two input signals. The first input signal is phase shifted 90° and coupled to a first analog multiplier. The second input signal couples to the first analog multiplier. These two signals multipl one another and the resultant product of the first analog multiplier comprising the upper and lower sidebands couples to a summing unit Then, foe first input signal couples to the second analog multiplier. The second signal is phase shifted 90° an coupled to the second analog multiplier. These two signals multiply one another and t he resul tant product of the second anal og multiplier comprising the upper and lower sidebands couples to the summing unit. In an ideal situation, the summin uni t combines these components together; the lower sidebands are 180° out of phase canceling each other out, while foe upper sideband components are in phase, and add together providing the result However, the input signals have a finite bandwidth and the phase shift devices have transfer curves over the finite bandwidth that is a functio of frequency. Over this finite bandwidth, it is difficult to match the behavior of the single sideband circuit over this finite bandwidth. This introduces phase error in foe multiplied signal Products

FIG, 3A illustrates a conventional analog multiplier 3-1 that mixes two frequency tones of f _j and f ₂ to produce a resulting signal at the output node 3-2. Typically, con ventional analog multipliers operate in the nonlinear region. The biasing of these devices in these analog multipliers cause the multiplication of these two frequency tones to generate a desired component along with a number of intermoduiation products. One of the multiplication components is die frequ ncy tone (/* + / ₂ ) that is a snnnnation of the two input frequency tones. The other multip1 teat ion component is the frequency tone (/, ~ / _¾ ) that is a difference of the two input frequency tones . hi addition to these components, there are a number of frequency tones generated at the output of the analog multiplier. These frequency tones include a sum and difference between the higher order harmonics of the two input freq uency tones as indicated by EQU. 1. Due to the nonlinearity of the analog multiplier, the signal at the output node 3~2 contains frequency tone components that include these higher order terms of each frequency and summations or differences of various multiplicative factors between the two input: frequency tones a presented in EQU I The desired frequency tone (/ _; 4- f ₂ ) is accompanied components that are undesirable and degrade the qualit of the desired frequency tone

FIG 3B illustrates the conventional analog multiplier 3-1 that mixes two equal frequency tones of f _Q and / ₀ to produce a resulting signal at the output node 3-3 As mentioned earlier, these analog multipliers operate in the nonlinear region and the multiplication of these two frequenc tones generates a desired component along with a number of intermodulation produc ts. The nonlinearity of the conventional analog multiplier is due to the operation of the de vices within the conventional analog multiplier operating in the nonlinear region. One of the desired multiplication components may be the frequency tone that is simply the summation of the two input frequency

tones (/o + /ø ~ 2 o ). Another resulted component is the difference between the two input frequency tones ( / ₀ ~/ ₀ = O), which in thi case has a DC voltage

of CQS(@I— @ ₂ ), where Q and $> are the phases of the two input frequency tones.

In addition to these components, there are many additional frequency tones generated on the output of the analog multiplier. These frequency tones include a number of different frequency tones that consists of the sum an difference of multiples of the frequency tone as indicated by EQU 2 Due to the nonlinearity of the analog multiplier, the signal at the output node 3-3 contains frequency tone components that include higher order terms of each of the input frequency tones and various other summations and differences of various multiplicative factors between die two input frequency tones as presented in EQU. 2,

The desired multiplication component is where M ^~ N ~ I or f _Q + / ₀ 2/0 and all remaining components generated by the conventional analog multiplier 3-1 are undesired. The PC voltage, f _Q —,/ ₀ ~ c ($ _t - f¾), generated by the analog multiplier is a function of phase of each of the equal frequency tones. Also, those intermodulation products where |M ~ Nj ^:::: 2, and P ^::: 2 are spurs and need to be reduced or eliminated since they have the same frequency as the desired 2f ₀ frequency term. Some of these spurs can be located 15 dB below the desired product component introducin as much as 10° of phase error. An analog multiplier that operates in a linear region can significantly minimize the generatio of these intermodulation products. Such an analog multiplier would be a desirable device particularly if it can eliminate or significantly reduce the amplitude of the intermodulation products and spurs.

MQS Transistor Characteristics In the Triode Region

An analog m ult iplier with linear characteristics ca reduce the magnitude of or eliminate some of the integer multiples of sums and differences between the two input frequency signals. This analog multiplier can significantly· reduce or eliminate the spurs al together. An analog multiplier with such a linear behavior would provide a purer or more ideal product component when the two input frequency signals multiply one another. One embodiment of a phase adder circuit presented in this specification when compared to conventional multipliers reduces the magnitude of the spurs from 15 dB down to 30 d.B and reduces the phase error from 10° to less than 1°, respectively.

FIG. 4 A illustrates the IV (current- voltage) characteristics 4-1 of an MQS transistor. Conventional analog multipliers typically operate MOS transistors in the saturation region 4-2 The non -linearity of the behavior of these MOS transistors operated in the saturation region is evident as indicated by the intermodulation products presented in EQU. 1 and EQU. 2. However, the triode region 4-3 offers transistors that can operate as practically linear devices. Transistors biased to operate in the triode region create analog multipliers that beha ve practically linearly. FIG. 4B illustrates an MOS device 4-4 configured to illustrate the operation of the MOS de vice In the triode region. Assume that the voltages VQ, VO, and Vs are constants and bias the transistor 4-4 to operate in the triode region.

Th current flowing in MOS device 4-4 is now a function of the two variable voltages V _D and V _s applied to the source and drain as indicated in EQU. 3, Note that if the gate voltage of the MOS transistor 4-4 is constant, the current through the device 4-4 can be represented to as: = f(V _D ) - f(Ys) (EQU. 3)

Each function in EQU. 3 can be further represented as a Taylor series expansion as indicated in EQU . 4. f(V) = a ₀ + _ai V + a ₂ V ² + a ₃ V ³ + a ₄ V ⁴ + ... (EQU. 4)

Substituting EQU. 4 into EQU. 3 provides:

Let the variable voltage applied to the source and drain terminals have a differential component where ( (¾ ~ !¾) and ( nd substituting these equivalent values into EQU. 5 simplifies to:

Note that all of the even terms in EQ . 6 cancel and go to zero. In addition, the third order od component is negligible since is approximately equal to zero.

Furthermore, all die highe order odd coefficients are significantly less than % and can be disregarded. By eliminating these terms and substituting — fe(l¾— IQ) where k is one of parameters defining the transistor, EQU. 6 becomes: 1 - zk(y _{& ~} v _r) v _t (EQU. 7)

Since V _c and V _† are assumed constant, the MOS device 4-4 behaves as a linear resistor in the triode region 4-3,

FIG. 4C introduces a second variable signal voltage V ₂ applied to tlie gate of OS transistor 4-4 as presented in EQU. 8;

VG = Vco + Vz (EQU. 8)

Substituting EQU 8 into EQU. 7 and simplifying provides the current thro ugh MOS device 4-4 as EQU 9 which consists of two parts: a reference product component and a leakage term.

/ = IkViVz + 2kV ₁ (V _G0 - V _T ) (EQU.9)

Tlie first terra is a reference product component of 2 A: 14 V ₂ representing the

rauhiplicatiot product. The second terra is the leakage terra 2&F ₁ (F _eo — V _T ) and represents the leakage component of the. MOS device 4-4,

FIG. 4D illustrates a circuit model representation of the MOS device 4-8 configured as an analog multiplier operating in the triode region. The multiplier 4-7 represents the reference product component of 2£K _j F ₂ corresponding to an ideal multiplication. The amplifier A has a magnitude of 2k(V _6Q ~ V _r ) and multiplies one of the inputs ¾ to form the leakage component. The summer 4-6 combines the two terms of the ideal reference product component and a leakage component.

The MOS device 4-4 as configured in FIG 4C is the triode transistor and exploits the linear properties of the MOS device to create an analog multiplier. The DC voltages VQ, VB _S and Vqo bias the operation of the transistor i the triode region. Differential signal voltages and couple to the source/drain terminals while a second signal voltage IQcouptes to the gate. The triode transistor generates the current described in EQU. 9 when the transistor is biased in the triode region. FIG. 4E Illustrates the reference product components mixing two equal frequency tones of tones / _& in a triode multiplier 4-7. FIG. 4E presents the collection of

intermodulation components at the output node 4-9. In the triode multiplier _» the transistor operates in the triode region 4-3 of FIG. 4A where the MOS devic exhibits linear behavior ^' The triode multiplier generates frequency tone that is simply the summation of tire two input frequency tones if a + fo = 2/ _{0 )} known as tire reference product component. Another resultant component is the difference between the two input frequency tones (/ ₀ — f ₀ ·= 0) known as fee DC component. The DC component has a DC voltage equal to here Q _t and B _z are the phases of he two input frequency tones. All of the even order higher harmonics components (see EQU. 6) are equal to zero, while the coefficients for the third and od higher order components are essentially zero. Therefore, all of the higher order components generated by fee triode multiplier 4-7 in FIG. 4E are essentially zero or negligible. Thus, in total, by referring to FIG. 4D and FIG. 4E, the triode transistor generates three components: the product component at 2fo, the leakage component at ft, and fee DC component. The claimed functionally of the triode transistor can be implemented with either an N-channel or a P- ehannd MOS transistor. Tire disclosed material is exemplary an should he construed as illustrating, not limiting, fee scope of fee claims.

Implementing the Triode Multiplier

FIG. 5 illustrates a BiCMOS differential triode multiplier comprising the triode transistor using an N~chanoel MOS transistor MS. Transistors Ml, M2 _» and M3 are H- ehannel MOS transistors, transistors M4 and Mb are P -channel MOS transistors and transistors Q3 and Q2 are bipolar junction transistors (BIT). The differential triode multiplier includes two circuit paths or legs between the power supplies of VDD and VSS. Transistor Mi couples VDD to the collector of Qr and transistor Ms couples VSS to the emitter of transistor Qj forming fee first leg of fee differential triode mnliiplfer.

Transistor Ms couples VDD to the collector of Qa and transistor Ms couples VSS to the emitter of transistor forming the second leg of fee differential triode multiplier.

Transistors Ms and Ms, located within the current source unit 5-9, are current sources that provide a current hi to the first leg and the second leg, respectively:. Transistors M and Ms, located within the differential load circuit 5-1, fon» a passive load for the first leg and second leg of the differential triode multiplier, respectively.

The triode transistor Ms couples die two legs of the differential amplifier at the emitters of transistor Qi and Qa. The node 5-5 coupled to the gate of Ms receives the signal voltage VT, while the source and drain of the triode transistor Mή recei ves the differential signal voltage ofVi via the nodes 5-3 and 5-4 coupled to the base junctions of the Qi an Qs bipolar junction transistors (BJT), respectively. The applied differential signal voltage of Vj at the bases of the BIT'S each experiences a VRB drop. Each of the differential signal voltages of Vj are down shifted by this voltage drop before being applied to the source and drain of the triode transistor Ms. The triode transistor Ms multiplies th signal voltage Vi times the“VBE shifted voltage Vi" hereinafter, unless specifically stated otherwise, referred as Vt. The transistor configuration of the three transistors, in this case Qi, Qs and M _¾ forms a Made interface 5-2. The transistor Qi and a interface the triode transistor to the differential triode multiplier. The triode interface represents the circuit Mock performing the multiplication and is between a loa 5-1 an a current source 5-9. The DC voltages VQ, VO, and VB bias the operation of the triode transistor in the triode region. Adjustment of these DC voltages also controls the gain of die overall circuit.

The multiplication of Vi times \½ causes a current I represented by EQU 9 to flow through the triode transistor M<$ as depicted in FIG, 5, Current I adds to the bias current few, rathe first leg of the differential triode multiplier while the same current I subtracts from the bias current Mas in the other leg of the differential triode multiplier. Each leg of the differential triode multiplier connects to a differential load circuit 5- 1 ,

The differential triode multiplier generates a differential output signal voltage V itr between legs 5-6 and 5-7 across the differential load circuit.

The current in the diode connected MGS transisior Mf adj usts the bias current b as. Transistors Ms and Ms in die current source unit 5-9 mirror the bias current Mas into die legs of the differential triode multiplier. A sealing of the physical dimensions of transistors Ms and Ms compared to the physical dimension of transistor Mi sets the Iwas current within each leg of the triode multiplier circuit. The current M adjusts the current Ibias. Typically, each leg of the differential triode multiplier has identical characteristics, for example, transistor Qj is identical tO Qa _* transistor M4 is identical Ms, etc.

The differential load circuit 5-1 uses a common mode voltage determined by the resistor divider Rj and Ra network between the two legs and applies this common mode voltage between the resistors to each gate of the P-eharmel devices, Mr and Ms, within the differential load circuit 5- 3 . This self-biasing of transistors Mi and Ms provides a stable load for the triode multiplier circuit..

An adjustment of the DC voltages of V¾ or \¾ varies the gain of the multiplier. Tile final biasing values of VQ or Vo after an adjustment should set the triode transistor Mr, in the triode region so that the transistor behaves as a triode multiplier.

The inputs of the c ircuit receive two signal vol tages, Vi and Vi (as illustrated in the top spectrum within 5-8), Both of these two signal voltages are operating at a frequency of fir The triode multiplier circui t generates an Output spectrum (shows in the lower spectrum of 5-8) of three components; the product component at 2f>, the leakage component at fi>, and the DC component. The product component at 2Fo provides the multiplication of the two frequency tone signals operating at fb at the inputs. The leakage component at fo and the DC componen t are undesirable hi t he outp ut spectrum o f the Mode multiplier circui when generating a desired product component. Circuit techniques described in the later sections remove the leakage component at f© and the DC component.

The triode transistor within the triode multiplier circuit eliminates the even order harmonies and minimizes the odd order harmonics when compared to conventional analo multipliers. Transistors operated in the triode region generate intennodulation terms having a tower magnitude or eliminate some of the terms altogether. This

advantageously allows the triode multiplier circuit to have a greater amplification over the conventional analog multiplier while still maintaining a lower noise floor than the conventional analog multiplier. The ode multiplier circuit provides a cleaner output signal while providing a larger magnitude signal at Y*?r. The difference in the effective

I S noise floor between the triode mul tiplier circuit and a conventional analog multiplier can be as much as 15 dB.

FIG. 6 illustrates a similar differential triode multiplier as that provided in FIG. 5 except MGS transistors M? and Ms replace the BIT transistors Qj and t¾, respectively. The transistors M _? and Ms shift the applied input signal voltage of Vi by the gate to source vol tage (Vos) of the transistors M? and Ms. The transistor configuration of the three transistors, in this case M?, Ms and e. have the same configuration as before and are still considered to form a triode interface 5-2 Those of skill in the art will understand that alternati ve configurations of the present disclosure of the triode interface can substitute the BJTs with MOS transistors (as illustrated) or any other comparable semiconductor device such as a field effect transistor (PET), Schottky transistor*

Darlington transistor, insulated gate bipolar transistor, junction fiel effect transistor, or the like. However, the triode transistor Ms should be a device that displays MOS characteristics.

The claimed ideal multiplicatio of the M-clmnnel MOS transistor M _<$ can be implemented by P-ehannel MOS device as a suitable alternative embodiment for the triode transistor. One embodiment of a circuit using the P-ehannel as a triode multiplier may require the remaining components of the triode interlace wi thin the triode multiplier circuit replaced with thei complimentary values.

Two equal frequency tone signals Vs and Vs, each at frequency fo as illustrated in the top spectrum within 5-8, are applied to the inputs of the circuit i FIG. 6. The triode multiplier generates an output spectrum (shown in the lower spectrum of 5-8) of three components: tire product component at 2i¾, the leakage component at tri and the DC component. The product component at 2fo provides the multiplication of the two frequency tones at fin The leakage component at fo and the DC component are undesirable in the triode multiplier. Various circuit technique embodiments remove these components as described in the latter sections

FIG. 7 illustrates a block diagram for both of the differential triode multiplier circuits illustrated in FIG. 5 and FIG. 6 The differential load circuit 5-1 couples the triode interface 5-2 to VDD. The current source unit 7-3 couples the triode interface 5-2 to YSS. The current source symbols 7- i and 7-2 each sourcing a current oflw» represents the current source transistors Mi and Ms within the c urrent source unit 5-9 of the multipliers shown in FIG. 5 and FIG. 6. These figures illustrate a common mode differential load circuit within 5-1. The choice of the stated common mode differential loa circuit does not rule out other suitable choices known to the art, as for example, loads comprising resistive or reactive components.

Nodes 5-3 and 5-4 form a differential input, with an AC signal of ÷ Vi applied to node 5-3 and an AC signal of—Vi applied to node 5-4, ie., an AC signal that is 180 ^s out of phase with the AC signal applied to «ode 5-3. Another AC signal -fVs is applied to node 5-5. The triode interface 5-2 multiplies the signal voltage of V at node 5-5 with the signal voltage ofYi applied to nodes 5-3 and 5-4, respectively. The leg 5-6 carries current (l¾ss + 1) while the leg 5-7 carries current (feus ·· 1). Reversing the polarity of the signal voltage ofV 5 applied to nodes 5-3 and 5-4 would cause the currents: flowing in the leg 5-6 to carry a current (h - 1} while the leg 5-7 would cany a current (li s + 1). A differential signal voltage Ym forms between the two legs 5-6 and 5-7 located between the differential load circuit and the triode interface. (Note: the two inputs represented by nodes 5-3 and 5-4 can also be referred to as a differential input of the multiplier circuit with first input tine represented by node 5-3 and a second input line represented by node 54.)

The differentia! triode multipliers of FIG. 5, FIG. 6, and FIG. 7 will be referred to as‘‘'single-balanced” in comparison to“double-balanced” differential triode multipliers to be discussed next.

Eliminating the Leakage Component

The triode interface 5-2 generates an output spectrum of three components: the product component at 2f¾, foe leakage component at if, and foe DC component. The product component at 2ft provides the multiplication of the two frequency tones at ft applied to foe inputs. The leakage component at ft and the DC component are undesirable in the triode multiplier circuit if the final desired result is a reference product component of 2fe. FIG. 8A illustrates a block diagram of a triode multiplier where an additional mode interface is added to the block diagram of FIG . ? to eliminate the leakage component at ft. The combination of the two triode interfaces 5~2a and 5-2b and the network interconnecting the legs of the two triode inter faces coupling to die load circuit as illustrated inside the dotted block forms the double-balanced triode interface 8-7.

Note that the double-balanced triode interface configuration means that the two triode interface circuits are interconnected such that their outputs are connected in parallel (le , node 5-6 connected to node 8-3 and node 5-7 connected to node 84) while the inputs are connected in a reversed fashion (Le., node 5~3 connected to node 5~4h and node 5 4a connected to node S 3 b). Also, node 5 5a of triode interface circui t 5 2a and node 5~5b of triode interface circuit 5~2b represent a differential input to the double balanced triode Interface, with the AC signal applied to node 5-5a being 180° out of phase from the AC signal applied to node 5~5b, i.e., -t-Va versus Ah.

The differential output voltage Vsur includes a first AC component on a first output node 8-1 _» a second AC component on a second output node 8-2, and a common mode DG voltage. The first AC component is substantially phase shifted 180° fro the second AC component. Both AC components include substantially the same DC voltage. Similarly, the differential input voltage Vi includes a first AC component on a first input node 5 -3a, a second AC component on a second output node S~4a, and a common mode DC voltage Vq. The first AC component is substantially phase shifted 180° from the second AC component. Both AC components contain substantially the same DC voltage VQ; Finally, the differential input voltage Yz includes a first AC component on a first input node 5-5a, a second AC component on a second input node 5-5b, and a common mode DC voltage Vo The first AC component is substantially phase shifted 180 ^® from the second AC component. Bot AC components contain substantially the same DC voltage Vo.

The triode interface 5-2a multiplies the positive signal voltage ofYz at. node 5-5a with bot the positive signal voltage of Vi applied to node 5-3a an the negative signal voltage of V t applie to node 5~4a. Using BQU, 9, the leg 5-6 is found to cany·' a current of 2k(U )(lA) -f 2!ί(¥ _l · )(n, _:;o — ty) while the leg 5-7 carries a current of 2 i (— ) (¾¾ ) + 2fc(-V _j )(V _eo - V _T ). The second mode interface S-2b multiplies, the negative signal voltage of Vs at node 5-5b with both the negative signal voltages of Vt applied to node $-3h and the positive signal voltage of Vt applied to nod 5~4b. The leg 8-3 carries a current of 2k(-V _t )—Vt) + 2 k(-Vi }{¾ ₀ - Fr) while the leg 8-4 carries a current of 2k(V ₁ )(~V ^' ) + 2 i(V _:t )(y _-0 — i'V)· The current in leg 5-6 combines with the current in leg 8-3 to form the current 4k(F _t )(V ₂ ) in leg 8-5. EQL\ 9 shows that the leakage component cancels while the product component doubles with a positive amplitude. The current in leg 5-7 combines with the current in leg 8-4 to for the current—4fe(Fi)(F ₂ ) in leg 8-6. EQU 9 shows that the leakage component cancels while foe product component doubles with a negative amplitude. In addition, the multiplication result of foe two single frequency tones at (fa - fe) causing a DC component is adde to each of the two outputs 8-1 and 8-2 of the circuit. The Viunoutput contains the desired peak-to-peak difference signal of 8kVi\¾ plus the same DC component applied to each output The DC component is a function of foe phase difference between V I and V2.

FIG. SB illustrates the input and output spectrum 8-3 of the circuit in FIG. SA. The _: input spectrum in foe top waveform shows overlapping frequency tones of fa applied to both inputs Vi and Vs. The lower wa veform illustrates the elimination of the leakage component at fo 8-4 while the DC component remains. When the double-balance differential triode multiplier of FIG 8.4 is used as phase adder for the network of FIG 1 , the DC component varies as the double-balanced differential triode multiplier couples from one location in the distribution tree network to another location in the distribution tree network. The variation of this DC component makes the extraction of the reference product component at 2f« more difficult, since the variation of the common mode voltage of the multiplication result can be large

FIG 9 presents one embodiment when the block diagram components of FIG. 8A are replace witli equivalent circuit schematics. The differential load circuit 5-1 uses a common mode voltage determined hy the resistor divider Ri and Ra network between the two legs and applies this common mode voltage between the resistors to each gate of the F-ehannel devices, M ₄ and Ms, within the differentia! load circuit The self-biasing of transistors M and Ms provides a stable load for the double-balanced differential triode multiplier circui

Both of the triode interfaces (5~2a and 5~2fa) use MOS transistors to form tire circuit configuration of the double-balanced triode interface. For example, the triode interface 5-2a include MOS transistors Mr, Ms and Ms _, while triode interface S-2b includes MOS transistors Mte, Mi 1 and M¾ The transistors M? and Ms shift the applied input signal voltage of V t to transistor Mis by the gate to source voltage Vos of the transistors M? and Mis. The transistors Mi< and Mu shift the applied input signal voltage: of Vs to transistor Ms by ie gate to source voltage Vos of the transistors Mio and Mu.

Eliminating the DC Component

FIG. 10A depicts one embodiment of eliminating the DC component generated by the double-balanced differential triode multiplier, which is a function of position of where the triode multiplier coupl es to the s ign als of the distribution tree network 2-1.

The triodemultiplier configuration of FIG. 10A generates an output spectrum that eliminates the leakage component at ft as discussed earlier. However; the DC component still accompanies the desired product component at 2i¾. One embodiment to remove the DC component is placing an AC coupled circuit 10-1 at the output nodes of the triode multiplier as illustrated in FIG. lOA. The high pass AC coupled circuit noves the DC component while allowing the desired product component at 2ft to pass to the two output nodes 10-2 and 10-3 providing the resultant signal Vdiff at nodes 10-2 and 10-3.

FIG . 10B illustrates the input and output -spectrum 10-4 for the circui t in FIG .

10A. The input spectrum in the top waveform shows the two overlapping frequency tones of to applied to Vi and Vs. The lower wa veform illustrates the elimination of the leakage component at ft 8-4 due to the double-balanced triode interface configuration as discussed earlier. The AC coupled circuit removes the DC component from the output as illustrated within the region 30-5 of the lower spec trum plot. The product component at 2ft is found at the output nodes 10-2 and 10-3 in FIG. 10A. FIG. 1 1 illustrates one embodiment of die AC coupled circuit using coupling capacitors Ci and Cz to block the DC component of cos(t¾— $>) on nodes 8-1 and 8-2. Capacitor Ci couples the AC component from node 8-1 to node 1 1 -2, Capacitor Ct couples the AC component from node 8-2 to node 11-3. Nodes 1 1-2 and 11 -3 recei ve the desired product component at 2f> The differential amplifier 11-1 amplifies the signals on nodes 12-2 and 1 1-3 and generates the resultant signal output at nodes 10-2 and 10-3. Each of the coupling capacitors Ci and Ci fabricated on a silicon substrate have an associated parasitic capac tor of Cs an Cr, respectively. The parasitic capacitor leak a portion of the coupled AC signal to the substrate. The coupling capacitor along with its associated parasitic capacitor forms a voltage divider and reduces the transfer of the desired product component at 2f to the differential amplifier 1 1-1, Thus, the efficiency of this capacitive coupling network depends on the ratio of the coupling capacitor to its corresponding parasitic capacitor, A coupling network wit a minima! parasitic

capacitance increases the efficiency of the transfer. The choice of the stated AC coupled ci rc uit of coupling capacitor does not rule out other suitable choices known to the art such as any other reactive component or combination of such components configured to transfer the AC components but block the DC component.

FIG . 12 illustrates a block diagram of a embodiment to compensate for the DC component due to the frequency difference component cos (ft _j — # ₂ )y which varies as a func tion of position with regard to where the tnode multiplier, one embodiment of the phase adder, couples to the signals of die distribution tree network instead of eliminating the DC component using coupling capacitors as presented in FIG. 1 1 , a feedback technique adjusts the DC component on each output node to maintain th DC component constant at a predetermined value of Vbm. For example, a feedback circuit made up of a differential amplifier 128-2, a low pass filter 12- la, and P-channel transistor Ml 2 Is connected to output 8-1. The differential amplifier 12-2a receives a reference vol tage Vwas and samples the signal at the output 8-1. The output of the differential amplifier is filtered with die low pass filter 12- 1 a and applied to the P-channel transistor ii.

Transistof Mis adjusts the voltage of the signal at the output node 8-1. This feedback loop maintains the DG component of the voltage of die output node at the fixed reference voltage Vbias. Similarly, a differential amplifier 12-2b receives the same reference voltage VM*, and samples the signal of the output node 8-2. The output of the differential amplifier is filtered with a low pass filter 12- lb and applied to the P-channel transistor Mss.

Transistor Mis couples die output node 8-2 to VDD. This feedback loop adjusts the voltage of the output nod 8~2 to Vws*. Each output node 8-1 and 8-2 has a DC

component set to a voltage of Y .

The output signal between nodes 8-1 and 8-2 contains the desired product component at 2fiv and this DC component. The DC component remains constant independent of where the triode multiplier, or this embodiment of the phase adder, couples info the signals of the distribution tree network. As the phase adder couples into different locations into the distribution tree network, the feedback loops adjusts the DC component to remai constant Independent of location. The feedback loop technique allows extraction of the desired product component at 2¾ since its associated DC component remains constant independent of where the triode multiplier couples to the network of the distribution signal

FIG. 13 replaces the block diagrams of FIG. 12 with circuit schematics that present one embodiment of using the feedback technique to adjust the DC component. The differential load circuit 5-1 is replace with another circuit embodiment that include a load element 13-1 coupled between current mirrors Mis an Muu A diode connected transistor MM provides a reference current Wand the generate voltage at node A is applie to current mirrors ss rand Mis. A load element 13-1, such as a resistoror a transistor configured as a resistance, couples the two output nodes 8-1 and 8-2.

A description of the feedback loop coupled to the node 8- 1 follows. A high gain differential amplifier 13 -2a couples to the output node 8-1 and the reference voltage ¾ _as . The output of die differential amplifier couples to a low pass filter formed by Ri? and Cs. A P-channel transistor Mr? connects the output node 8- 1 to VDD. The output of the low pass filter cou ples to the gate of transistor Mw and forms a feedback loop that adjusts the voltage on output 8-1 to V _* . If the voltage at node 8- 1 is above Vwas, the voltage at the output of the differential amplifier increases. The RC network passes this signal to the gate of Mi? causing a reduction in the conductivity of transistor Mi? This decreases the current in Mis and causes a drop in the voltage on node 8-1. The voltage on node 8-1 approaches that of the voltage V¾» _s . Similarly, if the voltage at node 8-1 is below Vbns, the voltage at the output of tire differential amplifier decreases. The RC network passes tliis signal to the gate of Mu causing a increase in the conductivity of transistor Mia. This increases the current in Mir and causes a rise in the voltage on node S- L The voltage on node 8-1 approaches that of the voltage V if the gain of the differential amplifier l3-2a is high. In practice, the voltage on node 8-1 matches the voltage .

Similarly, for the other output node 8-2, a high gain differential amplifier 13 -2b couples to the other output node 8-2 and the same reference voltage The output of the differential amplifier couples to a low pass filter formed by R.t and€¾. A P-channe! transistor Mi 3 connects tile output node 8-2 to VDD. The output of the tow pass filter couples to the gate of transistor MB an forms a second feedback loop that adjusts the voltage on output node 8-2 to Vs s until the voltage on node 8-2 matches the voltage Vbi .

The differentia! output signal V _< sfr formed between nodes 8-1 an 8-2 contains the desired product: component at 2fe and a DC component that is constant independent of where the Mode multiplier couples to the signals of the distribution tree network. The DC component remains constant due to the feedback loop independent of where the triode multiplier couples into the signals of die distribution tree network. The feature allows extraction of the desired product component at 2fo since its associated DC component remains constant independent of where the triode multiplier, or this embodiment of phase adder, couples to the network of the disMhution signal.

Fig, 14 illustrates anot her embodiment of a feedback technique to adjust the voltage of the DC component at the output nodes of the circuit. A high gain differential amplifier 14-la couples to die output socle 8-1 and the reference voltage of Vkas, The output of the differential amplifier is appl ied to a tow pass filter 14-2a. An N-channel transistor Mis is placed in parallel with the current source 7-1 a which provides current to one leg of the Mode interface 5-2a. A second N -channel transistor M i? is placed in parallel with current source 7~2a which pro vides current to another leg of the ode interface 5-2a. The low pass filter 14~2a drives the gates of transistors Mia and Mi?. The output of die low pass fil ter couples to the gate of transistor Mis and forms a first seif- feedback loop that adjusts the voltage on output 8-1.

Similarly, for th other output node 8-2, a high gain differential amplifier 14-3b couples to one of th output node 8-2 and the same reference voltage of Vt» _as . The output of the differential amplifier is applied to low pass filter 14~2I>. An N-channei transistor Mte is placed in parallel with the current source 7-2b while another and channel transistor Mis is placed in parallel with another current source 7-l b associated with triode interface 5~2b. The low pass filter 14- 2b drives the gates of transistors Mis and M The output of the low pass filter couples to the gate of transistor M»> and fbrtns a second self-feedback op that adjusts the voltage on output node 8-2.

The first and second feedback loops interact with one another via cross-feedback loops in the first feedback loop transistor Mn augments the current source 7-2 a that influences the second self-feedback loop controlling the voltage of the output node 8-2. Simultaneously, the second feedback loop transistor Mis augments the current source 7- 3 b that influences the first self-feedback loop controlling the output voltage 8-1. The self- feedback an cross-feedback loops eventually stabilize and maintain the output voltage and nodes 8-1 and 8-2 at a DC voltage of \ .

The output signal between nodes 8-1 and 8-2 contains the desired product:

component at 2.fo and a common DC voltage. ^' Hie common voltage o nodes 8-1 and 8-2 contain tire DC component pfV determined by the feedback loops. The DC voltage on nodes 8-1 and 8-2 is constant independent of where the triode multiplier, or this embodiment of the phase adder, couples into the signals of the distribution tree network. The desired product component at 23¾ can be extracted from the output signal between the nodes 8-1 and 8-2 when its DC component remains constant independent of position.

PIG, 15 replaces the block diagrams of the differential load circuit 5-1 of the differential amplifiers 14-1 , the tow pass filters 14-2, and the triode interfaces 5-2 with their corresponding circuit schematics.

FIG. 16 depicts an embodiment that eliminates the cross feedback loop described in FIG. 15, A high gain differential amplifier 15-la couples to one of the output nodes 8- 1 and a reference voltage of \¾½s. A low pass filter comprising Rs and C? couples the output of the differential amplifier to the gates of two N-channel transistors Mis and Mu. Transistor Mrs is placed in parallel with the current source 7~ia while transistor is placed in parallel with another current source 7- lb, Both transistors Mis and Mi¾ supplement currents to current sources ?~la and 7-1 b. Both of these current sources share a common output node 8-1 within the load. This first feedback loop adjusts the voltage on output 8-1 to match the voltage of \’ .

Similarly, for the other output node 8-2, a high gain differential amplifier 15-lb couples to one of the outputs 8-2 and a reference voltage ofV . A low pass filter comprising Rs and Cs couples the output of the differential amplifier to the gates of two N-channel transistors M20 and Mr?. Transistor Mzo is placed in parallel with the current source 7-2b while transistor Ms? is placed in parallel with another current source 7-2a. Both transistors Ma> and M i? supplement the currents of current sources 7 -2b and 7-2a to form a second feedback loop that adjusts the voltage on output 8-2. This embodiment of the feedback loop eliminates the cross feedback loops of FIG. 14 and FIG. 15,

The output signal between nodes 8-1 and 8-2 contains the desired product component at 2fi> and a DC component that is constant independent of where the triode multiplier couples to the signals of the distribution tree network. The desired product component at 2f¾ can be easily extracted when its DC component remains constant independent of posi tion.

FIG. 1 7 presents a diagram of a double-balanced triode interface 8-7 and the current source unit 7-3 coupled to a folded cascode 17-1. The folded cascode amplifier provides a loa for the double-balanced triode interface an amplifies the signal from the double-balanced triode interface at nodes 17-2 and 17-3. The amplified signal is available at the output 17-4 of the folded cascode.

FIG. 18 presents th circui t diagram of the folded cascode 17-1. The folde cascode includes two stacks of series connected transistors. The first stack consists of the R-cihannels transistors MB and MB and the N-channel transistors M and MB. The second stack consists of the P-ehannels transistors MB and MB and the N-channel transistors Ms? and Mss. A biasing block (not illustrated) provides the voltages Y n acs, and Vdc3. The P~channel transistors MM and Mae are the eascode transistors biased by the voltage Vac. The P-channel transistors Mn and Mss p ovide a current source to the double- balanced triode interface 8-7 and the two P channel transistors M22 and MM in the two stacks. The current provided by 21 is split between or is shared by the left legs of the two triode interface circuits and the left teg (he., transistor Mr?) of the folded eascode amplifier; and the current provided by Mss is split between or is shared by the right legs of the two triode interface circ uits and the right leg (he., transistor Mar.) of the folded eascode amplifier. The N-channel "transistors form: tire eascode current: minor. The N channel transistors Mas and Mr? form the eascode component of the current mirror, A voltage Vim biases transistors Mss and M ?. The transistors MM and Mas form the remainder of the current mirror biased by tapping a node between M22 and M: in the first stack. The current through nodes 17-2 an 17-3 of the double-balanced triode interface directly connect to the source/drain node of transistors Mm and Mn and the source/drain node of transistors M25 and ¾, respectively. The folded eascode provides a current source to the double-balanced triode interface and generates rail-to-rail swings at the output 17-4 for small current changes through nodes 17-2 and 17-3 caused by the double- balanced triode interface. The folded eascode offers a large gain, a large output

impedance and stability.

FIG. 19 presents one embodiment of using feedback to set the DC voltage at the output of the folded eascode 17-1 , The output node 17-4 of the folded eascode and a reference voltage both couple to a differential amplifier 19-1. A low pass filter 19-2 couples the output of the differential ampl ifier to the gat© of transistor M¾r The drain of M» couples to node 17-3. The differential amplifier, the low pass filter, MM and MM form a feedback loop. The feedback loop adjusts the output of fee folde eascode to match the reference voltage Visas,

The output signal at node 17-4 contains the desired product component at 2fo and a DC componen that is constant independent of where the triode multiplier couples to the signals of the distribution tree network. The desired product component at 2fe can be easily extracted when the common mode vol tage of the DC component at node 17-4 remains constant independent of position.

FIG. 20 illustrates another embodiment of using feedback to set the voltage at the output of the folded cascode .17-1. The output node 17 _* 4 of the folded cascode and a reference voltage Vw« both couple to a differentia! amplifier with a differential output 20-2. The low pass filter 19-2 couples it first output of the differentia! amplifier to the gate of transistor iv The low pass filter 20-1 couples a second output of the differential amplifier to die gate of transistor M3Q, The drain of js· couples to lead 17-3 while the drain of Mao couples to lea 17-2. The differential amplifier, the low pass filter, Maw the first stack, and Mss form a feedbac k loop. The feedback l oop adj usts the output of the folded cascode the match the reference voltage Yfew.

FlGs. 12-16 use feedbac techniques to maintain the common mode voltage of the output node of the circuit at a reference voltage specified by \¾a . The output signal at these output nodes contains the desired product component at 2fo and the DC component corresponding to the common mode voltage that due to feedback is constant independent of where the triode multiplier couples to the signals of the distribution tree network. The output nodes 8-1 an 8-2 include both the desired differential product component at 21¾ an a DC component corresponding to the common mode vol tage that is now set to Y _bias . The DC component remains constant independent of where the triode multiplier couples to the signals of the distribution tree network. The desired differential product component at 2io can easily be extracted from a node where the common mode voltage of the differential signal remains constant

FIGs. 19-20 use feedback techniques to maintain the DC voltage of die output node of the circuit at a reference voltage specifie by V The output signal at this output node contains the desired product component at 2fo and die DC component corresponding to this DC voltage. The feedback technique maintains the PC voltage constant independent of where the triode multiplier couples to the signals of the distribution tree .network. The output node 17-4 includes both the desired product component at 2fo and a DC component that is now set to a voltage ofVwas. Eliminating leakage and DC components with a Tank Circuit

As described earlier, the triode interface 5~2 within the triode interface generates three components: the reference product component, the leakage component, and the DC component. FIG. 21 illustrates how a bandpass fil ter 21-1 used as the load of a triode interface can eliminate both the leakage component and a DC component simultaneously. Instead of using a double-balanced triode interface comprising two triode interfaces; only one triode interface is required. Each leg of the triode Interface couples to tank circuit. Output node 1-3 couples to a tank circuit formed by Li and€?. Output node 21-4 couples to a tank circuit: formed by SL and€¾. The output nodes 21-3 an 21-4 of the multiplier couple via a toad.

As illustrated in the spectrum plots of 21-2, two equal frequency tone signals, Vi and Vs, each at frequency & and illustrated in the top spectrum within 21-8 are applied to the inputs of the triode interface 5-2. The triode interlace 5-2 generates all three terms: the product component at 2 ft, the leakage component at ft, and the DC component.

These three components from the triode interface couple to the bandpass filter 21-1. Each of the tank circuits within this toad is tuned to a freq uency of 2 ft; thus , the bandpass filter has a high impedance at die frequency of 2ft and has a very low impedance components at ft an DC. The leakage component at ft and the DC component are filtered out leaving only the frequency component at 2ft The product component at 2ft provides the ideal multiplication of the two frequency tones at ft applie to the inputs of the triode interface. The output signal Vdatonly contains the spectrum of the product component at 2fe as illustrated in the lower spectrum plot in 21-2. Mote that the DC component at 10-5 and the leakage component at ft have been filtered out by the bandpass filter FIG. 22 illustrates die triode interface 5-2 comprised of only MOS devices. The output signal \ r of the c ircuit in FIG. 22 only contains the spectrum of the reference product component as illustrated In the lower spectrum plot in 21-2 of FIG. 21.

FIX Phase Adding Circuit

A phase locked loop and a triode multiplier can together generate the product component at 2ft and generate a second orthogonal product component at 2ft The diagram of the circuit 23-3 illustrated in FIG. 23 presents spectrum plots at two locations within the embodiment of the circuit A multiplier 23-1 configured as a triode tnu!iipUer multiplies two signals coupled from a distribution tree network. Each of the coupled signals Stave a frequency ft and generate the spectrum illustrated within block 23-4. This spectrum contains the three components of the triode multiplier as described earlier. These components include the DC component, the leakage component at frequency ft, and product component at frequency 2ft. The first input node 23-8 of die mixer 23-2 recei ves this spectrum with the three resultant components illustrated in 23-4.

The secon input 23-7 of th mixer recei ves a frequency tone at a frequency of 2d. The mixer 23-2 mixes these three resultant components from the analog multiplier

23-1 with the frequency tone at a frequency of 2fo. The block 23-5 presents the resultant output spectrum at the output 23-6 of the mixer as a function of frequency. The components include the mixing of 2ft with DC that generates die 2ft component, the mixing of 2ft with ft that generates an ft component and a 3fb component, and the mixing of 2ft with 2ft that generates a DC component and a 4ft component

FIG. 24 A completes the embodiment of the circuit 23-3 illustrated in FIG. 23 by incorporating a phase lock loop (PLL) 24-1 with the mixer. The PLL includes a loop formed with the existing mixer 23-2, a loop fitter 24-2, and a voltage controlled oscillator (VCO) 24-4 where the output of the VCO couples to die mixer. The output 23-6 of the mixer 23 -2 couples to the input of the l oop filter 24-2. The output 24-3 of the loop filter

24-2 couples to the input of die VCO 24-4 and die output of the VCO couples back to a second input node 23-7 of the mixer. The VCO generates frequency tone at 2ft an applies this frequency tone to the second input of the mixer.

With the P LL included* die output «ode 23-6 of the mixer generates the spectrum 24-5 This spectrum is similar to die spectrum 23-5 presented in FIG 23; however, in 24- 5 the loop filter 24-2 applies a low pass filter mas 24-6 to the spectrum. Due to the low pass fil tering 24-6 of the loop filter, the DC component on node 24-3 is the only component remaining at the output 24-3 of the loop filter. The loop filter eliminates the remaining higher frequency components: ft, 2fb, 3 ft, and 4ft within the spectrum plot of 24-5. The VCO 24-4 receives the DC component on node 24-3 from the loop filter. The operation of the PLL adjusts the phase of the tone frequency at 2fo at the out ut of the VCO coupled to the second input node 23-? of the mixer. The loop of the VCO adjusts itself to the reference tone frequency at 2fe provided to the first input node 23-8 of ie mixer by the multiplier 234. hi the process of the phase adjustment of the PLL, the DC component on node 23-6 reduces in magnitude. As the magnitude of the -voltage of the DC component reduces, the frequency tone at 2ti) at the output of the VCO becomes closer to being orthogonal (90 degree phase difference) to the frequency tone at 210 of the signal applied to: the input node 23-8 of the mixer. Eventually, the PLL reduces the DC component to zero. At this point, the VCO locks. The locked VCQ generates a frequency tone at 2fo at the input node 23-7 to the mixer that is phase shifted from die frequency tone at 2fa applied to the first input node 23-8 of the mixer by 90 ^® (this also represents the desired output signal of the circuit). The circuit configuration of die analog multiplier, mixer, and PLL illustrated in FIG. 24A is another embodiment of a phase adder.

The active antenna array requires aplurality ofphase adders. Each phase adder generates a reference product component at a frequency tone at 2fb, Each antenna element of the active aatenna array requires at least one separate reference product componen t operating at a frequency tone of 2i¾ Thus, each instance of an antenna in an active antenna array requires a corresponding instance of a phase adder. Furthermore, each instance of the reference product component appl ied to each antenna needs to

synchronized in phase and frequency to every other instance of the reference product component that is applied to even· other antenna within the antenna array. Each one of the plurality of phase adders couples into the distribution tree network at different physical locations. The signals of the distribution tree network have a fixe global network parameter called“synchronization Sight time”. Based on this parameter, the phase adder generates a reference product component, which is essentially phase coherent (practically identical phase) to ever other instance of reference product component generated by the remaining plurality of phase adders. Any phase adder that couples into the signals of the distribution tree network at an location therefore generates reference product component that is phase coherent to every other instance of phase adder coupled into the signal of the distribution tree network. The signals of the distribution tree network guarantee a phase coherency over the entire area that the array of an active antenna array occupies. For further details of using a plurality of phase adders in an active antenna array, see Mihai Banu. Yiping Feng, and Vladimir Prodanov“Low Cost, Active Antenna Arrays” US Patent 8,611,959, published December 17, 2013, fee disclosure of which is incorporated herein by reference in its entirety.

FIG. 24B illustrates an embodiment of a phase adder where fee PLL loop includes a buffer 24-8. The buffer can drive larger loads without significantly affecting the performance of the PLL. The buffer 24-8 provides the reference product component at 2f¾ back to the second input node 23-7 of fee mixer. The buffer can drive larger loads via the output lead 24-9. The signal on lea 24-9 provides the reference product component at 211) to at least one antenna of the phased array. The remaining phase adders coupled to different portions of the distribution tree network provide their own version of the reference product component at 2f>, All instances of the reference product component at 2fo generated by their respective phase adder is globally in phase over the entire phased array. This global reference product component at 2fb presented to each antenna enables the accurate steering of the various beams of the communication channe ls estab lished by fee phased array.

FIG. 25 presents a side-by-side comparison between the model initially presented in FIG. 23 comprising the analog multiplier 23-1 a d the mixer 23-6 an the

corresponding circuit and block equivalents shown to the right The first and second inputs of the analog multiplier 23- 1 couple to the frequency tones of fo coupled from the distribution tree network. The corresponding circuit implementation presents a double- balanced triode interface 8-7 receiving the differential frequency tone of fo from fee network of the distributional tree signals. Note that the double-balance triode multiplier 8-7 and the Gilbert mixer 25-3 are electrically stacked together so that the bias currents feat are provided to the multiplier circuit by fee current source section also serve as bias currents for the mixer circuit.

The analog multiplier 23-1 generates a multiplied result. Th double-balanced triode interface 8-7 generates a corresponding multiplied result on its two output leads as shown. A first input of the mixer 23 -2 receives the multiplied result, the second input of the mixer receives a frequency tone of 2f> and fee output 23-6 provides fee mixed signal result. The corresponding circuit of the mixer 23-2 is the double-balanced Gilbert mixer 25-3 that recei ves the multiplied resul from the double-balanced triode interface 8-7 s the multiplied result and. a balanced dual frequency tone of 2i¾ on input leads 25-4 and 25-5 as a second input. The differential outputs 25-1 and 25-2 of the double-balanced Gilbert mixer provide the mixed signal result.

FIG. 26 illustrates one embodiment describing the components necessary to form a phase adder using a FIX formed with the double-balanced Gilbert mixer 25-3, Low pass filters 26-1 and 26-2 optionally filter the outputs of the double-balanced Gilbert mixer 25-1 and 25-2, respectively. These filtere outputs couple to an amplifier 26-3

The amplifier couples to the input of a loop filter 26-4. The loop filter passes the DC component and eliminates the fo components and their harmonics. Tire output of the loop filter couples to the VCO 24-4. The differential outputs of tire VCO operating at 2I¾ couple to the gates of the double-balanced Gilbert mixer 25-3. This final phase adder circuit is die equivalent to the circuit described in FIG. 24L.

The multiplied resul t on leads 26-6 and 26-7 from the double-balanced triode interface comprising die ideal 2i¾ multiplied component mixes in the double-balanced Gilbert mixer 25-3 with the 2fi> output signals 25-4 and 25-5 from the VCO 24-4. The operation of the PLL causes the 2fe output of the VCO to become orthogonally locke to the reference 2fe current signals on leads 26-6 and 26-7 generated by the double-balanced triode interface.

FIG. 27 illustrates another embodiment of die phase adder using other components to form a PLL wife the double-balanced Gilbert mixer 25-3 The double- balanced Gilbert mixer outputs 25-1 and 25-2 couple to a folded cascode 17-1. The output of the folded cascode is DC filtere by the loop filter 26-4 and applied to the VCO 24-4,

The distribution tree network couples a first differential signal carrying a differential reference product component tone ¾ flowing in a first direction and couples a second differential signal carrying frequency tone fo in a second opposite directio to the multiplier. The first differential signals 27-3 and 27-4 couple to transistors M-, Ms, Mio, and Mi i . These transistors switched the L s current ia each of the triode interfaces. The second diffe ntial signals 27- .1 and 27-2 couple to the gates of the triode transist ors M6 and M9. These transistors control the current flow I between the legs of the triode interfaces. The magnitude of the current flow I is typically muc less tha the magnitude of the currnt Lm.

FIG. 28 illustrates a block diagram of FIG. 27 with an additional component added within the PLL loop. The additional component is a differential buffer 28-L The differential buffer is part of th PLL loop and can drive large loads without influencing the performance of the PLL, otherwise the operation is similar to that of FIG. 26.

FIG . 29 illustrates an embodiment of a phase adder where the transistor stack of the triode interface and double-balanced Gilbert mixer are partitione to provide additional voltage headroom in case the power supply is reduced. The multiplied result from the double-balanced triode interface couples to a current mirror 29-1, The current mirror controls the current source 29-2 and provide current to a double-balanced Gilbert mixer 29-3 implemented using N-channel transistors. The PLL consists of the components double-balanced Gilbert mixer, the folded caseod 17-1 , the loo filter 26-4, the VCO 24-4, and the buffer 28-1.

Note that most of the above-described circuits are preferably fabricated on a single integrated circuit chip on which much greater uniformity among the characteristics and performance of the devices is more easily achievable. This includes, for example, the circuits illustrated by Figs 5-7, BA, 9, 10A, 1 1-21, 24A, 24B, and 25-29.

Removing phase errors due to practical Impairments

The practical realisations of th phase adding circuits disclosed in the previous sections may have non-aeghgible output phase errors due to transistor mismatches, bias variations, temperature variations, undesired signal coupling, etc. In other words, the output phase of the practical realizations will be di fferent from the ideal sum of the t wo input phases by an error value. Next, techniques to reduce or eliminate these practical phase errors are described. These techniques are also referred as calibration methods. hi the case of the PLL-based phase-adding circuits, such as those of FIG. 24 A and FIG 24B, a major source of output phase errors is the generation of undesired DC offsets throughout the circuit For example, any signal propagating through a transistor, which is a nonlinear device, can generate DC spurs, which can potentially end up through various mechanisms, at the output of the phase adder and at the input of the VCQ because the PLL loop filter allows DC to pass. When in lock, the PLL drives the total DC signal at the input of the VCO to zero . S ince thi s total DC signal at the input of the VCO is composed of the desired DC sign al and the sum of all DC errors, when the PLL is in lock, the desired DC signal will equal toe negative: of the sum of all DC errors. This creates phase errors at the output of the VCO, which is the output of toe realized phase adder.

A method for minimizing or eliminating the phase errors mentioned above is to calibrate ou the DC errors at the in put of the VCO. This can be done by first shifting toe signal frequency at the second input of the mixer (23-7 in FIG. 23) from 2fato 2fb+Af, where is a small frequency shift compared to f¾. This makes toe desired phase adding DC component at toe input of the VCO zero because the two input signals of mixer (23-2 in FIG. 23) have different frequencies. The only remaining DC component at the input of the VCO is the sum of all DC errors. Notice that shifting only the signal frequency of the second input of toe mixer is a minimally invasive action to the phase adder circuit, leaving all other component connections and signals of the phase adder intact, including most of the DC error generating mechanisms in the circuit In parallel with shifting only the signal frequency of the second i nput of the mixer , the PLL loop must be broken so t he input of the VCO is not forced to zero b the loop. Next one can monitor the DC errors (e.g. compare t a set value) and calibrate them out with an additional circuit After this calibration is performed, the PLL loop is reconnected to the original configuration.

The following presents implementations of this concept together with adding PLL locking aid mechanisms.

FIG. 30A illustrates one embodiment of a cal ibration circuit used to calibrate a phase adder. Tire phase adder circuit illustrated in FIG. 27, for example, can use this calibration circuit to calibrate the Primary PLL within the phas adder. A side-by-side comparison of FIG 30A and FIG. 27 would highlight common components within eac of these circuits. For example, the circuit schematics for the analog multiplier 23-1 and the mixer 23-2 in FIG. 30.4 are illustrated in FIG. 27 within the corresponding doted boxes 23-1 and 23-2, respectively. In FIG; 27, the components of the folded cascode 17- 1, the loop filter 26-4, the VCG 24-4, and the double-balanced Gilbert mixer 23-2 form “Primary MX Loop”. Note that in F G. 30A, (disregarding the bu fer 28-1 ) the same listed components would form the“Primary FIX Loop” which is currently open due to the position of three-way switch SW3.

Switch SW 1 is set to form a different PLL loop called the“Initialization PLL Loop”. This loop includes components common to“Primary PLL Loop”, namely, the loop filte 26-4 and the VCO 24-4 (and the buffer 28-1). However, the“Initialization PLL Loop” uses the new circuit components including a divide-by-two circuit 30-2 and a phase and frequency detector 30-3, to complete the“initialization PLL Loop” The newly formed“Initialization PLL Loop” includes the phase frequency detector 30-3, the loop filter 26-4, the VCO 24-4, a buffer 28-1, and the divide-by-two circuit 30-2, The “Initialization P L L Loop” sets the operating frequency of the VCO 24-4 to twice the frequency of the fa frequency tone coupled from the signals of the distribution tree network. The fo frequency sen· es as a reference product component for the phase frequency detector 30-3. The phase frequency detector 30-3 compares the reference product component fo from tire distribution tree network with the frequency of the VCG 24-4 after being dlvided-by-two circuit 30-2 The“Initialization PLL Loop” settles to generate a DC control voltage at node 30-16 at the output of the loop filter 26-4 that causes the VCO to operate at a frequency 2fo.

Before the SW1 is switched back to create the“Primary PLL. Loop”, the DC voltage at the output of the folded cascode 17-1 needs to be adjusted to match the DC control voltage of the“Initialization PLL Loop” at the output of the loop filter 26-4, which is stored in the memory block 30-17. To accomplish this, the switches SW 1 and SW2 are changed to initialize the DC voltage at the output of the folded cascode. To calibrate out only the DC errors but not the desired phase adding DC component at the input of the VCO, the conditions of the switches SW1 and SW2 are change as shown in FIG. 3GB. SW2 is turned off to disconnect emory' 30-17 fro the“Initialization. PLL Loop”. And the“Initialization PLL Loop” is broken by switchi gthe SWl to a

frequency selection block 36- 18. The frequency selection block 30- 18 changes the DC control voltage 30-16 and the input of the V€G 24-4. As a result, site VCD frequency is shifted from 2¾ by a small amount Af by setting the frequency selection 30-18 to the desired frequency hand.

Referring to TIG. 30B, the output 30-13 of the mixer 23-2 draws current from the folde cascode 17-1. As note previously, the folded eascode has a very large gain with a very sharp transfer curve. Th DC vol tage of the output 30-14 of the folded cascode is dependent on the signal received from the mixer 23-2 as well as the process variations imposed on the transistors due to the fabricati n of the integrated circuit. To compensate for the uncertainty of the DC voltage at the output of the folded cascode, a“feedback loop” formed by the folded cascode 17-1, a low pass filter 30-4, a comparator 30-5, a state machine 30-6, a current adjust circuit 30-7, and a summer 30-8 is formed it is desirable to set the DC voltag at the output 30-14 of the folded cascode 17-1 to match the DC control voltage Vb stored in the memory 30-17, which was generated for the VC0 in the previously described‘Initialization PLL Loop”.

The comparator 30-5 within the feedback loop compares the DC voltage stored m the memory 30-17 with the DC output voltage at the output of the folded cascode 30-14 via the low pass filter 30-4 The comparator 30-5 compares these two input signals and applies the resultant: signal to a sequential state machine 30-6. The sequential state machine produces an output based on the result of the comparator. The output 30- 15 fro the state machine adjusts the current in the current adjust circuit 30-7 in small incremental steps. The adder 30-8 combines the small incremental currents to the existing current that the folded eascode 17-1 sources to the mixer 23-2. The small incremental currents cause the DC operating poin at the output 30-14 of the folded cascode to change an thereby reduce the difference between the signals applied to the inputs of the comparator 30-5. The sequential state machine receives the output of the comparator and if that output is not zero, it increments the current to the adder 30-8. This process continues until the difference between the inputs applied to the comparator 30-5 approach zero. Once the comparator determines that the difference passes zero and becomes negative, the state machine ceases operation and stores the digital state of th current adjust circuit 30-7 in a memory (not shown). The stored result is then

continuo usly applied to die current adjust circuit 30-7 such that the ou tput voltage at 30- 14 of the folded cascode 17-1 substantially matches the voltage value stored in the memory block 30-17, which equals the voltage that causes the V CO to operate at a frequency of 2fc.

Once the DC voltage at the outpu t 30-14 of the folded cascode 17-1 matches the loop control voltage stored at the memory 30-17, the DC error calibration is finished lire control voltage 30-16 is re- set to die value store a the memory 30-17 by switching switch SW! into its third position connecting the output of folded cascode 17-1 to the input of loop filter 26-4 as illustrated in FIG. 30C. The new switch position forms the “Primary FIX Loop” as indicated.

With the“Primar PLL Loop” formed in this way, the analog multiplier 23-1 generates three components: a product component at 210, a leakage component at ft, and a DC component, and it applies these signals to the mixer 23 -2 via input line 30-1 1. The mixer 23-2 generates the mixing products on node 30-13. These include the mixing of 2fi X DC generating a 2ft component, the mixing of 2ft X ft generating an ft component and a 3 ft component, and the mixin of 2fc X 2ft generating another DC component and a 4ft component. The“Primary PLL Loop” has a locking range that insures that the “Primary PLL Loop” locks once this PLL loop forms. The DC component at the output 30- 16 of the loop filter 26-4 decreases through die feedback action of the“Primary PLL Loop”. As the DC component reduces to zero, the phase difference between the 2ft signals applied to the inputs of the mixer 23-2 approach 00° and orthogonally phase locks die frequency of the VCO to the reference product component tone at 2ft at the output of the analog multiplier 23-1. These calibration steps when perforated throughout the entire system ensure that the frequencies of all instances of the phase adders within the entire system are globally identical and phase locked.

Fig. 33 A illustrates another embodiment of the circuit presented in FIG. 30A b replacing the 2ft VCO 24-4 with a 4fc VCO 31 -3, The frequency at 4ft is divided with a divide-by-two circuit 31 -1 to generate land Q signals each at frequency 2ft and separated by 90°. Each of the 1 and Q signals is buffered by buffers 28-1 and 31-2, respectively in other respects, the operation of the circuit in FIG. 31 A mirrors that of the circui t in FIG. 30A FIG. 31 B illustrates the formation of the DC calibration loo after switches SWI and SW2 change connectivity. FIG. 31C illustrates the formation of the Primar PLL loop after switches S WI and SW2 again change connectivity. The circuits operate similar to the circuits illustrated by FIG. SOB and FIG. 3QC, except that the VCG phase locks at a frequency of 4& an generates an I and Q signal operating at a frequency of 2f _>,

FIG. 32 illustrates an implementation of the system show» in FIG. 30A with the current adjust circuit 30-7 implemented as two current adjust blocks 32* la and 32- lb that are digital transistor arrays. Also, mixer 23-2 is implemented by a double balanced Gilbert mixer such as Gilbert mixer 25-3 illustrated in Fig. 25; and multiplier 23-1 is implemented by a double balanced triode interface such as double balanced triode interface 8-7 illustrated i Fig. 8A. The state machine 30-6 adjusts the digital weight applie to the gates of the transistors of the digital transistor array. Adjusting the digital weight alters the current through the digital array. These currents adjust die current flowing through the folded easeode 17-1 and alter the output voltage of the folded caseode. The comparator 30-5 compares the voltage difference at its inputs and sends the results to the state machine. The state machine 30-6 takes sequential incremental steps to make changes to the digital transistor array according to the information received from the comparator. The process continues sequentially until the difference at the inputs to the comparator approaches zero and then switches polarities. The state machine stops the sequential comparisons and stores the digital weight in memories (not shown).

FIG. 33 shows the embodiment of FIG. 32, but with the digital transistor arrays represente by current adjust blocks 32-la and 32-lb, absent the details of the internal structure of those blocks. In all other respects, the circuit shown in Fig 33 is the same as what is shown in Fig. 32.

FIG 34 presents a flo wchart of a computer or processor implemented algorithm for initializing and phase locking the frequency of a VCO to the reference product component i¾ coupled from the signals of the distribution tree network. In ste 34-1 (and also referring to FIGS. 30A-C), loop filter 26-4 coupled to VCO 24-4 within the

initialization FIX loop locks the VCO in frequency to one of the plurality of signals of the distribution free network (DTN) that is coupled to the phase frequency detector 30-3 The initialization FLL loop includes divider 30-2, phase frequency detector 30-3, loop filter 26-4, and VCO 24-4 The signals of the distribution tree network have a frequency offo and the VCO operates at a frequency that is an integer multiple of fo.

In step 34-2, the DC voltage output of die loop filter 26-4 in th first PLL is stored in memory 30-17, and then memory 30-7 is connected to a first/input/of comparator 30-5 within the feedback loop. The feedback loop includes comparator 30-5, state machine 30-6, current adjust circuit 30-7, folded cascode 17-1, and low pass filter 30-4. The state machine is a sequential machine. Digital operations perform decisions once per clock cycle, unless the state machine halts the sequence operation.

In step 34-3, the initialization PLL loop is broken and the frequency selection block 30- 18 is switched into the circuit to change the VCO control voltage to shift the VCO frequency from the locking frequency in the initialization PLL loop from 2fo to 2ί¾+Dί , where Af is a small frequency shift compared to J

In step 34-4, mixer 23-2 mixes the signal from the output of the analog multiplier 23-1 with the frequency generate by the VCO 24-4. The mixer 23 2, which can be a double-balanced Gilbert mixer (al though other mixer configurations are possible), generates a mixed signal. The VCO output signal couples to the double-balanced Gilbert mixer. Optionally, th buffer 28-1 buffers the VCO output signal for improved capacitance drive characteristics.

In step 34-5, the mixed signal couples through folded cascode 17-1 to a second input of the comparator 30-5. The folded cascode 17-1 provides the current source for the mixer 23-2 and generates an output signal based on the signals coming out of the mixer 23-2 Low pass filter 30-4 filters the output signal and couples the filtered output signal to the second input of the comparator 30-5. In step 34-6, a current is incrementally introduced into the feedback loop to adjust the second input to the adder 30-8 until the DC ou tput of the folded cascade i 7-1 substantially matches the voltage at the first input of the comparator 30-5. The feedback loop contains state machine 30-6, which operates sequentially. Once the comparator 30- 5 receives its two inputs, the state machine receives the comparison result of the

comparator and decides how to adjust the current into the node between the mixer an a folded eascode such that the differences between the inputs to the comparator reduce. Digitally weighed transistor arrays controlled by the state machine provide the current adjustments. The arrays include transistors placed in parallel and eac transistor has a digitally scaled width of IX, 2 , 4X, etc. The state machine enables the transistors to adjust the overall width of the array. The sequence of the state machine steps through each clock cycle an either increments or decrements the overall width of the transistor array by one minimum transistor width. Each step causes the voltage at the output of the folde cascode to change such that the difference applied to the Inputs of the comparator decreases . In the sequential process, the transistor width of the array adjusts every clock cycle. Once the voltage inputs applied to the comparator flip polarity, die state machine steps the sequential process. The digital weight that was determined by the slate machine is stored in memory _* The memory' holds the digital weight and applies this digital weight to the transistor arrays during normal operation.

In step 34-7, switch SW 1 disconnects the frequency selection block fro t the input to the loop filter 26-4 and couples the output of the folded cascode 17-1 to the input of the loop filter 26-4. This switching process also forms the primary·' PLL loop inclu in the loop filter 26-4, V CO 24-4, buffer 28-1, mixer 23-2, and folded eascode 17- L Since the voltage at the output of the folded cascode 17-1 substantially matches the voltage at the output of die loop filter 26-4, coupling them min imizes die transient behavior of the primary' PLL loop. This allows the newly formed primary PLL loop to operate well within its Socking range.

In step 34-8, the primary PLL loop phase locks the 2io frequency of VCO to the 2ί> component of the multiplied components generated by the analog multiplier 23-1

The mixer 23-2 compares these two frequencie and reduces the DC voltage component at the output of the folded easeode 17~L As the DC voltage component reduces to zero _» the primary PEL loop becomes phase locked.

Other embodiments are within the following claims. For example, network and a portable system can exchange information wirelessly by using communication techniques such as Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Code Division Multiple Access (CDMA), Orthogonal

Frequency Division Multiplexing (OFDM), Ultra Wide Band (UWB), Wi-Fi, WiGig, Bluetooth, etc. The communication network can include; the phone network, IP (Internet protocol) network, Local Area Network (LAN ), ad hoc networks, local routers and even other portable systems, A "computed’ can be a single machine or processor or multiple interacting machines or processors (located at a single location or at multiple locations remote from one another). One or mote processors that can comprise multiple interacting machines or computers generate these digital or analog control signals. A computer- readable medium can be encoded with a computer program, so that execution of that: program by one or more processors to perfor one or more of the methods of phase and amplitude adjustment The claimed semiconductor substrates can be implemented using semiconductors, such as, silicon, germanium, gallium arsenide, 111- V semiconductor, etc. Packaged units called chips contain these semiconductor substrates an mount on a circuit board within the syste of the phased array. The circuitry formed on the

semiconductor substrates can use the technology of CMOS or BiCMOS fabrication.

WHAT IS CLAIMED IS: