INJECTION-LOCKED FREQUENCY DIVIDER AND PLL CIRCUIT

Title:

INJECTION-LOCKED FREQUENCY DIVIDER AND PLL CIRCUIT

Document Type and Number:

WIPO Patent Application WO/2011/089918

Kind Code:

A1

Abstract:

Disclosed are a PLL circuit and an injection-locked frequency divider that can lessen the effect of parasitic capacitance and wherein the operating frequency is broadband. The injection-locked frequency divider (100) is provided with: a first amplification circuit (141) configured from an N-channel MOS transistor (111) and a P-channel MOS transistor (112); a ring oscillator (140) wherein a second amplification circuit (142) and a third amplification circuit (143) having a similar configuration have a ring-shaped three-stage cascade connection; an N-channel MOS transistor (150) wherein the source of the N-channel MOS transistor (111, 121, 131) of each stage is connected to the drain thereof; and a differential signal injection circuit (160) that injects an injection signal (I1) to the gate of the P-channel MOS transistor (112, 122, 132) of each stage and that injects a reversed-phase signal of the injection signal (I1) as a differential signal to the gate of the N-channel MOS transistor (150).

Inventors:

SHIMA TAKAHIRO
SATO JUNJI
KOBAYASHI MASASHI

Application Number:

PCT/JP2011/000317

Publication Date:

July 28, 2011

Filing Date:

January 21, 2011

Export Citation:

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Assignee:

PANASONIC CORP (JP)
SHIMA TAKAHIRO
SATO JUNJI
KOBAYASHI MASASHI

International Classes:

H03K3/354; H03K3/03; H03K27/00; H03L7/08; H03L7/10

Foreign References:

JPH0548402A	1993-02-26
JPH09246957A	1997-09-19
JPH1093399A	1998-04-10
JPH1093399A	1998-04-10
JP2010012131A	2010-01-21

Other References: