Technical Field

[0001] Embodiments of the invention are in the field of light emitting diode (LED) displays.

Background

[0002] As addressed in PCT Publication WO 2016/060676, filed October 17, 2014 and assigned to Intel Corp. of Santa Clara, California, U.S.A., display technology has advanced rapidly in recent years as an important user interface to electronic devices. To date, liquid crystal display (LCD) technology has been the dominant display technology for both large format (e.g., television) and mobile devices. LCD based displays however only pass through -5% of light from a backlight source (e.g., LED or CFL, etc.) leading to poor power efficiency, insufficient daylight display illumination, and poor viewing angles.

[0003] Another display technology includes organic light emitting diodes (OLED). OLED displays improve display power efficiency, though not dramatically, relative to LCD. OLED technology currently suffers from color fading, leading to decreased display

endurance/lifetime at high brightness levels that are needed for outdoors viewing (e.g., 1,000 cd/m ² ).

[0004] Another display technology is crystalline LED, also referred to as inorganic LED (iLED). A crystalline LED display relies on an array of crystalline semiconductor LED chips. A crystalline LED display, for example, may utilize one LED chip for one picture element, or pixel. The power efficiency of crystalline LED can be one order of magnitude more efficient than that of OLED, however a high volume manufacturing process is still a challenge for display applications. One of the technical challenges of crystalline LED is that a vast number of very small crystalline LEDs need to be transferred from a monolithic growth/fabrication medium into a spatially larger array electrically interconnected in a manner that enables controlled light emission. For current display resolutions (e.g., HD), one may expect hundreds of thousands or millions of crystalline LED elements within a 1 " square of display area with each crystalline LED element on the micron scale (e.g., 5μιη, or less on a side). The great number of devices and their small size has made micro scale assembly a challenging regime between monolithic devices and conventional millimeter pick-and-place assemblies. Brief Description of the Drawings

[0005] Features and advantages of embodiments of the present invention will become apparent from the appended claims, the following detailed description of one or more example embodiments, and the corresponding figures. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

[0006] Figure 1 includes a μΙ _^ Εϋ display in an embodiment. [0007] Figure 2 includes a process in an embodiment. [0008] Figure 3 depicts a system that includes embodiments.

Detailed Description

[0009] Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments more clearly, the drawings included herein are diagrammatic representations of semiconductor/circuit structures. Thus, the actual appearance of the fabricated integrated circuit structures, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may only show the structures useful to understand the illustrated embodiments. Additional structures known in the art may not have been included to maintain the clarity of the drawings. For example, not every layer (e.g., barrier layer, seed layer, etch stop layer) of a semiconductor device is necessarily shown. "An embodiment", "various embodiments" and the like indicate embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments. "First", "second", "third" and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. "Connected" may indicate elements are in direct physical or electrical contact with each other and "coupled" may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact. [0010] As discussed above, iLEDs face a number of difficult challenges before they are a viable option for mass production. The challenges only increase when the iLEDS are formed on a microscale to form micro LEDs (μίΕϋ). A μΕΕϋ, also simply referred to herein as an LED, has a largest lateral dimension on the micron scale, and advantageously has a longest lateral length no more than ΙΟμιη. Display assembly embodiments and fabrication techniques exemplified herein are highly scalable being suitable for LEDs in the 1- ΙΟμιη range, for example. Although described herein in the context of a few or even a single LED for the sake of clarity, the exemplified are also understood to be applicable to concurrent

fabrication/assembly of a vast number LEDs.

[0011] More specifically, Applicant has determined a challenge exists for micro level iLEDs regarding planarization of dielectric layers. To make active matrix μΕΕϋ display panels, μΕΕϋβ that emit red (R), green (G) and blue (B) colors are first fabricated on separate wafers (e.g., silicon or sapphire) and then transferred from the wafers to thin film transistor (TFT) backplanes to make RGB pixels that make the active matrix μΕΕϋ display panel.

[0012] However, Applicant has determined that in order to place μίΕϋβ on a backplane TFT, the receiving backplane surface must be substantially planar, otherwise transfer yield will be significantly degraded. This is problematic because the conventional fabrication process of TFT backplanes does not result in a planar surface because the substrate size (e.g. 1.4 xl .3 m ² ) is too large for chemical -mechanical polishing (CMP) to be practically used in planarizing the passivation dielectric (e.g., oxide or nitride) that is deposited on top of TFTs.

[0013] Furthermore, Applicant had determined still other problems exist for μΕΕϋβ beside non-planarized dielectric surfaces. iLEDs are driven by very high speed digital pulse trains. But these digital pulse signals can be improperly changed (e.g., morphology of the pulse train changes) due to capacitance between the transparent electrode that couples to the μίΕϋ and the interconnects that couple a TFT to the μΕΕϋ.

[0014] Embodiments described herein addressed both the planarization and the capacitance issues. Embodiments do so by using a doped dielectric (e.g., oxide or nitride) for a passivation dielectric and then planarization of the passivation dielectric using microwave annealing or laser annealing. [0015] An embodiment includes an apparatus 100, such as a crystal μίΕϋ display, a portion of which is shown in Figure 1. Various TFT circuits 121, 122, 123 couple to substrate 106 (which may be silicon or glass or some other material). A dielectric layer 105 may be formed on substrate 106 and the dielectric layer may form gate oxide for metal gates of the TFTs, such as gates 130, 131. Another dielectric layer 101 may be formed on the TFT circuits 121, 122, 123. The dielectric layer may include portions of the TFTs such as channels 124, 125 (which may include, for example, Indium gallium zinc oxide (IGZO)) along with source/drain nodes 126, 127, 128, 129 (as can be seen TFT circuit 121 is representative of circuits 122, 123 so only circuit 121 is discussed in detail). Layer 101 may further include portions of metal interconnects 117, 118, 119.

[0016] Upper surface 141 of layer 101 may be planarazied. However, since layer 101 is on substrate 106, and substrate 106 is relatively large (e.g., greater than or equal to 1.0 x 1.0 m ² ) CMP is not a viable option for planarizing surface 141. Instead, embodiments utilize microwave annealing and/or laser annealing to planarize surface 141. As such, these methods provide a relatively shallow "reflow" to an upper half 145 of layer 101 without affecting lower half 146 (or the TFT components in general). The refl owing of material results in planarization of the top surface. In other words, in dielectric layer 101 portion 145 is annealed and portion 146 is not annealed in an embodiment. As a result metal components (e.g., metal interconnects like components 130, 131 and/or source/drain nodes 126, 127, 128, 129) are not affected as they might be if a conventional anneal were conducted on layer 101. While in some embodiments some contacts may be formed after the planarization occurs (e.g., possibly source/drain node contacts 126, 127, 128, 129 and portions of interconnects 117, 118, 119) still other components may already be formed (e.g., metal gates 130, 131) before planarization of surface 141 occurs.

[0017] After surface 141 is planarized, iLED 111 may be transferred onto surface 141. The iLED may include top and bottom metal electrodes between which are p doped and n doped layers of, for example, Gallium Nitride (GaN) that collectively form the iLED. Methods for forming such LEDs and transferring such LEDs onto other substrates is discussed in, for example, the aforementioned PCT Publication WO 2016/060676 and are not discussed herein for purposes of brevity. In an embodiment the bottom such electrode of LED 111 directly contacts the top surface 141 of the first dielectric layer and does so successfully due to the planarization of surface 141. In an embodiment the surface of the electrode that directly contacts the top surface 141 is not planarized and is rougher than the top surface 141.

[0018] An additional dielectric layer 102 is then formed. Layer 102 includes LED 111. Similar to layer 101, surface 142 is planarized using, for example, microwave or laser annealing.

[0019] In the embodiment of Figure 1 TFT 121 includes a metal gate 130, 131 that is between the LED 111 and the substrate 106 but in other embodiments this specific orientation of components is not mandatory (e.g., the TFT may be above LED 111). Further, in Figure 1 TFT 121 is a "bottom gate" device but in other embodiments the TFT may be a "top gate" TFT.

[0020] In an embodiment top surface 142 is planarized and an optically transmissive interconnect (e.g., interconnect 144) is on the planarized top surface. Thus, not all embodiments include layers 103, 104.

[0021] However, in the embodiment of Figure 1 another LED 112 is transferred onto top surface 142 and dielectric layer 103 is formed to include LED 112. The LED 112 is inorganic and the top surface 143 of the dielectric layer is planarized using, for example, microwave or laser annealing.

[0022] The embodiment of Figure 1 includes another μΕΕϋ 113 on the top surface 143 and dielectric layer 104 is formed, which includes LED 113. LED 113 is inorganic and surface 144 is planarized using, for example, microwave or laser annealing.

[0023] Optically transmissive interconnect 120 (e.g., indium tin oxide (ITO) or ZnO) is on top surface 144 and is coupled (using interconnects 114, 115, 116) to each of the first, second, and third LEDs 111 (e.g., Red), 112 (e.g., Green), 113 (e.g., Blue). In an

embodiment optically transmissive interconnect 120 directly contacts the top surface 144 and does so successfully due to the planarization of surface 144.

[0024] As mentioned above, an additional dielectric layer (such as layer 105) may be included between dielectric layer 101 and the substrate 106. Furthermore, a metal interconnect (e.g., 117) may be included between LED 111 and the substrate 106. Further, in an embodiment none of the dielectric layers 101, 102, 103, 104 are monolithic with each other. While substrate 106 includes glass in other embodiments the substrate may include a silicon wafer or some other material In an embodiment, the TFT, the dielectric layer 101, and the substrate 106 are all included in a TFT backplane 150 and the substrate 106 is greater than 1.0 x 1.0 m ² (and therefore not conducive to planarization by CMP). In an embodiment, there is no etch stop layer between a dielectric layer (e.g., layer 101) immediately underlying an LED (e.g., LED 111) and the LED. Such an etch stop may be present between, for example, layer 101 and LED 111 if CMP had been used to planarize the top surface of layer 111.

[0025] In an embodiment each of LEDs 111, 112, 113 includes GaN but other

embodiments may include, for example, AlGalnP or AlGaAs. The GaN (or other material) may be in crystal form.

[0026] In an embodiment at least one of the dielectric layers 101, 102, 103, 104 is doped with at least one member selected from the group consisting of carbon, boron, phosphorous, hydrogen, and fluorine (or other low K dielectric materials). For example, in device 100 each of layers 101, 102, 103, 104 is Carbon doped but in other embodiments the layers need not all be doped are all doped with the same element.

[0027] As mentioned above, lower portion 146 may not be annealed while upper portion 145 is annealed in layer 101. The same is true for each of layers 102, 103, 104.

[0028] An embodiment includes a signal source (e.g., a current source like a timing controller and/or pulse width modulation logic that couples to LED drivers that in turn provide drive signals to the TFT circuits 121, 122, 123) configured to drive the TFT and the first LED with a digital drive pulse train.

[0029] Figure 2 includes a method 200 in an embodiment. Method 200 entails providing a substrate (block 201), depositing a buffer, such as Si0 ₂ in layer 105 (block 202), depositing a metal gate of TFT, such as gate 130 (block 203), patterning a metal gate of TFT (block 204), depositing gate oxide, such as oxide 101 (block 205), depositing channel materials, such as channel 124 (block 206), patterning the channel materials (block 207), depositing a passivation dielectric, such as layer 101 (block 208), planarizing the passivation oxide using microwave or laser annealing for a surface, such as surface 141 (block 209), opening source/drain and gate contacts through the planarized passivation oxide (block 210), depositing source/drain and gate metals in contact holes (block 211), removing excess metals by wet etch (block 212), transferring an iLED, such LED 111, to the planarized surface (block 213), depositing passivation dielectric, such as layer 102 (block 214), planarizing passivation oxide using microwave or laser annealing for a surface, such as surface 142 (block 215), transferring an iLED, such LED 112, to the planarized surface (block 216), depositing passivation dielectric, such as layer 103 (block 217), planarizing passivation oxide using microwave or laser annealing for a surface, such as surface 143 (block 218), transferring an iLED, such LED 11, to the planarized surface (block 219), depositing passivation dielectric, such as layer 104 (block 220), planarizing passivation oxide using microwave or laser annealing for a surface, such as surface 144 (block 221), forming a transparent electrode on the planarized surface (block 222). Such a method may also include typical interconnect formation steps for interconnects such as interconnects 114, 115, 116. Further, the process may include doping any of the dielectric layers, such as layers 101, 102, 103, and/or 104 to address capacitance between interconnects such as interconnects 144, 114, 115, 116, 117, 118, 119.

[0030] An embodiment includes doping any of layers 101, 102, 103, 104 with boron and phosphorous to provide better smoothing of step corners. Such a doped dielectric can be made to reflow at high temperatures (850-959 °C). Other embodiments include

carbon-doped oxide deposited using Plasma-enhanced chemical vapor deposition (PECVD).

[0031] Thus, embodiments utilizing the planarization of a TFT backplane described herein will result in high yield of transferred μίΕϋβ from wafer to backplane. Such embodiments enable the manufacturing of cost-effective and high performance, low power displays used in Notebooks, Tablets, Smartphones, Wearables, and the like. Such displays will consume less power and extend battery life for devices, thereby adding value to such devices.

[0032] Further, even with substrates that are small enough for CMP, embodiments described herein still provide advantages in that when there are dense structures on the substrate (e.g., more TFTs in some areas than in others), carbon-doped oxide deposition will leave a characteristic non-perfect gap fill signature. For example, top surface 141 may be slightly elevated over areas rich in TFTs and slightly depressed in areas void of a high number of TFTs. CMP has difficulty smoothing these elevated and depressed areas into a single level plane because the source (TFTs) is buried and cannot be smoothed. However, when laser or microwave annealing is used to reflow the oxide, these gap-fill signature features smooth out.

[0033] Various embodiments include a semi conductive substrate. Such a substrate may be a bulk semiconductive material this is part of a wafer. In an embodiment, the semi conductive substrate is a bulk semiconductive material as part of a chip that has been singulated from a wafer. In an embodiment, the semiconductive substrate is a semiconductive material that is formed above an insulator such as a semiconductor on insulator (SOI) substrate. In an embodiment, the semiconductive substrate is a prominent structure such as a fin that extends above a bulk semiconductive material.

[0034] Referring now to Figure 3, shown is a block diagram of an example system with which embodiments can be used. As seen, system 900 may be a smartphone or other wireless communicator or any "Internet of Things" (IoT) device. A baseband processor 905 is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system. In turn, baseband processor 905 is coupled to an application processor 910, which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps. Application processor 910 may further be configured to perform a variety of other computing operations for the device.

[0035] In turn, application processor 910 can couple to a user interface/display 920 (e.g., touch screen display). In addition, application processor 910 may couple to a memory system including a non-volatile memory, namely a flash memory 930 and a system memory, namely a DRAM 935. In some embodiments, flash memory 930 may include a secure portion 932 in which secrets and other sensitive information may be stored. As further seen, application processor 910 also couples to a capture device 945 such as one or more image capture devices that can record video and/or still images.

[0036] A universal integrated circuit card (UICC) 940 comprises a subscriber identity module, which in some embodiments includes a secure storage 942 to store secure user information. System 900 may further include a security processor 950 (e.g., Trusted Platform Module (TPM)) that may couple to application processor 910. A plurality of sensors 925, including one or more multi-axis accelerometers may couple to application processor 910 to enable input of a variety of sensed information such as motion and other environmental information. In addition, one or more authentication devices 995 may be used to receive, for example, user biometric input for use in authentication operations.

[0037] As further illustrated, a near field communication (NFC) contactless interface 960 is provided that communicates in a NFC near field via an NFC antenna 965. While separate antennae are shown, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionalities.

[0038] A power management integrated circuit (PMIC) 915 couples to application processor 910 to perform platform level power management. To this end, PMIC 915 may issue power management requests to application processor 910 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 915 may also control the power level of other components of system 900.

[0039] To enable communications to be transmitted and received such as in one or more IoT networks, various circuitry may be coupled between baseband processor 905 and an antenna 990. Specifically, a radio frequency (RF) transceiver 970 and a wireless local area network (WLAN) transceiver 975 may be present. In general, RF transceiver 970 may be used to receive and transmit wireless data and calls according to a given wireless

communication protocol such as 3 G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. In addition a GPS sensor 980 may be present, with location information being provided to security processor 950 for use as described herein when context information is to be used in a pairing process. Other wireless communications such as receipt or transmission of radio signals (e.g., AM/FM) and other signals may also be provided. In addition, via WLAN transceiver 975, local wireless communications, such as according to a Bluetooth™ or IEEE 802.11 standard can also be realized.

[0040] Embodiments, such as iLED displays described herein, may be included in the above mentioned displays (e.g., display 920) of mobile computing nodes, wearable computing nodes, and the like.

[0041] The following examples pertain to further embodiments. [0042] Example 1 includes an apparatus comprising: a thin film transistor (TFT) coupled to a substrate; a first dielectric layer on the TFT; an inorganic first light emitting diode (LED) on the first dielectric layer; and a second dielectric layer including the first LED; wherein: (a)(i) a surface of the first dielectric layer is planarized; and (a)(ii) the first LED is on the planarized surface of the first dielectric layer.

[0043] In an embodiment, any or all of the doped oxide layers in an apparatus are transparent to visible light. In an embodiment, any or all of the doped oxide layers is betweenlOO nm and 300 nm in thickness (measured vertically) so light from LEDs is seen properly by the viewer of the display.

[0044] Example 2 includes the apparatus of example 1, wherein the TFT includes a metal gate that is between the first LED and the substrate.

[0045] Example 3 includes the apparatus of example 2 wherein a surface of the second dielectric layer is planarized and the apparatus comprises an optically transmissive interconnect that is on the planarized surface of the second dielectric layer and is coupled to the first LED.

[0046] Example 4 includes the apparatus of example 3 wherein the first LED includes Gallium Nitride (GaN).

[0047] Example 5 includes the apparatus of example 4 wherein at least one of the first and second dielectric layers is doped with at least one member selected from the group consisting of carbon, boron, phosphorous, hydrogen, and fluorine.

[0048] Example 6 includes an apparatus comprising: a substrate; a thin film transistor (TFT) on the substrate; a first dielectric layer on the TFT; a first light emitting diode (LED) on the first dielectric layer; and a second dielectric layer including the first LED; wherein: (a)(i) the first LED is inorganic; (a)(ii) the first dielectric layer includes a bottom surface between a top surface of the first dielectric layer and the substrate; (a)(iii) the top surface of the first dielectric layer is planarized; and (a)(iv) the first LED is on the top surface of the first dielectric layer. [0049] Example 7 includes the apparatus of example 6 wherein: the second dielectric layer includes a bottom surface between a top surface of the second dielectric layer and the substrate; and the top surface of the second dielectric layer is planarized.

[0050] Example 8 includes the apparatus of example 7 comprising an optically transmissive interconnect that is on the top surface of the second dielectric layer and is coupled to the first LED.

[0051] Example 9 includes the apparatus of example 8 wherein the first LED includes Gallium Nitride (GaN).

[0052] Example 10 includes the apparatus of example 9 wherein at least one of the first and second dielectric layers is doped with at least one member selected from the group consisting of carbon, boron, phosphorous, hydrogen, and fluorine.

[0053] Example 1 1 includes the apparatus of example 10 wherein at least another of the first and second dielectric layers is doped with at least one member selected from the group consisting of carbon, boron, phosphorous, and fluorine.

[0054] Example 12 includes the apparatus of example 11 wherein the optically transmissive interconnect directly contacts the top surface of the second dielectric and the first LED directly contacts the top surface of the first dielectric layer.

[0055] Example 13 includes the apparatus of example 12 wherein an electrode of the first LED directly contacts the top surface of the first dielectric layer.

[0056] Example 14 includes the apparatus of example 13 wherein: the first dielectric layer includes a second portion between a first portion of the first dielectric layer and the substrate; the first portion of the first dielectric layer is annealed; the second portion of the first dielectric layer is not annealed.

[0057] Example 15 includes the apparatus of example 14 wherein: the second dielectric layer includes a second portion between a first portion of the second dielectric layer and the substrate; the first portion of the second dielectric layer is annealed; the second portion of the second dielectric layer is not annealed. [0058] Example 16 includes the apparatus of example 13 wherein the electrode includes a surface that directly contacts the top surface of the first dielectric layer and the surface of the electrode is not planarized and is rougher than the top surface of the first dielectric layer.

[0059] Example 17 includes the apparatus of example 7 comprising: a second LED on the top surface of the second dielectric layer a third dielectric layer including the second LED; wherein: (a)(i) the second LED is inorganic; (a)(ii) the third dielectric layer includes a bottom surface between a top surface of the third dielectric layer and the substrate; (a)(iii) the top surface of the third dielectric layer is planarized.

[0060] Example 18 includes the apparatus of example 17 comprising: a third LED on the top surface of the third dielectric layer a fourth dielectric layer including the third LED;

wherein: (a)(i) the third LED is inorganic; (a)(ii) the fourth dielectric layer includes a bottom surface between a top surface of the third dielectric layer and the substrate; (a)(iii) the top surface of the fourth dielectric layer is planarized; (a)(iv) the third and fourth dielectric layers are each doped with at least one member selected from the group consisting of carbon, boron, phosphorous, and fluorine.

[0061] Example 19 includes the apparatus of example 18 comprising: an optically transmissive interconnect that is on the top surface of the fourth dielectric layer and is coupled to each of the first, second, and third LEDs; an additional dielectric layer included between the first dielectric layer and the substrate; and a metal interconnect included between the first LED and the substrate; wherein: none of the first, second, third, and fourth dielectric layers are monolithic with each other; the substrate includes glass; the TFT, the first dielectric layer, and the substrate are all included in a TFT backplane; and the substrate includes a top surface that is greater than 1.0 x 1.0 m ² .

[0062] Thus, an embodiment may use a common-cathode arrangement.

[0063] Example 20 includes the apparatus of example 7 comprising a signal source configured to drive the TFT and the first LED with a digital drive pulse train.

[0064] Example 21 includes the apparatus of example 20 wherein the TFT is included in the first dielectric layer and the first LED includes a semiconductor crystal. [0065] Example 22 includes a crystalline LED display comprising the first and second dielectric layers according to any one of examples 1 to 21.

[0066] Example 23 includes a method comprising: forming a dielectric layer on a substrate; forming a thin film transistor (TFT) in the dielectric layer; forming a first dielectric layer on the TFT, the first dielectric layer including a bottom surface between a top surface of the first dielectric layer and the substrate; planarizing the top surface of the first dielectric layer without using chemical mechanical polishing (CMP); forming a metal interconnect that couples the TFT to the top surface of the first dielectric layer transferring a first light emitting diode (LED) onto the planarized top surface of the first dielectric layer; and forming a second dielectric layer including the first LED, the second dielectric layer including a bottom surface between a top surface of the second dielectric layer and the substrate; planarizing the top surface of the second dielectric layer without using CMP; and forming an optically transmissive interconnect on the planarized top surface of the second dielectric and coupling the optically transmissive interconnect to the first LED.

[0067] Example 24 includes the method of example 23 wherein planarizing the top surfaces of the first and second dielectric layers includes planarizing the top surfaces of the first and second dielectric layers using a method selected from the group consisting of microwave annealing and laser annealing.

[0068] Example 25 includes the method of example 24 comprising doping at least one of the first and second dielectric layers with at least one member selected from the group consisting of carbon, boron, phosphorous, hydrogen, and fluorine.

[0069] The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the "top" surface of that substrate; the substrate may actually be in any orientation so that a "top" side of a substrate may be lower than the "bottom" side in a standard terrestrial frame of reference and still fall within the meaning of the term "top." The term "on" as used herein (including in the claims) does not indicate that a first layer "on" a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.