Presently, there exists a variety of concepts how to design an input circuit with a large common mode range. The term common mode range is well-known in the art and relates to a range of signal levels, voltage or current, which are allowed to be simultaneously present at both inputs of a circuit for processing differential signals, without impairing the ability of the circuit to process the differential signals across its differential input terminals. A large common mode range is desirable for a variety of different circuits, including operational amplifiers, line receivers for receiving differential signals from a transmission line, and the like.

The ability to process differential signals over a large common mode range depends in particular on the design of the input stage of the circuit provided for receiving and processing the differential signals. The input stage design has to face the challenge of processing the differential input signals as independently as possible from the common mode level present at both inputs of the differential input stage. Particular demands arise in this respect if a circuit is expected to operate at high data rates. It is known in the art, to design an input circuit for receiving differential signals over a large common mode range by combining two or more amplifier stages, each having a different receiving window, that is a different common mode range over which the stage is able to operate. A common internal point in the input circuit is provided to sum up the various output signals of the amplifier stages, this summation point forming the output of the circuit. US 5,574, 401 to Spitalny proposes to provide an NMOS differential pair connected in parallel with a PMOS differential pair in order to enlarge the available common mode input signal range. US 6,081, 113 discloses a universal receiver circuit having two amplifier circuits connected in parallel, for receiving differential signals over a large common mode voltage range. Both amplifier stages comprise transistors of the same conductivity type. The first stage has a common source architecture for processing input signals over a higher common mode range, while the second stage is adapted to process the input signals over a lower common mode range partially overlapping with the higher common mode range, by means of a differential common gate architecture. Another example is known from US 6,236, 242 which discloses a first differential amplifier stage adapted to receive and process differential signals within a first common mode voltage range, and a second differential amplifier stage for receiving and processing differential signals in a second common mode voltage range.

Again, one of the amplifier stages is a differential common source amplifier operable in a higher common mode range, while the other amplifier stage has a common gate architecture for lower common mode levels.

US 5,414, 388 discloses an operational amplifier using a pair of differential input amplifier stages in order to enlarge the common mode range, each stage having a bipolar common emitter architecture, one stage being NPN, the other stage being PNP. US 2001/0004219 Al discloses a low voltage differential signal input circuit in order to solve problems associated with using bipolar differential circuits over a wide common mode voltage range. According to this document, two amplifiers are provided, one with a bipolar common emitter architecture and the other one with a bipolar common base architecture. A third and a fourth amplifier are provided with the objective to achieve a constant linear transfer characteristic over the full common mode range and especially over the amplifier transition region.

While these known input circuits offer a satisfactory performance and the ability to operate over an enlarged common mode range reaching from the lower power supply potential up to the higher power supply potential ("Rail- to-Rail"), there remains the desire to further improve the capabilities of an input circuit particularly when the differential input signals to be processed have a high data rate. In the known input circuit designs the input impedance depends on which of the respective input stages is presently active, because the dedicated input amplifier stages for the different common mode windows have particular electrical characteristics with respect to input impedance, speed and signal delay, which are not necessarily identical or at least similar for the two different input stages. The NMOS stage in US 5,990, 743 differs in this respect from the PMOS stage in the circuit known from that document. In US 6, 081, 133 and US 6,236, 242 the common source amplifier for the upper common mode range has electric characteristics different from those of the common gate amplifier provided for the lower common mode range. Also, the signal delay depends on whether one or the other or both input stages are presently active, this being particularly undesirable at high operating speeds.

From William J. Dally and John W Poulton, Digital Systems Engineering, Cambridge University Press, 1998 and from an Article in IEEE Journal of Solid-State Circuits, 28 (12), pages 1273-1282, December 1993:"Precise Delay Generation Using coupled Oscillators", high Speed differential current mode logic gates (CML) are known. These known gates are based on differential NMOS pairs with drain loads in the form of resistors or PMOS devices working in the resistive (saturated) region. The conventional CML gate comprises two NMOS devices connected as a differential common source pair, each drain being connected to a drain load forming the outputs of the circuit. The gates of the differential pair form the inputs, and the sources are connected to a common current source which is typically implemented as an NMOS device having its drain connected to the sources of the differential pair and having its source connected to the lower power supply potential. The gate of the common current source typically receives a reference voltage. The known CML gate works with a small differential amplitude close to the upper supply rail. However, the conventional CML gate will cease to operate when the common mode level reaches lower limits determined by the threshold voltage of the transistors in the differential pair and by the voltage required by the common current source. These lower limits are undesirably high.

The various concepts of input circuits discussed above, accordingly suffer from different shortcomings which will become more and more prominent with increasing operating speed and data rates. The known designs discussed above suffer from an impaired timing precision and signal resolution, due to the different electrical characteristics of the input stages dedicated to different common mode ranges. When one input stage takes over the operation from the other input stage, at high operating speeds this take over will be accompanied in the known designs by a change in signal timing and amplitude. Particularly when high operating speeds are envisaged, it would be desirable to alleviate these unwanted effects.

Summary of the Invention The present invention is defined in the appended claims.

Advantageous embodiments are defined in the dependent claims.

According to an embodiment of the present invention, an input circuit for receiving differential input signals may comprise two input stages designed such that at least selected signal processing characteristics of the two input stages are essentially similar. These selected electrical characteristics may comprise at least one of the following parameters: signal delay, signal amplification, input impedance, output impedance. The output signals of these input stages may be combined at a suitable summation point.

The input signals of at least one of the input stages may then be subjected to a common mode level shift. This leads to an increased total common mode range in which at least one of the two input stages is able to operate. Due to essentially similar electrical characteristics of the two input stages, there will be little timing distortion and/or other spurious effects when, during operation in a common mode level transition region, one input stage takes over from the other input stage. A similarity of at least selected electrical characteristics may be obtained by designing the two input stages to be of the same type of circuit, suitable circuit types comprising, but not being limited to, differential common source and differential common gate architectures as such known in the art.

Preferably, not only the type of circuit is the same for the two input stages but also at least selected design parameters like conductivity type, physical dimensions and the like, of the corresponding transistors.

Preferably, the operating current required by each of the two input stages is provided by a common current generator circuit, and a circuit is provided to distribute the current generated by the current generator, or at least a portion of that current, among the two input amplifier stages such that if one of the amplifiers gets more current, the other amplifier will get less. This distribution of current may depend on the common mode level of the differential input signal of the input circuit. This allows to achieve that an amplifier stage out of its common mode range will not contribute in an erroneous way to the output signal.

Preferably, the current provided by the common current generator circuit for distribution among the two input amplifier stages, is constant and essentially independent from the common mode level of the differential input signal. This is advantageous in that parameters like the signal delay in the input circuit and the output signal amplitude of the input circuit are then even less dependent on the common mode level of the differential signal. In this embodiment of the invention both input stages are preferably similar at least with respect to selected electrical characteristics, or even have an essentially similar design. Since the current provided by the common current generator circuit is shared among the two amplifier stages depending on the common mode level of the input signal, the signal amplitude at the summation point of the two amplifier stages will show little dependency of the amplitude and delay on the common mode level of the differential input signal.

The two input amplifier stages may be designed in accordance with the principles of differential common source amplifiers, and they may preferably be designed in differential CML style, each input stage having a differential pair of MOSFET devices, at least one input stage being preceded by a common mode level shifting circuit which may e. g. be formed by a pair of source followers. The two differential pairs share the current provided by a common current source, and an additional transistor device may be provided for determining the current sharing between the two differential pairs.

A pair of source followers may be adopted for embodying a common mode level shifting circuit, this being but one of a variety of different design options. Also, a pair of cascades of more than one source followers for each of the two inputs may be suitable for obtaining an even larger amount of shift. A pair of coupling capacitors connected across the gates and sources of the respective source followers or in case of cascades, across the first gate and the last source, may be advantageous in order to enhance the speed capabilities of the source follower stage. Due to the capacitive coupling, the signal delay caused by the source followers is almost negligible, even at very high operating speed. This has the advantage that the two parallel signal paths from the input of the input circuit to its output through the two input stages do not essentially differ in their signal delay properties, even if only one of the input stages is preceded by a common mode level shifting circuit, or if the common mode level shifting circuits provided in the two signal paths achieve different shifts.

Alternative arrangements for shifting the common mode level may comprise diodes or resistors in cooperation with constant current sources in order to achieve an offset of the input signal at each of the inputs constituting the differential input of the input circuit. Other designs which are similarly suitable for the purpose of shifting the common mode level, may be based on capacitors in the input signal path to the at least one of the two input stages, the capacitors being kept charged to provide an offset voltage which results in the common mode level shift. The skilled person will appreciate that there exists a large variety of design options all of which fulfil the purpose of providing a common mode level shift, and all of which are intended to be covered by the principles of the present invention.

An embodiment of the current distribution circuit which is advantageous due to its simplicity, comprises a transistor device the drain source path of which is connected between the current distribution point of the common current generator and the common source node of one of the two amplifier circuits. The common source node of the other amplifier circuit may be connected directly to the current distribution point of the common current generator circuit.

The gate of said transistor device receives a reference voltage which determines the input common mode level at which both amplifier stages receive the same share of operating current.

According to this embodiment, if the common mode level of the differential input signal is high, the amplifier which has its common source node connected to the current generator circuit, will receive essentially all the current provided by the common current source, due to the fact, that in this case the resulting high common source potential of this amplifier will cause the current distribution transistor in the common source path of the other amplifier stage to pinch off the source current to that amplifier stage. On the other hand, in case the common mode level of the differential input signal is low, the current distribution transistor will turn conductive due to its increased gate source voltage, such that the other of the two amplifier stages can turn active, which in this embodiment receives the differential input signal with a common mode level shifted upward by the common mode shifting circuit.

Other embodiments of a current distribution circuit may comprise a pinch off transistor for the other amplifier stage, or may comprise pinch off transistors in the common source current path of each of the two amplifier stages.

These pinch off transistors may receive different reference gate voltages, or may be driven by dedicated control circuitry which detects the common mode level at the input of the input circuit and controls the two pinch off transistors in a complementary fashion in accordance with the detected common mode level. This embodiment is advantageous in that it keeps the circuit architecture symmetrical, which will lead to a further improved independency of signal amplification and delay from the common mode level of the differential input signal, however for the price of slightly increased circuit complexity.

Another advantageous embodiment of the present invention includes a control circuit for controlling the signal amplitude of the output signal provided by the input circuit. This control circuit may advantageously be implemented using a replica of the load circuitry of the amplifier circuits, as well as a replica of at least one of the branches of at least one of the common source amplifiers of the source input circuit, as well as a replica of the current generator circuit. According to this embodiment, these replicas are connected in series, and the voltage drop across the load replica is detected and compared against a reference voltage. A deviation of the voltage drop across the load replica from the reference voltage is amplified by a control amplifier which provides a control signal for the current generator replica in order to operate towards a reduction of any deviation that occurs. The control signal for controlling the current generator replica may then be used to furthermore control the current generator circuit which supplies the amplifier stages with current.

Preferably, a voltage mirror circuit detects the voltage across the current generator circuit which may vary depending on the present common mode level of the differential input signal, and provides a corresponding voltage across the current generator replica. This embodiment is particularly advantageous when the current source generator is embodied simply by a MOSFET transistor operated in the non-saturated region.

It will be appreciated that other design options for the current generator circuit are readily available. Designing the current generator circuit as a cascode may be a suitable alternative or supplement to adopting a voltage mirror circuit. The larger minimum operating voltage required by the cascode can be compensated by means of appropriately selecting the amount of shift provided by the common mode level shifting circuit.

The output of the input circuit may be differential or single-terminal (non-differential). Subsequent stages may be provided to follow the differential input stage in order to increase the differential signal amplification of the entire circuit. These subsequent stages may be embodied in the form of differential CML gates (current mode logic).

The input circuit according to the present invention is suitable for a large variety of applications, including analogue and digital line receiver circuits, operational amplifiers, comparators and the like, where a large common mode range with little or no delay and/or amplitude variations over the entire common mode range are desired.

In the following, advantageous embodiments of the present invention will be described with reference to the accompanying drawings. It is to be understood that the embodiments described in the present application are advantageous examples of implementing the present invention, while these examples should not be construed as limiting the scope of the present invention in any way.

Fig. 1 shows a first embodiment of an input circuit according to the present invention; Fig. 2 shows a second embodiment of an input circuit according to the present invention; Fig. 3 shows a third embodiment of an input circuit according to the present invention; Fig. 4 shows a first embodiment of a signal amplitude control circuit which may advantageously be used in conjunction with or to supplement any of the input circuit embodiments herein described; Fig. 5 shows a second embodiment of a signal amplitude control circuit which may advantageously be used in conjunction with or to supplement any of the embodiments of an input circuit herein described; and Fig. 6 shows a third embodiment of a signal amplitude control circuit which may advantageously be used in conjunction with or to supplement any of the embodiments of an input circuit herein described.

Fig. 1 shows a first embodiment of an input circuit for receiving a differential input signal in accordance with the present'invention. In this figure, reference numeral 1 denotes a load circuit. Reference numerals 2 and 3 each denote an input amplifier stage, each stage in this embodiment having a differential common source amplifier circuit, each of the differential source amplifier circuits comprising a pair of transistor devices having their sources tied together, in order to constitute a common source node denoted CS2 and CS3, respectively. The two amplifier circuits have essentially similar electrical characteristics, and preferably a similar design to achieve this. Reference numeral 4 denotes a common mode shifting circuit. 5 denotes a current distribution circuit. 6 denotes a current generator circuit for providing a current labelled 16 in Fig. 1. Vd and GND, respectively, denote power supply terminals for providing the input circuit with a power supply voltage. InP and InN, respectively, denote the differential input terminals of the input circuit.

These terminals are provided to receive a differential input signal for processing by the input circuit. SP and SN denote output terminals of the common mode shifting circuit 4.

The input terminals InP and InN are connected with the input of the common mode shifting circuit 4. These input terminals are furthermore connected with the differential input of the differential common source amplifier circuit 3. In the embodiment shown in Fig. 1, these inputs are constituted by the gates of the differential transistor pair of the amplifier 3. The output SP, SN of the common mode shifting circuit 4 is connected with the differential input of the differential common source amplifier circuit 2. The current generator 6 provide the current I6, i. e. sinks or sources this current, to the current distribution circuit 5 which, therefore, is appropriately connected with the current generator circuit 6. Shares of the current I6, or at least of a portion of that current 16, are distributed by the current distribution circuit 5 to first and second terminals of the current distribution circuit 5 which are connected with the common source node CS3 and CS2, respectively, of the first and second amplifier circuits. The current distribution terminals of the current distribution circuit 5 will be referred to as outputs in the following, even if strictly speaking in accordance with the convention, these terminals act as current inputs.

Also, the terminal of the current distribution circuit 5 which is connected with the current generator circuit 6, will be called input of the current distribution circuit 5 in the following, even if strictly speaking, this terminal is a current output, based on the convention that current is shown to flow from the upper power supply potential VD to the lower power supply potential GND.

The signal available at the output SP of the common mode shifting circuit 4 corresponds to the signal available at the input InP, but has a DC offset relative to the signal at InP. Similarly, the signal at the output SN of the common mode shifting circuit 4 corresponds to the signal at the input terminal InN and has a similar DC offset as the positive branch SP. In this way, the common mode shifting circuit providing these offsets achieves a shift of the common mode level at the differential output SP, SN of the circuit 4.

The drain of that transistor in the first amplifier circuit 3 which receives at its gate the signal InN, and the drain of that transistor in the second amplifier circuit 2 which receives at its gate the signal SN, are connected together and connected to a terminal of the load circuit 1, the resulting node constituting the output OUT of the input circuit. Although not shown in Fig. 1, a further load circuit may be provided, with one of the terminals of this further load circuit being connected with the drains of the transistors of the amplifier circuit 2 and 3, the gates of which receive the signal SP and InP, respectively, the resulting node constituting an output terminal complementary to the output terminals OUT shown in Fig. 1.

In this way, a differential output can be implemented. If a differential output is not required then it can be sufficient to simply couple the drains shown dashed, to VD.

In operation, the embodiment shown in Fig. 1 receives differential input signals at the input terminals InP and InN. This differential input signal is taken by the common mode shifting circuit 4 to provide a differential signal at SP, SN which corresponds to the input signal but has a shifted common mode level with respect to the differential input signal. Depending on the common mode level at the differential input InP, InN, the current distribution circuit 5 distributes the current 16 from the current generator circuit 6 among the two differential common source amplifier circuits 2,3 such that in a higher common mode level range of the received differential signals, at least a major portion of the current 16 flows into one of the amplifiers 2,3 while in a lower common mode level range at least a major portion of the current flows into the other of the two amplifiers 2,3. If the common mode shifting circuit 4 elevates the common mode level, amplifier 3 will receive a major portion of the current 16 in the higher common mode level range while amplifier 2 will receive at least a major portion of the current E6 when the input signal is in the lower common mode level range. In this embodiment, the output amplitude above the drain load 1 will be fairly constant and independent of which of the amplifiers 2,3 are presently active, as long as the current 16 from the current generator 16 is constant, even in a transition region for such common mode levels of the differential input signals, for which both amplifiers 2 and 3 are active simultaneously.

In case the common mode shifting circuit 4 is designed to lower the common mode level, in the higher common mode range of the differential input signal across InP, InN the amplifier 2 will receive at least a major portion of the current 16 while in a lower common mode range, the amplifier 3 will receive at least a major portion of the current E6.

Fig. 2 shows a second embodiment of an input circuit according to the present invention. In this Fig. , reference numerals similar to Fig. 1 denote similar or corresponding elements, such that with respect to these elements reference can be made to the description of Fig. 1 in order to avoid repetitions. In the embodiment of Fig. 2, reference numeral N61 denotes an NMOS transistor, the source of which is connected to ground and the gate of which is connected to receive a gate voltage V1. N31 and N32 denote NMOS transistors which are connected to constitute a differential common source amplifier circuit.

To this end, the sources of the two transistors N31, N32 are connected together to constitute a common source node CS3. This node is connected to the drain of transistor N61.

The gate of transistor N31 is connected with the input terminal InP while the gate of transistor N32 is connected to the input terminal InN of the input circuit. N21 and N22 constitute a further differential common source amplifier.

The sources of the transistors N21 and N22 are connected together to constitute a common source node CS2. N52 denotes an NMOS transistor, the drain of which is connected to CS2 and the source of which is connected with the drain of transistor N61. The drains of the transistors N21 and N31 are connected together and through the drain source path of a PMOS transistor P11 with the upper power supply potential VD. The drains of the transistors N22, N32 are connected together, and through the drain source path of a PMOS transistor P12 to VD. The gates of the two PMOS transistors P11, P12 are both connected to the lower power supply potential GND. The node constituted by the drains of the transistors N21, N31 and P11 constitutes a first output terminal OUTP while the node constituted by the drains of the transistor N22, N32 and P12 constitutes a second output terminal OUTN, the terminals OUTP and OUTN constituting the differential output of the input circuit shown in Fig. 2.

P43 and P44 denote PMOS transistors, the drains of which are connected to ground. The gate of P43 is connected with the input terminal InP while the gate of PMOS transistor P44 is connected with the input terminal InN. C41 denotes a capacitance connected across the gate and source of PMOS transistor P43 while C42 denotes a capacitance connected across the gate and source of PMOS transistor P44. The source of transistor P43 is connected with the drain of a PMOS transistor P41 the source of which is connected VD.

The source of transistor P44 is connected with the drain of a PMOS transistor P42 the source of which is connected to VD. The source of transistor P43 is connected with the gate of transistor N21 while the source of transistor P44 is connected with the gate of transistor N22. P51 denotes a PMOS transistor the source of which is connected to VD and the drain of which is connected to the drain and gate of an NMOS transistor N52, and furthermore to the gate of transistor N51. The source of transistor N52 receives a reference voltage V2. The gates of the transistor P41, P42 and P51 receive a reference voltage V3.

In this embodiment shown in Fig. 2, the transistors N31 and N32 constitute a first differential common source amplifier while the transistors N21, N22 constitute a second differential common source amplifier. The second differential common source amplifier in this embodiment receives input signals SP, SN from a common mode shifting circuit for elevating the common mode level which is constituted by the transistors P41 to P44 and the capacitances C41, C42. The input of this common mode shifting circuit is constituted by the gates of the transistors P43, P44. The transistors P41, P42 constitute load devices for the transistors P43, P44 which operate as respective source followers. To this end, the reference voltage V3 at the gates of the transistors P41, P42 serves to turn these devices conductive. V3 can be the ground potential GND or can be obtained from a known current mirror circuit which is conventionally used for setting the operating point of load devices. Transistor P11 constitutes a drain load for combining the currents through the transistors N21, N31. Similarly, transistor P12 constitutes a second drain load for combining the drain currents of the transistor N22, N32. Transistor N51 in cooperation with the transistors P51, N52 constitutes simple yet efficient current distribution circuit which exploits the fact that the drain potential of transistor N61 depends on the common mode potential at the differential input InP, InN of the Input circuit. When a reference voltage V2 is applied to the source of transistor N52, a voltage will appear at the drain of N52 which is about VT (a threshold voltage) higher than the reference voltage V2. Due to the fact that transistor N51 needs about VT across drain and source to turn conductive, it is readily apparent that the reference voltage V2 determines that voltage level at the drain of transistor N61 below which the transistor N51 is able to turn conductive, and above which the transistor N51 will turn non-conductive. This behaviour is exploited for distributing the current among the two differential common source amplifiers N21, N22 and N31, N32, as will be explained in the following. P51 serves to provide an operating current for transistor N52.

In order to explain the operation of the embodiment shown in Fig. 2, the case will be considered that the common mode level at the differential input InP, InN gradually changes from the upper limit of the input common mode range to the lower limit. To begin with the upper common mode level limit, this limit is reached when there is no more"head room"for the transistors N31 in series connection with P11 on the one hand and transistor N32 in series connection with transistor P12 on the other hand, to operate. At very large common mode levels at the gates of transistor N31 and N32, the common source node CS3 will reach such a high potential that the difference between VD and the potential at CS3 is no longer large enough for the transistors N31 and N32 to operate as a differential amplifier. The high potential of CS3 will turn transistor N51 non-conductive such that essentially no current provided by the current generator circuit embodied by transistor N61 and the associated circuitry for providing the voltage V1, flows through the amplifier N21, N22. Rather, in this operating region essentially all the current provided by N61 flows through the amplifier N31, N32. With the input common mode level decreasing, this situation will prevail until the node CS3 and the source of transistor N51 reaches a potential where the transistor N51 begins to turn conductive. As explained above, this will happen at a common mode level at the input InP, InN of about V2 + VT, VT being the threshold voltage across the gate and source of the transistors N31, N32. Once the transistor N51 turns conductive, the amplifier N21, N22 begins to take over some of the current previously flowing through the amplifier N31, N32. As long as the current provided by the current generator circuit N61 is independent from the common mode level at the input InP, InN and the potential at the node CS3, which would be the case for N61 being ideal, this transition from the first amplifier N31, N32 to the second amplifier N21, N22 will not have any significant impact on the output amplitude of the circuit, due to the fact that the current through the corresponding branches of the two amplifiers are combined into a single load element P11 and P12, respectively. The shifted common mode level at SP, SN of the second amplifier results in a corresponding drain source voltage across N51 such that the operating points of the two amplifiers are essentially similar. Accordingly, even in this transition region of the common level the behaviour of the two amplifiers will be essentially similar and adverse timing differences between the two amplifiers which result in a signal dispersion at high operating speed, as well as amplitude variations at the output of the input circuit can be avoided or at least alleviated quite effectively.

With the common mode level at the input decreasing further, the drain potential of transistor N61 will now remain at about the level of V2 due to the action of transistor N51 which now functions as a source follower. The potential at node CS3 will accordingly no longer follow the decreasing common mode level at the input InP, InN such that the first amplifier N31, N32 will essentially cease to operate, i. e. the transistors N31, N32 turn non-conductive. Due to the common mode shifting circuit, which in this embodiment elevates the common mode level of the differential input signal, in this lower common mode range the second amplifier N21, N22 is able to continue its operation to amplify the differential signals at the input InP, InN. In this state, all the current provided by the current generator N61 will flow through transistor N51 into the second amplifier N21, N22 while essentially no current flows through the first amplifier N31, N32. The common mode shifting circuit makes it possible to extend the common mode level operating range to values around or even below the ground potential GND, by appropriately selecting the potential V2 at the source of transistor N52, the selection of which depends on the amount of shift provided by the common mode level shifting circuit. If transistor N61 is chosen to have a large Early voltage, V1 may be a constant reference voltage which determines the constant current provided by N61.

Fig. 3 shows a third embodiment of an input circuit according to the present invention. In Fig. 3, elements similar or corresponding to elements shown in Fig. 2, have been denoted with the same reference numerals and with respect to these elements, reference is made to the description given in conjunction with Fig. 2 in order to avoid repetitions.

The input circuit according to the embodiment shown in Fig.

3 has a first common mode level shifting circuit constituted by the elements P41 to P44 and C41, C42 which have already been described in detail in conjunction with Fig. 2. The input circuit of Fig. 3 furthermore comprises a second common mode level shifting circuit constituted by the elements N41 to N44 and C43, C44. While the first common mode level shifting circuit is designed to elevate the common mode level of the differential signals received at the input terminals InP, InN of the input circuit, the second common mode level shifting circuit is provided for lowering the common mode level of the differential input signals received at InP, InN. The differential output SP1, SN1 of the first common mode level shifting circuit is connected with the differential input of the differential common source amplifier N21, N22 while the differential output SP2, SN2 of the second common mode level shifting circuit is connected with the differential input of the differential common source amplifier N31, N32.

The NMOS transistors N41 and N42 have their drains connected together and with the upper power supply potential VD. The gate of transistor N41 is connected with the positive terminal InP of the differential input of the input circuit, while the gate of transistor N42 is connected with the negative terminal InN of the differential input of the input circuit. The source of transistor N41 constitutes the positive output terminal SP2 of the second common mode level shifting circuit, and is connected with the gate of transistor N31. Similarly, the source of transistor N42 constitutes the negative output SN2 of the second common mode level shifting circuit and is connected with the gate of transistor N32. The source of transistor 41 is connected with the drain of transistor N43. The source of transistor N43 is connected to GND. The source of transistor N42 is furthermore connected with the drain of transistor N44. The source of transistor N44 is connected to GND. The gates of the transistors N43 and N44 are connected to receive a reference voltage V5 to turn the transistors N43 and N44 conductive. The reference voltage V5 is preferably selected such that the transistors N43 and N44 operate in the non-saturated region. V5 can be the upper power supply potential VD or can be obtained from a known current mirror circuit for setting the operating point of those transistors which constitute a source load for the source followers N41 and N42. The capacitive element C43 is connected across the gate and the source of transistor N41 while the capacitive element C44 is connected across the gate and the source of transistor N42.

In the embodiment shown in Fig. 3, reference numerals R61 and R62 denote a series connection of resistive elements which constitute a circuit for detecting the common mode level at the differential input InP, InN of the input circuit. Reference numeral Al denotes an operational amplifier having a negative input terminal connected to receive a reference voltage V6, and a positive input terminal connected with the node between the resistive elements R61 and R62 to receive a signal corresponding to the common mode level at the differential input InP, InN.

The amplifier Al furthermore has a pair of differential output terminals which are connected to control the current distribution circuit of the input circuit in a differential fashion.

In the embodiment of Fig. 3, the current distribution circuit comprises a first NMOS transistor N53 the source of which is connected to the drain of transistor N61. The drain of transistor N53 is connected with the common source node CS2 of the differential amplifier N21, N22. The current distribution circuit furthermore comprises a second NMOS transistor N54 the source of which is connected with the drain of transistor N61. The drain of transistor N54 is connected with the common source node CS3 of the differential amplifier N31, N32. The gate of transistor N53 is connected with one of the two differential output terminals of amplifier Al, while the gate of transistor N54 is connected with the other one of the two differential output terminals of amplifier Al. Specifically, in the embodiment shown in Fig. 5, the gate of transistor N53 is connected with the negative output terminal of the amplifier Al, while the gate of transistor N54 is connected with the positive output terminal of transistor Al. It will be appreciated by those skilled in the art, that the differential amplifier Al can be connected in a variety of different ways, all of which are intended to be included in the scope of this embodiment. For instance, if the positive input terminal of the amplifier Al is used as the input for the reference voltage V6 and the negative input terminal is connected to the common mode level detection circuit R61, R62, then the gate of transistor N53 should be connected to the positive output terminal of amplifier Al rather than the negative output terminal, while the gate of transistor N54 should in this case be connected to the positive output terminal of amplifier Al rather than the negative output terminal. The amplifier Al is a low gain amplifier with a differential gain preferably in the order of 1 to 5. The differential amplifier Al can be any kind of differential amplifier per se well known to those skilled in the art, with a conventional resistive feed back network to control the differential gain of the amplifier.

In operation, the two common mode level shifting circuits of this embodiment contribute to extending the input common mode range of the input circuit of this embodiment. In order to explain the operation of the embodiment shown in Fig. 3, the case will be considered that the common mode level at the differential input InP, InN gradually changes from the upper limit of the input common mode range to the lower limit. To begin with the upper common mode level limit, this limit is reached when the differential amplifier N31, N32 receiving the differential input signals at a common mode level lowered by the operation of the second common mode level shifting circuit N41 to N44 and T43, T44, ceases to operate. This will happen when the voltage at the common source node CS3 of this amplifier has reached a level such that there is not enough operating voltage left for the transistors N31 in series connection with P11 on the one hand, and transistor N32 in series connection with transistor P12 on the other hand, to operate as a differential amplifier. In the upper range of the input common mode level, the amplifier Al will control the transistors N53 and N54 such that N54 will be conductive while N53 is non-conductive. Accordingly, in this input common mode region the amplifier N31, N32 will take essentially all of the current I6 while the amplifier circuit N21, N22 will receive essentially no share of the current I6, such that this differential amplifier will not have an adverse effect on the operation of the input circuit.

With the common mode level decreasing, this situation will prevail until the input common mode level approaches the reference potential V6. At this stage, the amplifier Al will gradually turn off transistor N54 by lowering the potential at the gate of N54, and at the same time gradually turn on the transistor N53 by increasing the potential at the gate of N53. The reference potential V6 defines that input common mode level for which the amplifier Al provides the transistors N53 and N54 with equal gate voltages. This is approximately that point where the two differential common source amplifiers N21, N22 and N31, N32 receive about the same share of the current I6.

Due to the different common mode levels at the differential inputs of these two amplifiers, the drain source voltages of the two transistors N53 and N54 will be different, this resulting in a slight shift of that input common mode level, where the two differential common source amplifiers receive exactly the same share of the current I6, from the reference voltage V6, this deviation being, however, negligible from a practical point of view. In this middle range of input common mode levels, both differential source amplifiers N21, N22 and N31, N32 will contribute to the output signal across the output terminal OutN and OutP of the input circuit. With the input common mode level decreasing further, the operational amplifier Al will eventually cause the transistor N53 to fully turn on while the transistor N54 is controlled by the amplifier Al to fully turn off. In this lower region of the common mode operating range of the input circuit, the differential common source amplifier N31, N32 will, therefore, no longer contribute to the differential output signal across OutN, OutP because this differential common source amplifier does not receive any substantial share of the current I6. The lower limit of the input common mode operating range is reached when the gate source voltages of the transistors N21, N22 become to low to turn these transistors conductive, or when the potential at the drain of transistor N61 drops to a level where this transistor can no longer operate as a current generator.

The embodiment of an input circuit according to Fig. 3 offers a large input common mode range which can extend from the lower power supply potential or even below, to the upper power supply potential or even above ("rail-to- rail"). Since the circuit architecture is symmetrical, the behaviour of the two differential common source amplifiers will be essentially similar, and adverse timing differences between the two amplifiers which would result in a signal dispersion at high operating speed, as well as amplitude variations at the output of the input circuit can be kept very small.

The reference voltage V6 can be generated e. g. by means of using a voltage divider circuit consisting of a series connection of resistive elements. Of course, the variety of different circuits for generating a reference voltage is known to those skilled in the art, and all these variants are intended to be included in the scope of this embodiment. The reference voltage V6 can have a level of about half the supply voltage. If for some reason, it is desired to place the transition region of the input common mode level range, where one of the differential common source amplifiers gradually ceases to operated while the other one gradually takes over, at a level different from half the supply voltage, this can be achieved easily in this embodiment by means of appropriately selecting the level of V6- Figure 4 shows a first embodiment of a signal amplitude control circuit 7 which may advantageously be used in conjunction with any of the input circuit embodiments herein described. The circuit of Fig. 4 allows to adjust the maximum output signal amplitude of the input circuit and to keep the output signal amplitude to a large extent independent from parameter variations of the devices in the circuit. In Figure 4, elements similar or corresponding to elements shown in the preceding figures, have been denoted with the same reference numerals such that with respect to these elements, reference can be made to the description already given above. Reference numeral A2 denotes an operational amplifier having a positive input, a negative input and an output. Reference numerals R1 and R2 denote resistive elements like resistors, which are connected in series to constitute a voltage divider in order to provide a reference voltage V4. The series connection of these two resistive elements R1 and R2 is connected between the upper power supply node VD and the lower power supply node GND.

The node connecting R1 and R2 is furthermore connected to the negative input of the operational amplifier A2 to receive the reference voltage V4. Of course, any circuit for generating a reference voltage V4 may be used instead of the series connection of resistors shown in fig. 4, and all such alternatives are intended to be included in the scope of this embodiment.

Reference numeral 61 denotes a current generator circuit having a current level control terminal which is connected to the output of the operational amplifier A2 such that the output of the operational amplifier A2 can provide a control voltage V1 for controlling the level of the current I6'of the current generator circuit 61. This current generator circuit preferably has a design similar to the current generator circuit 6 in the input circuit, embodiments of which have been described above. N71 denotes an NMOS transistor, the source of which is connected to receive current from the current generator circuit 61, and the gate of which is connected to turn the transistor N71 conductive. A connection of the gate of N71 to the positive power supply potential VD is suitable for this purpose. The drain of transistor N71 is connected with the positive input of the operational amplifier A2. Reference numeral 16 denotes a load circuit which is connected between the drain of transistor N71 and the upper power supply potential VD.

In this embodiment, the load circuit 16 is preferably designed to be similar to the load circuit 1 provided in the input circuit. Embodiments of the load circuit 1 have been described above. It is well known in the art of semiconductor technology that while it can sometimes be difficult to achieve specified electrical characteristics with sufficient precision, a plurality of replica elements or circuits with essentially identical electrical characteristics can be obtained simply by manufacturing them in the same manufacturing process under the same manufacturing conditions. In this embodiment, the current generator circuit 61 preferably is a replica circuit of the current generator circuit 6 in the input circuit.

Similarly, the NMOS transistor 71 preferably is a replica of the transistors constituting the differential amplifier circuits 2 and 3 in the input circuit. This transistor has its gate connected to turn the transistor conductive, in order to take account of the operating conditions of the transistors in the differential amplifiers 2 and 3. Also, the load circuit 16 preferably is a replica of the load circuit 1 in the input circuit.

In operation, the operational amplifier A2 receives at its negative input a reference voltage V4. The operational amplifier A2 controls the current generator 61 by means of appropriately adjusting the current level control signal V such that the voltage VA occurring at the node connecting the load circuit 16 to transistor N71, corresponds to the reference voltage V4. Accordingly, the signal amplitude control circuit 7 shown in Fig. 4 is suitable for controlling the voltage drop across the load circuit 16 to take a given value determined by the reference voltage V4, by appropriately adjusting the current generated by the current generator 61, taking into account the influence of the transistor N71 and the load circuit 16 on the operating point of the current generator circuit 61. If the load circuit 16, the transistor N71 and the current generator 61 in Fig. 4 have electrical characteristics similar to, or even are replicas of the load 1, the amplifier transistor of one of the branches of the differential amplifiers 2,3 and of the current generator 6, respectively, of the input circuit, the reference voltage V1 can furthermore be applied to control the current generator circuit 6 of the input circuit to generate a current at a level which will lead to a signal amplitude across the load 1 corresponding to the voltage drop across the load replica 16 in Fig. 4.

This voltage drop in turn corresponds to the reference voltage V4, such that when adopting a signal amplitude control circuit 7 according to the embodiment of Fig. 4, the signal amplitude across the load 1 of the input circuit can be adjusted in accordance with the reference voltage V4. While a control of the output signal amplitude across OutP, OutN of the input circuit can be achieved in a variety of alternative ways, for instance by detecting the actual output signal amplitude and adjusting the current level provided by the current generator circuit 6 in accordance with a deviation of the detected output signal amplitude from a desired level, the embodiment of a signal amplitude control circuit shown in Fig. 4 has the particular advantage that a direct interaction to measure the output signal across OutP, OutN for the purpose of signal amplitude control can be avoided. Nevertheless, it is intended that alternative arrangements for output signal amplitude control, as well as no signal amplitude control at all, are included in the scope of the present invention.

Figure 5 shows a second embodiment of an amplitude control circuit which may advantageously be used with any of the embodiments of an input circuit herein described, and which is particularly suitable in conjunction with the embodiments of an input circuit shown in Fig. 2 and in Fig.

3. In Fig. 5, elements similar or corresponding to elements shown in the preceding figures have been denoted with the same reference numerals such that with respect to these elements, reference can be made to the description of the preceding figures. In Fig. 5, reference numeral P71 denotes a PMOS transistor, the source of which is connected to the upper power supply potential VD and the gate of which is connected to turn transistor P71 conductive, e. g. by means of connecting the gate of transistor P71 to the lower power supply potential GND. The drain of transistor P71 is connected to the drain of an NMOS transistor N71. The source of transistor N71 is connected to the drain of an NMOS transistor N72. The source of transistor N72 is connected to GND. The gate of transistor N71 is connected to the upper power supply potential VD in order to turn this transistor conductive.

The NMOS transistor devices N70, N75 to N77 and N80 as well as the PMOS transistors P73, P74, P78 and P79 are connected to constitute an operational amplifier A2. While this is a suitable embodiment of the operational amplifier A2, it has to be noted that there exists a large variety of other suitable amplifier designs all of which can be used to achieve essentially the same purpose and function, and all of which are, therefore, intended to be covered by the scope of the present invention. In the embodiment shown in figure 5, transistor N77 has its source connected to ground and its drain connected with the sources of the transistors N75 and N76. The gate of transistor N77 is connected to the upper power supply potential VD or any other reference potential suitable for turning transistor N77 conductive to operate in the non-saturated region. The drain of transistor N75 is connected with the gate and the drain of transistor P73, the source of which is connected to VD.

Similarly, the drain of transistor N76 is connected with the source and the gate of transistor P74, the source of which is connected to VD. The gate of transistor N75 constitutes the inverting input of the operational amplifier A2 and is connected with a circuit for generating a reference voltage V4 which can be a series connection of resistive elements as shown e. g. in Fig. 4, or any other suitable reference voltage generator circuit per se well known in the art. The gate of transistor N76 constitutes the positive input of the operational amplifier A2. This gate is connected with the drain of transistor P71 and the drain of transistor N71.

The source of transistor P78 and the source of transistor P79 are connected to VD. The gate of transistor P78 is connected with the drain and the gate of transistor P73 to constitute a current mirror circuit with transistor P73.

Similarly, the gate of transistor P79 is connected with the drain and the gate of transistor P74 to constitute a current mirror circuit with transistor P74. The drain of transistor P78 is connected with the drain and gate of transistor N80 and the gate of transistor N70. The drain of transistor P79 is connected to the drain of transistor N70.

This node constitutes the output of the operational amplifier A2 which is connected to the gate of transistor N72. Transistor N81 is connected to constitute a capacitive element for reducing serious noise signals at the output of the operational amplifier A2. To this end, the gate of transistor N81 is connected with the drains of the transistors P79 and N70 while the channel terminals of transistor N81 are connected to GND.

In the embodiment of Fig. 5, transistor P71 is a replica of the load elements P11, P12 of the input circuit examples of which are shown in Fig. 2 and Fig. 3 described further below. N71 is a replica of one of the transistors N21, N22, N31, N32 in the embodiments of Fig. 2 or Fig. 3. Transistor N72 is a replica of transistor N61 of the input circuit shown in Fig. 2 or Fig. 3. Transistor P71 constitutes a load replica while transistor N72 constitutes a current generator replica.

In operation, the operational amplifier A2 operates in accordance with the principles described in conjunction with Fig. 4 above. Specifically, transistor N77 provides an operating current for the differential input stage N75, N76 of the operational amplifier A2. The current mirror circuit P73, P78 acts to mirror the drain current of transistor N75 into the drain of transistor N80. Transistors P79 and N70 constitute a complementary push pull stage for generating the output signal V1, the upper transistor P79 being driven in accordance with the current through transistor N76 while the lower transistor N70 is driven in accordance with the current through transistor N75.

Similar to the embodiments described in connection with Fig. 4, the operational amplifier A2 of Fig. 5 operates to adjust the current through the current generator replica N72 such that the voltage drop across P71 constituting a replica of the load circuit of the input circuit, corresponds to the reference voltage V4 at the negative input of the operational amplifier A2. The output of the amplifier A2 is connected to control the current level of the current generator circuit embodied by transistor N61 in the embodiments shown in Fig. 2 and Fig. 3. If the transistors N72 and N61 are replicas and operate in the non-saturated region, the current 16 generated by the current generator circuit of the input circuit will correspond to the current through the current generator replica N72 in Fig. 5, such that the signal amplitude across the load elements Pll, P12 of the input circuit can be adjusted in accordance with the reference voltage V4 at the negative input of the operational amplifier A2.

When adapting the control circuit shown in Fig. 5, the output signal amplitude of the input circuit will be largely independent from the device parameter variations occurring during manufacture.

Fig. 6 shows a third embodiment of a signal amplitude control circuit 7 which may advantageously be used in conjunction with any of the input circuit embodiments herein described. In Fig. 6, elements similar or corresponding to elements shown in the preceding figures, have been denoted with the same reference numerals, such that with respect to these elements, reference can be made to the description already given above. The embodiment of Fig. 6 is particularly advantageous in that it can suppress or at least reduce a dependency of the differential output signal amplitude across the output terminals OutP, OutN of the input circuit from the common mode level of the differential input signals at InP, InN. A cause of such unwanted dependency can be the fact, that it is impossible to design a current generator circuit 6 which provides a current at a level entirely independent from the operating voltage across the current generator circuit. This dependency of the current I6 on the voltage across the current generator circuit is particularly prominent when a simple design for the current generator circuit 6 is adopted, which essentially consists of a single transistor operating in the non-saturated region, compare transistor N61 in the embodiments of Figs. 2 and 3. The drain current of transistor N61 in these embodiments will not only depend on the gate voltage V1 for controlling the current level, but also on the drain source voltage of this transistor.

This voltage in turn depends to some extent on the common mode level of the input signal across InN, InP, as explained above. Since the current I6 influences the output signal amplitude across OutP, OutN, as explained above, this may lead to an unwanted dependency of the output signal amplitude from the common mode level of the input signal. While it may be sufficient and fully in accordance with the principles of the invention, to design the current generator circuit 6 such that there is little dependency of the current I6 on the operating voltage across the current generator circuit 6, which can be achieved e. g. by means of selecting transistor N61 in Fig. 2 to have a high Early voltage, or by means of adopting a well-known cascode circuit, the embodiment of Fig. 6 allows to further improve output signal amplitude control of the input circuit according to the present invention.

To achieve this, the embodiment of Fig. 6 is adapted to detect the actual operating voltage across the current generator circuit 6, and to mirror that voltage to appear across the current generator circuit replica in the output signal amplitude control circuit. In Fig. 6, reference numeral 7 denotes a current source for generating a current 17. This current is preferably small in comparison with the current I6 generated by the current generator circuit 6.

Reference numeral N73 denotes an NMOS transistor having its gate and drain connected together and to the output of the current generator circuit 7. The other terminal of the current generator circuit 7 is connected to the upper power supply potential VD. The source of transistor N73 is connected to the output terminal of the current generator circuit 6. In the embodiment shown in Fig. 2, this is the drain of transistor N61. The gate of transistor N71 which is a replica of one of the transistors constituting the differential common source amplifiers in the input circuit, is connected with the gate and drain of transistor N73. The current generator 7 can be simply a resistive element, or can be any kind of constant current circuit well known in the art, e. g. a part of a current mirror or a cascode design. All these design alternatives fulfil the purpose of the current generator 7, to provide transistor N73 with operating current, and all these various designs are intended to be included in the scope of the embodiment shown in Fig. 6. The other elements shown in Fig. 6 have already been described in conjunction with the Figs. 4 and 5.

In operation, the source of transistor N73 will be at the same potential as the operating voltage of the current course generator 6, which is the potential of the drain of transistor N61 in the embodiment of Fig. 2 or Fig. 3. The current generator circuit 7 will cause the transistor N73 to turn conductive, the gate of transistor N73 having a potential by VT higher than the source potential of N73, VT denoting the threshold voltage of N73. This is also approximately the gate potential of transistor N71, at the source of which a potential appears which is about the same as the potential at the output of the current source generator 6, to which the source of N73 is connected.

Accordingly, the drain source voltage of transistor N72 will correspond to the operating voltage across the current source generator 6. In this way, the control loop shown in Fig. 6 for controlling the voltage drop across source and drain of transistor P71 can take into account the actual operating condition of the current generator 6 of the input circuit, that is transistor N61 in the embodiments of the Figs. 2 and 3, when generating the current level control voltage V1.

Accordingly, when adopting the control circuit shown in Fig. 6, the output signal amplitude of the input circuit will not only be largely independent from device parameter variations, but also to a large extent independent from the common mode level across the input terminals InP, InN of the input circuit, even if the current generator circuit 6 has a simple design and shows a pronounced dependency of the current I6 from the operating voltage across the current generator circuit 6.

While advantageous embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the particular embodiments shown and described. While the embodiment of fig. 2 has a common mode level shifting circuit for elevating the common mode level of the input signal, an alternative arrangement may instead have a common mode level shifting circuit for lowering the common mode level of the input signal. While the shown embodiments comprise differential amplifier circuits having a differential pair of N type transistors, a P type design or bipolar designs are similarly possible. An input circuit according to the present invention can be useful as a front end e. g. in line receiver circuits, operational amplifiers, comparators and the like, or can be included in a design wherein the signals received by the input circuit have been preconditioned by other circuitry like filters, voltage clipping circuits, ESD protection and the like. It can be particularly advantageous to provide an input circuit according to the present invention in cascade with CML logic gates, wherein the input circuit removes common mode level variations from the received differential signals, whereas subsequent CML logic gate stages provide for the amplification and clipping of the output signals generated by the input circuit. An input circuit according to the present invention can be integrated on a semiconductor chip, either as a stand alone component or in combination with other circuitry for analog and/or digital signal processing. Reference numerals in the claims shall not be construed as limiting the claims.