Title:
INPUT CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/187731
Kind Code:
A1
Abstract:
In order to suppress signal propagation delay at the falling edge of an input signal, an NMOS transistor (M1) is connected between an input terminal (1) that receives a 3.3 V amplitude signal and an input of an inverter (INV1), a first PMOS transistor (M2) having low drive capability and a second PMOS transistor (M4) having high drive capability are parallel-connected between a power supply terminal (VDD18) that supplies 1.8 V and a gate of the NMOS transistor (M1), a gate of the first PMOS transistor (M2) is connected to the input of the inverter (INV1), and a gate of the second PMOS transistor (M4) is connected to an output of the inverter (INV1).
Inventors:
IIDA MASAHISA
Application Number:
PCT/JP2017/006201
Publication Date:
November 02, 2017
Filing Date:
February 20, 2017
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H03K19/0175; H03K19/01
Foreign References:
| JP2001251176A | 2001-09-14 | |||
| JPH11243330A | 1999-09-07 | |||
| JPH09121150A | 1997-05-06 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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