Title:
INPUT CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/058771
Kind Code:
A1
Abstract:
This input circuit comprises: a first NMOS transistor (N1) that has a gate and is connected between an output (OUT) and a ground potential (VSS); a second NMOS transistor (N2) that has a gate connected to a power supply voltage (VDD) and is connected between an input (IN) and the gate of the first NMOS transistor (N1); and first and second PMOS transistors (P1, P2) that each have a gate and are connected in series between the output (OUT) and the power supply voltage (VDD). The gate of the first PMOS transistor (P1) is connected to the gate of the first NMOS transistor (N1), and the gate of the second PMOS transistor (P2) is connected to the input (IN).
Inventors:
GION MASAHIRO (JP)
Application Number:
PCT/JP2018/028723
Publication Date:
March 28, 2019
Filing Date:
July 31, 2018
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H03K19/0175
Domestic Patent References:
| WO2010140276A1 | 2010-12-09 |
Foreign References:
| JPH0629826A | 1994-02-04 | |||
| JP2002280518A | 2002-09-27 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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