Cross-reference to other applications

The disclosure claims priority from US Provisional Patent Application No. 62/751 ,086 filed October 26, 2018, the contents of which are hereby incorporated by reference.

Field

The disclosure is directed generally at power conversion and, more specifically, at an inrush current limited AC/DC power converter apparatus and method.

Background

Various approaches have been attempted to limit the inrush current during an initial power up of a power converter. Limiting inrush current is often necessary to reduce or prevent damage to equipment or the tripping of external circuit breakers and fuses.

One current approach to limiting inrush current is to include a Negative Temperature Coefficient (NTC) thermistor in series between the AC mains and the power converter storage capacitor. A NTC thermistor is a variable resistor that decreases in resistance as its temperature increases in response to current flow through the power converter apparatus. During initial power up of the power converter apparatus, when the thermistor is in a cold state, it will have maximum resistance and maximum current limiting capability. As the thermistor heats up, its resistance decreases and its power dissipation is also reduced.

One disadvantage of this thermistor implementation is that in its reduced resistance state (when the thermistor is hot), the thermistor can still dissipate a significant amount of power thereby reducing overall power conversion efficiency. This also results in a higher internal operating temperature for the power converter. Another disadvantage is that, during operation of the power converter apparatus, when the thermistor is hot and at a reduced resistance, a higher inrush current may result in an AC mains input brown out or a voltage dip and/or interruption.

Therefore, there is provided a novel inrush current limited AC/DC power converter apparatus.

Summary

The disclosure is directed at an inrush current limited AC/DC power converter apparatus. In one embodiment, the apparatus includes a buck switch mode converter configured as a current source combined with a boost converter to limit inrush current during initial turn on or during brown out conditions.

The switching action of the buck converter limits current on a cycle-by-cycle basis. It also remains in a continuous on-state during normal operation with reduced power losses compared to a thermistor approach. Furthermore, the boost converter shares a zero crossing detection apparatus with the buck converter that reduces the component count and complexity of the power converter.

In one aspect, there is provided an inrush current limited AC/DC power converter apparatus including a switch mode buck power converter configured as a current source to limit inrush current to a storage capacitor; wherein the buck converter is coupled to a transition mode controlled PFC boost converter and wherein the buck converter and boost converter share a zero crossing detection circuit to control the switching action of said buck converter during initial start-up of AC/DC power converter and/or during voltage dips or interruptions of input AC mains.

In one aspect of the disclosure, there is provided an inrush current limited AC/DC power converter apparatus for controlling power to a load including a buck converter section; a power factor conversion (PFC) boost converter section; and a storage capacitor section; wherein in a first mode of operation, the boost converter section is disabled and the buck converter section is active and in a second mode of operation, the boost converter section is active and the buck converter section is disabled.

In another aspect, in the first mode of operation, the buck converter section charges the storage capacitor section; and in the second mode of operation, the PFC boost converter section controls power delivered to the load via the storage capacitor section. In a further aspect, the buck converter section includes a microcontroller unit; and a buck converter section current sense element. In yet a further aspect, the buck converter section includes a buck converter section power switch; and a gate driver. In another aspect, microcontroller unit includes a logic cell; and a timer. In yet another aspect, the apparatus includes a shared components section. In another aspect, the shared components section includes an inductor; and a zero current detection circuit.

In yet a further aspect, the boost converter section includes a transition mode (TM) boost controller and a power diode. In another aspect, the boost converter section further includes a boost converter section power switch; and a boost converter section current sense element circuit. In an aspect, the system includes a set of current senses for determining a current level within the inrush current limited AC/DC power converter apparatus.

In another aspect of the disclosure, there is provided a method of limiting inrush current including operating in a first mode of operation whereby a buck converter switching action controls an input current; determining if a peak current threshold has been met; operating in the first mode of operation if the peak current threshold has been met and operating in a second mode of operation whereby a booster converter switching action controls the input current if the peak current threshold is not met.

In yet another aspect, the method further includes charging a bulk capacitor. In another aspect, the method further includes regulating a power factor correction voltage. In yet a further aspect, the method includes determining if there is a voltage dip or interruption; and operating in the second mode of operation if there is no voltage dip or interruption and operating in the first mode of operation if there is a voltage dip or interruption.

Description of the Drawings

Embodiments of the present disclosure will now be described, by way of example only, with reference to the attached Figures.

Figure 1 is a schematic diagram of an inrush current limited AC/DC converter apparatus;

Figure 2 is a schematic diagram of a combined buck and boost converter;

Figure 3a is a schematic diagram of a set of buck converter control signal waveforms;

Figure 3b is a schematic diagram of buck converter power switch control inputs;

Figure 4 is a schematic diagram of a combined buck and boost converter with under voltage lock out; and

Figure 5 is a flowchart outlining a method of limiting inrush current.

Detailed Description

The disclosure is directed at an inrush current limited AC/DC power converter apparatus. In one embodiment, the disclosure includes a buck converter section, a power factor correction (PFC) boost converter section and a bulk storage capacitor section. The disclosure is directed a method and apparatus for controlling, or limiting, the inrush current during predetermined situations, such as, but not limited to, initial turn on or brown out conditions.

Turning to Figure 1 , a schematic diagram of an inrush current limited AC/DC power converter, or conversion, apparatus is shown. The inrush current limited AC/DC power conversion apparatus 100 includes a buck converter section 102 that includes a microcontroller unit (MCU) 104 and a current sense circuit or element 106. In operation, the MCU 104 controls a current feedback loop via the current sense element 106. In one embodiment, the buck converter section 102 may be configured as a current source.

The apparatus 100 further includes a shared components section 108 that includes a boost inductor 110 and a zero crossing detection (ZCD) circuit 112 and a boost converter section 114, or power factor correction (PFC) boost converter section, that includes a free wheel diode 116 and a Transition Mode (TM) or Critical Conduction Mode (CrM) controller 118. The buck converter section 102 can be seen as being coupled to the boost converter section 114 via the shared components section 108. The apparatus 100 further includes a bulk storage capacitor section 120. The apparatus 100 may include further components to enable operation of the apparatus that are not shown as they are not part of the innovation, however, are necessary for operation of the power conversion apparatus.

In operation of the apparatus 100, the buck and boost converter sections 102 and 114 share the boost inductor 110, the ZCD circuit 1 12, the storage capacitor 120 as well as the power diode 116.

This is described in more detail below The power conversion apparatus 100 is coupled to an AC mains input 122, such as a sinusoidal voltage source, via a bridge rectifier 124. A load 126 is typically connected to the apparatus 100 and may include, but is not limited to, an isolated DC/DC converter coupled to either a resistive load or a light emitting diode (LED) load. In one embodiment, the DC/DC converter may be an isolated step down buck derived topology implemented as a half bridge, full bridge, or forward converter topology. Alternatively, the load 126 may be a resistive load or LED load.

Figure 2 provides a more detailed schematic diagram of the apparatus of Figure 1. The power converter apparatus 100 may also be seen as a combined buck and boost switch mode converter. As shown in Figure 2, the buck converter section 102 further includes a high side, or buck converter section, semiconductor power switch 128, such as a metal-oxide-semiconductor field-effect transistor (MOSFET) connected in series between the bridge rectifier 124 and the boost inductor 110. In a preferred embodiment, the boost inductor 110 includes two (2) windings. A first coil winding 110A is connected between a cathode of a buck converter section diode 130 and an anode of the power diode 116 to enable the transfer of energy from the inductor 1 10 to the bulk capacitor 120 during an appropriate switching sequence. A second coil winding 110B, referred to as an auxiliary winding, is coupled to the ZCD circuit 112 and in one embodiment, the second coil winding 110B is used for sensing purposes.

The buck converter section power switch 128 is also connected, via a gate drive circuit 132, to the MCU 104. In the current embodiment, the MCU 104 includes a configurable logic cell 134 and a timer 136. Although not shown, the logic cell 134 includes logic gates and state functions such as NAND/NOR gates, comparators and flip flops that can be configured within the MCU 104 to provide a gate drive signal to control the switching action of the buck converter section power switch 128 based on received input control signals to the MCU 104. Alternatively, the gate drive signal may be implemented via firmware.

The MCU 104 is connected to input control lines (such as VZCD line) from the ZCD circuit 112 that includes a clamp circuit that senses a zero crossing voltage transition when the boost inductor 110 demagnetizes and the current sense circuit 106 senses current flow through the storage capacitor 120.

In one embodiment, the timer 136 includes a counter that counts, such as in 250 ps increments, for a predetermined duration of time during which the switching action of the buck converter section 102 via the buck converter section power switch 128 is permitted.

As shown in Figure 2, the PFC boost converter section 114 further includes a boost converter section power semiconductor switch 138 such as a MOSFET connected between the boost inductor 110 and the anode side of power diode 116. A cathode side of the power diode 116 is connected to the bulk storage capacitor 120 and maintains a regulated DC voltage across the load 126.

As outlined above, not all components, circuit blocks and/or interconnections are shown as they will be understood by one skilled in the art. For example, the AC/DC power converter apparatus 100 may include an electromagnetic (EMI) filter connected between the AC mains input 122 and the bridge rectifier 124. Similarly, the PFC boost converter section 114 may include a voltage control loop circuit to regulate the voltage across the bulk storage capacitor 120.

For inrush current operation, and with reference to Figure 2, the combined buck and boost converter apparatus 100 can operate in two modes of operation.

A first mode of operation occurs when an AC mains voltage input is initially applied and the combined buck and boost power converter apparatus 100 turns on. During the first mode of operation, a switching action of the buck converter section 102, limited to a peak current every switching cycle, charges the output capacitor 120. During the first mode of operation, the boost converter section 114 is disabled with its power switch 138 in its off state.

A second mode of operation begins after the initial turn on of the combined buck and boost apparatus 100 when the bulk, or output, capacitor 120 has charged such that an inrush current does not reach a predetermined threshold value or current within a predetermined period of time. At the start of the second mode of operation, the switching action of the buck converter section 102 is discontinued, or stopped while the power switch 128 remains in a continuous on state. The boost converter section 114 is then enabled and can begin switching. In this mode of operation, the boost converter section 114 continues to charge the bulk capacitor 120 to a regulated voltage Vcs and control peak input current while providing power factor correction.

In one embodiment, the predetermined threshold current may be calculated such that its value is greater than what can be reached during normal operation or the second mode of operation at 100% load and AC mains input 122 low line voltage input such as 100 Vac. For example, assuming a load 126 of 120 watts, a power conversion efficiency of 90% and a unity power factor, an input current of the combined buck and boost apparatus 100 can be calculated to be 1.33 Arms. With the boost converter section 114 operating in critical conduction mode during the second mode of operation, the expected peak current reached during normal operation is calculated to be 3.77 Apk. Therefore, in this instance, a predetermined threshold current of 3.9 Apk may be selected which is greater than the normal operating current of 3.77 Apk at a worst case line input voltage of 100 Vac.

With reference to the predetermined time period, as an example, the AC mains input 122 in North America is a 60 Hz sinusoidal voltage. The bridge rectifier 124 rectifies the sinewave resulting in a waveform with a period of 8.3 ms (milliseconds), therefore a predetermined period of time greater than 8.3 ms may be selected. For instance, a predetermined time period of 12 ms can be used such that at least one AC mains rectified sinewave cycle with a peak voltage transition Vbr may occur during this predetermined period of time.

A transition from the second mode of operation back to the first mode of operation occurs at any time when an AC mains input 122 power anomaly is experienced, such as a voltage dip or interruption, whereby the power anomaly results in the voltage across the bulk capacitor 120 decreasing significantly below a predetermined regulated output boost converter bus voltage. During this transition, the buck converter section 102 detects, via current sense circuit 106, the input current to determine if a predetermined peak current threshold is reached as the bulk capacitor 120 is recharged. If the predetermined peak current threshold is reached, the buck converter section 102 changes from a continuous on-state to a switching action of power switch 128 and back to the first mode of operation whereby the inrush current is peak limited every switching cycle as the storage capacitor 120 recharges. In returning to the first mode of operation, the boost converter section 114 is disabled with no switching action and its power switch 138 is in the off-state.

In another example, during the first mode of operation at turn on, the buck converter section 102 begins to charge the bulk capacitor 120 via a switching action of power switch 128. When switch 128 is turned on (or closed), the inrush current and therefore the rate of change of current over time (di/dt) is limited by the inductor 1 10A as current ramps up and flows through power diode 116 to charge storage capacitor 120.

The inductor 110A limits or reduces the rate of increase of current with time based on the instantaneous rectified AC mains voltage Vbr at the bridge rectifier 124 and the storage capacitor DC voltage V _cs expressed as (ignoring diode drop losses):

where the differential voltage (Vbr -V _cs ) is applied across inductor winding 110A.

When the switch 128 is turned off, the voltage across inductor 110A reverses polarity and the current continues to flow through power diode 116 and freewheel diode 130 into bulk capacitor 120, ramping downward over time as energy is transferred from the inductor 110A.

As the bulk capacitor 120 continues to charge with repetitive power switch 128 switching cycles, the differential voltage between the rectified sinewave mains peak point (Vbr) and the bulk capacitor V _cs declines such that eventually the ramp current (di/dt) does not reach its predetermined threshold within a predetermined period of time.

For example, in one specific embodiment, for an AC mains input 122 with a sinusoidal voltage of 120 Vac and a frequency of 60Hz, the rectified peak voltage is established at 169.68 Vpk. The inductor value is 570 pH, the predetermined current threshold is 3.9 Apk, and the predetermined time period is set at 12 ms. Based on these parameters and with reference to Eq. 7, the bulk capacitor voltage V _cs is calculated to be 169.49 V.

Therefore, for a bulk capacitor voltage V _cs greater than 169.49 V, there will be no further switching action of switch 128 since the predetermined current threshold of 3.9 Apk is not reached within the predetermined time period of 12 ms.

The MCU 104 controls the switching action of buck converter section 102 by providing a gate drive signal (via gate driver circuit 132) to the power switch 128. The gate drive signal is generated and controlled by the configurable logic cell 134 based on input signal VzcDfrom the ZCD circuit 1 12, the sense signal linms _h from current sense element 106 and timer 136. The configurable logic cell 134 is initialized during initial power up of the combined buck and boost converter apparatus 100. In a preferred embodiment, the initialization is implemented via firmware.

Both the timer 136 and the peak current sense signal determine when an inrush current sense event has concluded. In one specific embodiment, the MCU 104 is programmed to limit the sensed peak current to 3.9 amps peak for every switching cycle of power switch 128 to charge the bulk capacitor 120. The timer 136 is also established at a predetermined limit of 12 ms (milliseconds) to detect a switching event.

If the peak inrush current of 3.9 A is reached (or sensed by the circuit 106), the gate drive circuit 132 turns the power switch 128 off and the timer is reset for another 12ms interval via an interrupt and the power supply remains in or enters the first mode of operation. Once the 12ms interval expires, the apparatus 100 enters the second mode of operation. After power switch 128 is turned off, the inductor 110A reverses voltage polarity and demagnetizes as the inductor current ramps to zero. The ZCD circuit 112 senses via inductor winding 1 10B (coupled to winding 110A), a zero crossing voltage V _ZCd as the voltage transitions from positive to negative. At this point in time, the switch 128 is turned on to begin another switching cycle.

If the peak inrush current of 3.9 A is not reached within the 12 ms time frame, the inrush current limit event is determined to have concluded and the MCU 104 enables the TM boost controller 118 to begin switching the boost converter section 114 stage. The buck converter power switch 128 maintains an on-state condition unless a brown out event occurs. If a voltage dip or interruption occurs, the buck converter section 102 and corresponding power switch 128 may revert back to a switching action and the first mode of operation if the voltage across the bulk capacitor 120 decreases significantly below the peak rectified sinusoidal voltage.

As the timer 136 duration of 12 ms is approximately equal to one and a half cycles of a 120 Hz rectified sinusoidal AC mains voltage, it is understood that the timer duration can be configured for various other values and that the peak current threshold may also be configured for various values. The configuration requirements may be programmed into the MCU 104.

After the inrush current event has terminated, the second mode of operation begins and the boost converter section 114 is turned on with an enable control signal transmitted from the MCU 104 to the TM boost controller 118. It is understood that for those skilled in the art, the boost converter section 114 continues to control peak input current flow through the inductor 1 10A to charge the bulk capacitor 120 via current sense 140 and provide power factor correction and a regulated DC voltage across the bulk capacitor 120 typically around 450 Vdc.

In operation of the boost converter section 114, power factor correction is achieved by the input current being sourced in a sinusoidal manner to track with the input AC mains 122 sinusoidal voltage by a switching action of the boost converter. This results in a peak inductor current that is enveloped by a rectified sinusoidal waveform in phase with the input sinusoidal voltage. The TM boost controller 1 18 controls the switching of power switch 138 in a fixed on-time, variable frequency mode of operation. In transition mode, the inductor 1 10 operates at the boundary between continuous and discontinuous conduction modes whereby the inductor current ramps to zero current every switching cycle.

The current flow through inductor 1 10A is sensed by a current sense 140 (located in the boost converter section 1 14) and the demagnetization of inductor 1 10A is sensed by inductor auxiliary winding 1 10B and ZCD circuit 1 12 to control the switching action of the power switch 138.

Turning to Figure 3A, a set of signal waveforms for a buck converter to control inrush current are shown. The set of signal waveforms includes a gate drive signal waveform with an on and off duration, an ILHOA signal waveform with an l _pe ak limit, a VZCD(HOB) signal waveform with an off

(VZCD(I IOB>OFF) threshold and an on (VZCD(HOB)ON) threshold, and a VCDCCT signal waveform with a with a VzcDdrive threshold.

A gate drive turn on signal 150 is applied to the power switch 128 resulting in a current ramping 152 up through inductor 1 10 until a predetermined threshold is met 154.

When the predetermined threshold is met 154, the gate drive turns off the power switch 128, the auxiliary winding 1 10B reverses voltage polarity 156 as the inductor 1 10 demagnetizes, and a voltage pulse signal VzcDdrive is generated 158 by the ZCD circuit 1 12. At the threshold limit 154, the timer 136 is also reset for another 12 ms duration.

During the demagnetization of inductor 1 10, the current ramps to zero 160 and the VZCD signal 158 transitions from positive to negative. At the transition of the VZCD signal as the voltage crosses zero 162, the gate drive 164 turns on again beginning another current ramp cycle.

Figure 3B shows a detailed block diagram of a buck converter gate drive apparatus. During an inrush current limit mode of operation, the logic cell 134 controls the switching action of the power switch 128 based on inputs from the ZCD circuit 1 12, the current sense circuit 106 and timer 136.

The input that is sensed by the current sense circuit 106 assists to controls the turn off of the power switch 128 and the ZCD circuit 1 12 controls the turn on of the power switch. The timer 136 provides a time limit for the inrush current to ramp to its predetermined limit and an interrupt resets the time limit every time the peak current limit is reached.

The inrush current mode of operation concludes when the input current has not reached its predetermined limit within the time limit established by the timer 136.

Figure 4 shows an alternate embodiment of a combined buck and boost converter apparatus 100. In the current embodiment, the apparatus 100 includes a voltage sense circuit 164 that operates to monitor the storage capacitor voltage 120. The signal that is sensed by the voltage sense circuit 164 signal is transmitted to the MCU 104 and provides an additional control input signal as an under voltage lock out threshold to enable or disable the boost converter section 1 14.

For example, the MCU 104 can be programmed to reduce the likelihood or prevent the boost converter section 1 14 from activating or reduce the likelihood of the boost converter section 1 14 from activating until a predetermined capacitor voltage, such as a minimum or low capacitor voltage of 140 Vdc, is reached. When the threshold is reached, an enable signal is transmitted to the boost controller 118. All other aspects of operation of the combined buck and boost converter remain the same as the embodiment described above with respect to Figure 2.

Turning to Figure 5, a flowchart outlining a method of limiting inrush current is shown. Initially upon power up (200), the system or apparatus enters a first mode of operation (202). In this first mode of operation, buck converter switching action to control an input current is initiated or maintained (204).

A determination is then made to check if a peak current threshold has been reached, and if so, the timer interval is reset (206). If the peak current threshold has been reached, the system remains in the first mode of operation (202).

If the peak current threshold has not been reached within a time interval, the system enters a second mode of operation (208). In the second mode of operation, the buck converter switching action is disabled and the switch is maintained in an on-state (210). The booster converter switching action is then enabled or maintained to control the input current (212).

The bulk capacitor is then charged and the PFC voltage regulated (214). A check is then performed to determine if there is a voltage dip or interruption (216). If there is no voltage dip or interruption, the system remains in the second mode of operation (208). If there is a dip in voltage or an interruption, the system checks if a peak current threshold has been reached, and if so, the system or apparatus enters the first mode of operation.

Although the present disclosure has been illustrated and described herein with reference to preferred embodiments and specific examples thereof, it will be readily apparent to those of ordinary skill in the art that other embodiments and examples may perform similar functions and/or achieve like results. All such equivalent embodiments and examples are within the spirit and scope of the present disclosure.

In the preceding description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the embodiments. However, it will be apparent to one skilled in the art that these specific details may not be required. In other instances, well-known structures may be shown in block diagram form in order not to obscure the understanding. For example, specific details are not provided as to whether elements of the embodiments described herein are implemented as a software routine, hardware circuit, firmware, or a combination thereof.

Embodiments of the disclosure or components thereof can be provided as or represented as a computer program product stored in a machine-readable medium (also referred to as a computer- readable medium, a processor-readable medium, or a computer usable medium having a computer- readable program code embodied therein). The machine-readable medium can be any suitable tangible, non-transitory medium, including magnetic, s optical, or electrical storage medium including a diskette, compact disk read only memory (CD-ROM), memory device (volatile or non-volatile), or similar storage mechanism. The machine-readable medium can contain various sets of instructions, code sequences, configuration information, or other data, which, when executed, cause a processor or controller to perform steps in a method according to an embodiment of the disclosure. Those of ordinary skill in the art will appreciate that other instructions and operations necessary to implement the described implementations can also be stored on the machine-readable medium. The instructions stored on the machine-readable medium can be executed by a processor, controller or other suitable processing device, and can interface with circuitry to perform the described tasks.