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Patent Searching and Data


Title:
INRUSH CURRENT SUPPRESSION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2015/125793
Kind Code:
A1
Abstract:
This inrush current suppression circuit suppresses an inrush current flowing to a load, and the load is provided with an input capacitor (10) connected to a power supply (1), and a pair of output terminals (3, 4), which are connected in parallel to the input capacitor (10), and which output a current inputted from the power supply (1). The inrush current suppression circuit is configured from: a FET (5) that is on/off controlled by being connected to the direct current power supply (1); a first inductor (8) connected between a connection point and the FET (5); a reflux diode (9) that connects the cathode to a connection point between the FET (5) and the first inductor (8); and a second inductor connected between the connection point and the anode of the diode. The first and second inductors (8) are configured from a magnetic body covering around an electric wire (L), i.e., a current path.

Inventors:
MATSUSHITA Yoshinori (1500 Mishuku, Susono-sh, Shizuoka 94, 〒4101194, JP)
KIMURA Osamu (1500 Mishuku, Susono-sh, Shizuoka 94, 〒4101194, JP)
Application Number:
JP2015/054346
Publication Date:
August 27, 2015
Filing Date:
February 17, 2015
Export Citation:
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Assignee:
YAZAKI CORPORATION (4-28, Mita 1-chome Minato-k, Tokyo 33, 〒1088333, JP)
International Classes:
H02H9/02; H02J1/00
Foreign References:
JPH06327239A1994-11-25
JPH08275383A1996-10-18
JP2002095158A2002-03-29
JPH05260736A1993-10-08
Attorney, Agent or Firm:
EIKOH PATENT FIRM, P.C. et al. (Toranomon East Bldg. 10F, 7-13 Nishi-Shimbashi 1-chome, Minato-k, Tokyo 03, 〒1050003, JP)
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