Title:
INSTRUCTION CACHE MEMORY FOR REAL-TIME SYSTEMS
Document Type and Number:
WIPO Patent Application WO2006017874
Kind Code:
A3
Abstract:
For real-time systems, the knowledge of the maximum execution time (worst case execution time (WCET)) is of fundamental importance. The influence of the instruction cache upon this WCET in conventional designs is difficult to predict and leads to pessimistic WCET values. For this reason, the invention provides an instruction cache (103) for a processor (100), which enables a more precise predictability of the real-time behavior. The instruction cache is loaded with complete functions and combines all cache misses in the event of a function call-up and function return.
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Inventors:
SCHOEBERL MARTIN (AT)
Application Number:
PCT/AT2005/000326
Publication Date:
November 23, 2006
Filing Date:
August 12, 2005
Export Citation:
Assignee:
SCHOEBERL MARTIN (AT)
International Classes:
G06F9/38; G06F9/32
Domestic Patent References:
| WO1997036234A1 | 1997-10-02 | |||
| WO2003065204A1 | 2003-08-07 |
Foreign References:
| US4755935A | 1988-07-05 | |||
| US5197131A | 1993-03-23 | |||
| US5490262A | 1996-02-06 | |||
| US5893142A | 1999-04-06 |
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