Title:
INSTRUCTION SET SIMULATOR AND SIMULATOR GENERATION METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2017/014318
Kind Code:
A1
Abstract:
This instruction set simulator (S) comprises subroutine detection means (1d, 1e, 1f, 2), branch instruction detection means (1d, 2), subroutine call instruction detection means (1c, 1d), subroutine source code output means (3a, 3e), an identifier addition means (3a4), unconditional branch instruction output means (3a5, 3a6, 3a8), and subroutine call instruction output means (3a8, 3a9).
Inventors:
ISSHIKI TSUYOSHI (JP)
Application Number:
PCT/JP2016/071632
Publication Date:
January 26, 2017
Filing Date:
July 22, 2016
Export Citation:
Assignee:
TOKYO INST TECH (JP)
International Classes:
G06F9/455
Foreign References:
| JPH096646A | 1997-01-10 | |||
| JP2001515240A | 2001-09-18 | |||
| JPH1083311A | 1998-03-31 | |||
| JPH1124940A | 1999-01-29 |
Attorney, Agent or Firm:
ISONO INTERNATIONAL PATENT OFFICE, P.C. (JP)
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