BACKGROUND

[0001] Electronic technology has advanced to become virtually ubiquitous in society and has been used for many activities in society. For example, electronic devices are used to perform a variety of tasks, including work activities, communication, research, and entertainment. Different varieties of electronic circuitry may be utilized to provide different varieties of electronic technology.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] FIG. 1 is a block diagram illustrating an example of a computing device that may be used to provide instruction updates to a hardware device; [0003] FIG. 2 is a thread diagram illustrating an example of instruction updates to hardware devices;

[0004] FIG. 3 is a block diagram illustrating an example of an apparatus to perform instruction updates to hardware devices;

[0005] FIG. 4 is a flow diagram illustrating an example of a method for determining whether to lock or unlock a bus; and

[0006] FIG. 5 is a flow diagram illustrating an example of a method for instruction updates to hardware devices.

DETAILED DESCRIPTION

[0007] Some examples of the techniques described herein may be related to instruction updates to hardware devices. Some electronic devices (e.g., computing devices, laptop computer, desktop computer, etc.) may include a hardware device. A hardware device may include a microprocessor or microcontroller to execute firmware to provide functionality on the electronic device. Firmware may be stored in integrated storage (e.g., non-volatile storage on the hardware device) or in separate storage. In some examples, a hardware device may be connected to a central processing unit (CPU) via an input/output (10) bus. Examples of an 10 bus may include an inter-integrated circuit (I2C) bus, Universal Serial Bus (USB) or serial peripheral interface (SPI) bus.

[0008] During a firmware update, in some examples, a host CPU may receive a firmware image and may transfer the firmware image to the hardware device via an 10 bus, and the hardware device programs the firmware to storage. In some examples, the hardware device may accept a firmware image within a trust boundary (e.g., during BIOS POST before booting or before booting is completed).

[0009] In some examples, a hardware device may utilize relatively large firmware and may be connected to a host CPU with a relatively low speed bus. Some approaches to firmware updating may take a relatively long time to complete.

[0010] Some of the techniques described herein may provide a shared bus architecture with isolation control. For instance, firmware storage may be accessed by a host and a hardware device. The bus may be controlled by the BIOS and may be locked down. In a case where there is a pending firmware update, the BIOS may put the hardware device in reset and may gain access to the firmware storage. The BIOS may directly program the new firmware to the firmware storage and perform a reset upon completion of the firmware update. In a case where there is no pending firmware update, in some examples, the BIOS may lock down the bus within the trust boundary so that no access to the firmware storage is allowed from the host.

[0011] An electronic device may be a device that includes electronic circuitry (e.g., integrated circuitry). A computing device may be an electronic device that includes a processor, logic circuitry, or a combination thereof. Examples of computing devices may include desktop computers, laptop computers, tablet devices, smartphones, televisions, game consoles, smart speakers, voice assistants, Internet of Things (loT) devices, etc. A computing device may utilize processor(s) or logic circuitry to perform an operation or operations. In some examples, computing devices may execute instructions stored in memory to perform the operation(s). Instructions may be code or programming that specifies functionality or an operation of a processor or logic circuitry. In some examples, instructions may be stored in non-volatile memory (e.g., Read-Only Memory (ROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), flash memory, etc.). In some examples, different memories (e.g., flash memories) in an electronic device may store separate instructions for different circuitries. [0012] In some examples, a computing device may be linked to another electronic device or devices using a wired link, a wireless link, or a combination thereof. For example, a computing device may include a communication interface for linking to an electronic device (e.g., switch, router, server, computer, etc.). Examples of wired communication interfaces may include an Ethernet interface, Universal Serial Bus (USB) interface, fiber interface,

Lightning interface, etc. In some examples, a computing device may include a wireless communication interface to send wireless signals (e.g., radio frequency (RF)), receive wireless signals, or a combination thereof. Examples of wireless communication interfaces may include an Institute of Electrical and Electronics Engineers (IEEE) 802.11 (Wi-Fi) interface, Bluetooth interface cellular (e.g., 3G, Long-Term Evolution (LTE), 4G, 5G, etc.) interface, etc.

[0013] Throughout the drawings, similar reference numbers may designate similar or identical elements. When an element is referred to without a reference number, this may refer to the element generally, with or without limitation to any particular drawing or figure. In some examples, the drawings are not to scale and the size of some parts may be exaggerated to more clearly illustrate the example shown. Moreover, the drawings provide examples in accordance with the description. The description is not limited to the examples provided in the drawings. [0014] FIG. 1 is a block diagram illustrating an example of a computing device 102 that may be used to provide instruction updates to a hardware device. Examples of the computing device 102 may include a computer (e.g., laptop computer), a smartphone, a tablet computer, a game console, etc. The computing device 102 may include a first hardware device 106, a first firmware component 108, a bus 112, a second hardware device 110, and a basic input/output system (BIOS) 104.

[0015] The first hardware device 106 may be a logic circuit. For instance, the first hardware device 106 may be a logic circuit capable of performing logical operations. Examples of the first hardware device 106 may include a processor, field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), etc. In some examples, the first hardware device 106 is artificial intelligence circuitry. For instance, the first hardware device 106 may perform a machine learning operation or operations. In some examples, the first hardware device 106 may execute a machine learning model to perform object detection, object recognition, classification, speech recognition, or a combination thereof. In some examples, the first hardware device 106 may be disposed (e.g., located) in a display panel housing of the computing device 102. For instance, the computing device 102 may be a laptop computer that includes a display panel housing and the first hardware device 106 may be disposed in the display panel housing in some examples.

[0016] The first firmware component 108 may be memory circuitry to store firmware. Firmware may be executable instructions stored in non-volatile memory. Examples of the first firmware component 108 may include non-volatile memory, read-only memory (ROM), erasable programmable ROM (EPROM), flash memory, or a combination thereof. The first firmware component 108 may be coupled to the first hardware device 106. For instance, the first firmware component 108 may be coupled to the first hardware device 106 with an interface, wire, bus connection, or a combination thereof. The first firmware component 108 may store firmware for execution by the first hardware device 106. For instance, the first firmware component 108 may store a machine learning model for execution by the first hardware device 106. [0017] The second hardware device 110 may be a logic circuit. For instance, the second hardware device 110 may be a logic circuit capable of performing logical operations. Examples of the second hardware device 110 may include a processor, FPGA, ASIC, etc. In some examples, the second hardware device 110 is an FPGA. For instance, the second hardware device 110 may be an FPGA utilized for hardware acceleration, task offloading (e.g., offloading a task from a central processing unit (CPU) or application processor), input/output (I/O) port expansion, or a combination thereof, etc.

[0018] In some examples, the second hardware device 110 may be disposed (e.g., located) in a body of the computing device 102. For instance, the computing device 102 may be a laptop computer that includes a body and the second hardware device 110 may be disposed in the body (with the BIOS 104, motherboard, CPU, keyboard, or a combination thereof, etc.) in some examples. [0019] In some examples, portions of the computing device 102 may be coupled via an interface (e.g., bus(es), wire(s), connector(s), etc.). As used herein, the term “couple” or “coupled” may denote a direct connection (without an intervening component) or an indirect connection (with an intervening component(s)). The BIOS 104 may be coupled to the first hardware device 106 and to the second hardware device 110 by the bus 112. Examples of the bus 112 may include a serial peripheral interface (SPI) bus, inter-integrated circuit (I2C) bus, general purpose input/output (GPIO) bus, or a combination thereof, etc. The bus 112 may be utilized to communicate a signal, information, or a combination thereof. In some examples, the computing device 102 may include a coupling(s) (not shown in FIG. 1) in addition to the bus 112. In some examples, the BIOS 104 is coupled to the first hardware device 106 by the bus 112 and a cable that crosses a hinge interface between a body and a display panel housing of the computing device 102. For instance, the computing device 102 may be a laptop computer and the BIOS 104 may be coupled to the first hardware device 106 via the bus 112 and a cable coupled to the bus 112, where the cable connects the bus 112 to the first hardware device 106 over the hinge interface. [0020] The computing device 102 may include a BIOS 104. As used herein, a basic input/output system (BIOS) refers to hardware or hardware and instructions to initialize, control, or operate a computing device (e.g., computing device 102) prior to execution of an operating system (OS) of the computing device. Instructions included within a BIOS may be software, firmware, microcode, or other programming that defines or controls functionality or operation of a BIOS. In one example, a BIOS may be implemented using instructions, such as platform firmware of a computing device, executable by a processor. A BIOS may operate or execute prior to the execution of the OS of a computing device. A BIOS may initialize, control, or operate components such as hardware components of a computing device and may load or boot the OS of a computing device.

[0021] In some examples, a BIOS may provide or establish an interface between hardware devices or platform firmware of the computing device 102 and an OS of the computing device 102, via which the OS of the computing device 102 may control or operate hardware devices or platform firmware of the computing device 102. In some examples, a BIOS may implement the Unified Extensible Firmware Interface (UEFI) specification or another specification or standard for initializing, controlling, or operating a computing device.

[0022] In some examples, the BIOS 104 may perform operations during a boot sequence. A boot sequence may be a sequence of operations performed to boot an OS of the computing device 102 (e.g., before booting). For example, a boot sequence may be performed before an OS of the computing device 102 is operational (e.g., fully booted up) or before a boot event. In some examples, the BIOS 104 may perform an operation(s) within a trust boundary. A trust boundary may establish a period or state in which a sensitive operation(s) may be performed, and may establish a period or state in which a sensitive operation(s) may be prohibited. Before a trust boundary, for instance, the BIOS 104 may allow a sensitive operation (e.g., first hardware device 106 firmware update, second hardware device 110 firmware update, etc.) to be performed. After the trust boundary, a sensitive operation may be prohibited. For instance, the BIOS 104 may lock the bus 112 after the trust boundary to reduce access to change the firmware for the first hardware device 106 or to change the firmware for the second hardware device 110.

[0023] During a boot sequence, the BIOS 104 may set the second hardware device 110 to a reset state. For example, the BIOS 104 may send (e.g., assert) a signal (e.g., voltage, signal, pattern, etc.) to the second hardware device 110 that sets the second hardware device 110 to a reset state. When in a reset state, the second hardware device 110 may be disabled from receiving information on the bus 112. For instance, setting the second hardware device 110 to a reset state may enable the BIOS 104 to send information on the bus 112 to the first hardware device 106 without impacting the second hardware device 110. In some examples, the BIOS 104 may set the second hardware device 110 to the reset state in response to determining that an update flag is set for the first hardware device 106. For instance, the computing device 102 (e.g., BIOS 104 or OS) may set an update flag to update a hardware device when an instruction (e.g., firmware) update is available for the corresponding device. For instance, the computing device 102 may receive and store a firmware update and set an update flag for the corresponding hardware device. In some examples, the firmware update may be stored in an extensible firmware interface (EFI) system partition (ESP) on a hard drive. In some examples, the update flag may be stored as a UEFI variable. During the boot sequence, the BIOS 104 may read the update flag and may begin update procedures (e.g., setting a hardware device in a reset state) in response to an update flag. In some examples, the BIOS 104 may clear the update flag after the instructions are updated (e.g., firmware is updated).

[0024] During the boot sequence, the BIOS 104 may update instructions to the first firmware component 108 via the bus 112 while the second hardware device 110 is in the reset state. For instance, the BIOS 104 may send a firmware update to the first firmware component 108 to update the firmware for the first hardware device 106. In some examples, the firmware may be sent to the first firmware component 108 via the first hardware device 106 or may be sent to the first firmware component 108 directly. [0025] The BIOS 104 may lock the bus 112 after the instructions are updated. For example, the BIOS 104 may drive an output enable signal to a first state (e.g., “high,” upper voltage state, a high value, etc.) to lock the bus 112. In some examples, the bus 112 may include or may be coupled to a buffer. In some examples, the buffer may be utilized to lock the bus 112. For instance, the output enable signal in the first state may disable a buffer to lock the bus 112. Locking the bus 112 may disable the bus 112 from carrying information.

[0026] In some examples, the computing device 102 may include a second firmware component (e.g., memory circuitry to store firmware, not shown in FIG. 1). Examples of the second firmware component may include non-volatile memory, ROM, EPROM, flash memory, or a combination thereof. The second firmware component may be coupled to the second hardware device 110. For instance, the second firmware component may be coupled to the second hardware device 110 with an interface, wire, bus connection, or a combination thereof. The second firmware component may store firmware for execution by the second hardware device 110. For instance, the second firmware component may store instructions for execution by the second hardware device 110.

[0027] In some examples, during the boot sequence (and when the bus 112 is unlocked, for instance) the BIOS 104 may set the first hardware device 106 to a second reset state. The BIOS 104 may update second instructions (e.g., second firmware) to the second firmware component via the bus 112 while the first hardware device 106 is in the second reset state. In some examples, the first firmware component 108 may be updated before the second firmware component, or the second firmware component may be updated before the first firmware component 108. In some examples, a component described herein may be removed or modified without departing from the scope of this disclosure. [0028] In some examples, the computing device 102 may include additional components (e.g., circuitries, interfaces, wires, etc.). For example, the computing device 102 may include input/output (I/O) circuitry (e.g., port(s), interface circuitry, etc.), input device(s), output device(s), or a combination thereof, etc. Examples of output devices include a display panel(s), speaker(s), headphone(s), etc. Examples of input devices include a keyboard, a mouse, a touch screen, camera, microphone, etc. In some examples, a user may input instructions or data into the computing device 102 using an input device or devices.

[0029] In some examples, the computing device 102 may include a central processing unit (CPU). The CPU may be a processor to perform an operation on the computing device 102. Examples of the CPU may include a general- purpose processor, a microprocessor, etc. In some examples, the CPU may be an application processor. The CPU may execute instructions (e.g., an application) on the computing device 102.

[0030] In some examples, the computing device 102 may include memory circuitry to support the CPU. The memory circuitry may be electronic, magnetic, optical, other physical storage device(s), or a combination thereof that contains or stores electronic information (e.g., instructions and data). The memory circuitry may store instructions for execution by the CPU. In some examples, the memory circuitry may be separate from the first firmware component 108 (and the second firmware component, for instance) described in FIG. 1. The memory circuitry may be, for example, Random Access Memory (RAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), storage device(s), optical disc(s), the like, or a combination thereof. In some examples, the memory circuitry may be volatile or non-volatile memory, such as Dynamic Random Access Memory (DRAM), EEPROM, magnetoresistive random-access memory (MRAM), phase change RAM (PCRAM), memristor, flash memory, the like, or a combination thereof. In some examples, the memory circuitry may be non-transitory tangible machine-readable or computer-readable storage media, where the term “non-transitory” does not encompass transitory propagating signals.

[0031] In some examples, the computing device 102 may perform one, some, or all of the aspects, operations, elements, etc., described in one, some, or all of FIG. 1-5. In some examples, the computing device 102 may include an element described in one, some, or all of FIG. 1-5.

[0032] FIG. 2 is a thread diagram illustrating an example of instruction updates to hardware devices. FIG. 2 illustrates examples of a first memory 201 , a first logic circuit 203, a bus controller 205, a BIOS 207, a second logic circuit 209, and a second memory 211. In some examples, the first memory 201 , the first logic circuit 203, the BIOS 207, the second logic circuit 209, and the second memory 211 may be respective examples of the first firmware component 108, the first hardware device 106, the BIOS 104, the second hardware device 110, and the second firmware component described in relation to FIG. 1. In some examples, the first logic circuit 203 may be coupled to the first memory 201. [0033] The bus controller 205 may be circuitry (e.g., integrated circuitry, semiconductor circuitry, electronic component(s), etc.) to control an aspect of bus operation. For example, the bus controller 205 may include a circuitry component(s) (e.g., buffer(s), transistor(s), resistor(s), capacitor(s), inductor(s), etc.) that may be operated based on a signal(s) to control a bus (e.g., the bus 112 described in FIG. 1).

[0034] At 213, the BIOS 207 may perform a pending update determination. For example, the BIOS 207 may determine whether an update flag is set for the first logic circuit 203 (e.g., the first memory 201), whether an update flag is set for the second logic circuit 209 (e.g., second memory 211), or a combination thereof. In some examples, the pending update determination may be performed as described in FIG. 1. For example, the BIOS 207 may read a flag value(s) from a register or memory indicating whether an update is pending for the first logic circuit 203, for the second logic circuit 209, or for a combination thereof. In some examples, the BIOS 207 may determine that a first update flag indicates a pending update of the first logic circuit 203. In some examples, the BIOS 207 may determine that a second update flag indicates a second pending update of the second logic circuit 209.

[0035] At 215, the BIOS 207 may assert a second reset signal to the second logic circuit 209 to set the second logic circuit 209 to a reset state. In some examples, the BIOS 207 may set the second logic circuit 209 to a reset state as described in FIG. 1. For example, the BIOS 207 may assert a voltage, a current, a pattern, or a combination thereof to cause the second logic circuit 209 to enter a reset state. [0036] At 217, the BIOS 207 may send a first selection signal to the bus controller 205 to select the first logic circuit 203. The first selection signal may be a voltage, a current, a pattern, or a combination thereof (e.g., a chip select signal) to cause the bus controller 205 to select the first logic circuit 203 (e.g., route a bus channel from the BIOS 207 to the first logic circuit 203 or to the first memory 201).

[0037] At 219, the BIOS 207 may send a first update to the first memory 201 via a bus. In some examples, sending the first update to the first memory 201 may be performed as described in FIG. 1. For instance, the BIOS 207 may send an updated firmware image to the first memory 201. In some examples, the first update may be sent to the first memory 201 via the first logic circuit 203. For instance, the first update may be sent from the BIOS 207 to the first logic circuit 203, which may relay the first update to the first memory 201. In some examples, the first update may be sent to the first memory 201 without being sent to the first logic circuit 203.

[0038] At 221 , the BIOS 207 may assert a first reset signal to the first logic circuit 203. The first reset signal may set the first logic circuit 203 to a reset state. In some examples, the BIOS 207 may set the second logic circuit 209 to a reset state as described in FIG. 1. For example, the BIOS 207 may assert a voltage, a current, a pattern, or a combination thereof to cause the second logic circuit 209 to enter a reset state.

[0039] At 223, the BIOS 207 may de-assert the second reset signal. For example, the BIOS 207 may discontinue asserting the second reset signal or may change the second reset signal to another state that causes the second logic circuit 209 to exit the reset state.

[0040] At 225, the BIOS 207 may send a second selection signal to the bus controller 205 to select the second logic circuit 209. The second selection signal may be a voltage, a current, a pattern, or a combination thereof (e.g., a chip select signal) to cause the bus controller 205 to select the second logic circuit 209 (e.g., route a bus channel from the BIOS 207 to the second logic circuit 209 or to the second memory 211 ). [0041] At 227, the BIOS 207 may send a second update to the second memory 211 via the bus. In some examples, sending the second update to the second memory 211 may be performed as described in FIG. 1. For instance, the BIOS 207 may send an updated firmware image to the second memory 211. In some examples, the second update may be sent to the second memory 211 via the second logic circuit 209. For instance, the second update may be sent from the BIOS 207 to the second logic circuit 209, which may relay the second update to the second memory 211. In some examples, the second update may be sent to the second memory 211 without being sent to the second logic circuit 209.

[0042] At 229, the BIOS 207 may send a lock signal to the bus controller 205 to disable the bus. In some examples, sending the lock signal may be performed as described in FIG. 1. In some examples, the lock signal may disable a buffer(s) of the bus, which may reduce (e.g., prevent) further communication from the BIOS 207 to the first logic circuit 203 (e.g., first memory 201) and from the BIOS 207 to the second logic circuit 209.

[0043] In some examples, the BIOS 207 may clear the first update flag. For example, the BIOS 207 may set an indicator to a value indicating that there is no pending update to the first logic circuit 203.

[0044] In some examples, the BIOS 207 may clear the second update flag. For example, the BIOS 207 may set an indicator to a value indicating that there is no pending update to the second logic circuit 209.

[0045] In some examples, the BIOS 207 may initiate a BIOS reset. For instance, the BIOS 207 may perform a restart procedure to enable the first logic circuit 203 and the second logic circuit 209 to operate with the updated instructions (e.g., firmware).

[0046] FIG. 2 provides an example where the first logic circuit 203 is updated before the second logic circuit 209. In some examples, the second logic circuit 209 may be updated before the first logic circuit 203.

[0047] FIG. 3 is a block diagram illustrating an example of an apparatus 338 to perform instruction updates to hardware devices. In some examples, the apparatus 338 may perform the operations described in FIG. 1 , FIG. 2, or a combination thereof. The apparatus 338 may be an example of the computing device 102 described in FIG. 1. In some examples, the apparatus 338 may include a BIOS 336, a bus controller 328, a cable 334, second memory 324, a second logic circuit 326, a first logic circuit 342, and a first memory 340. Examples of the apparatus 338 may include a computing device, smartphone, laptop computer, tablet device, mobile device, etc.). In some examples, one, some, or all of the components of the apparatus 338 may be structured in hardware (e.g., circuitry). In some examples, the components described in FIG. 3 may be examples of corresponding components described in FIG. 1 , FIG. 2, or a combination thereof. In some examples, the apparatus 338 may perform one, some, or all of the operations described in FIG. 1-5.

[0048] The BIOS 336 may determine that a first update flag indicates a pending update of the first logic circuit 342. In some examples, determining that the first update flag indicates a pending update may be performed as described in FIG. 1 , FIG. 2, or a combination thereof. In some examples, the BIOS 336 may determine that a second update flag indicates a second pending update of the second logic circuit 326.

[0049] The BIOS 336 may set an output enable signal 320 to a first enable state. For instance, the BIOS 336 may produce an output enable signal 320 indicating a low value. In some examples described herein, a signal may be referred to as having a “low” value, being in a “low” state, having a “high” value, or being in a “high” state. “Low” and “high” may refer to different signal levels (e.g., different voltage levels, different current levels, or a combination of both), where the low value or low state is at a lower (e.g., smaller, lesser) level than a high value or high state. In some examples, “low” and “high” may refer to different logic levels or binary signal levels (corresponding to a digital logic 0 and digital logic 1 , for instance). In some examples, a low value or low state may correspond to 0 volts (V) (or less than a threshold such as 1.1 V) and a high value or high state may correspond to 3.3 V (or greater than a threshold such as 2.2 V). Other levels or thresholds may be used in some examples. Setting the output enable signal 320 to a first enable signal may cause the bus controller 328 to enable or unlock a bus 332 (e.g., SPI bus). For instance, the bus controller 328 may include a buffer coupled to the bus 332 that is enabled or disabled based on the output enable signal 320 (e.g., enabled (unlocked) with a low value, or disabled (locked) with a high value). In some examples, the BIOS 336 may produce an output enable signal 320 that defaults to disabling or locking the bus 332 (e.g., buffer).

[0050] The BIOS 336 may assert a second reset signal 330 to the second logic circuit 326 to set the second logic circuit 326 to a reset state. In some examples, setting the second logic circuit 326 to the reset state may be performed as described in FIG. 1 , FIG. 2, or a combination thereof.

[0051] The BIOS 336 may send a first selection signal to the bus controller 328 to select the first logic circuit 342. For instance, the BIOS 336 may send the first selection signal to the bus controller 328 via the bus 332. In some examples, selecting the first logic circuit 342 may be performed as described in FIG. 2.

[0052] The BIOS 336 may send a first update to the first memory 340 via the bus 332. In some examples, sending the first update may be performed as described in FIG. 1 , FIG. 2, or a combination thereof. For instance, the BIOS 336 may send the first update to the first memory 340 via the bus 332, the cable 334, the first logic circuit 342, or a combination thereof. In some examples, the cable 334 may cross a hinge interface of the apparatus 338. For instance, the first logic circuit 342 and the first memory 340 may be disposed in a display panel housing of the apparatus 338 and the BIOS 336 may be disposed in a body of the apparatus 338.

[0053] The BIOS 336 may assert a first reset signal 322. Asserting the first reset signal 322 may set the first logic circuit 342 to a reset state. In some examples, setting the first logic circuit 342 to a reset state may be performed as described in FIG. 1 , FIG. 2, or a combination thereof. In some examples, the first reset signal 322 may be carried on a path (e.g., wire) that is included in the cable 334 or that is separate from the cable 334.

[0054] The BIOS 336 may de-assert the second reset signal 330. In some examples, de-asserting the second reset signal 330 (e.g., enabling the second logic circuit 326) may be performed as described in FIG. 2. [0055] The BIOS 336 may send a second selection signal to the bus controller 328 to select the second logic circuit 326. For instance, the BIOS 336 may send the second selection signal to the bus controller 328 via the bus 332. In some examples, selecting the second logic circuit 326 may be performed as described in FIG. 1 , FIG. 2, or a combination thereof.

[0056] The BIOS 336 may send a second update to the second memory 324 via the bus 332. In some examples, sending the second update may be performed as described in FIG. 1 , FIG. 2, or a combination thereof.

[0057] The BIOS 336 may set an output enable signal 320 to a second enable state. For instance, the BIOS 336 may produce an output enable signal 320 indicating a high value. Setting the output enable signal 320 to a second enable state may cause the bus controller 328 to disable or lock a bus 332 (e.g., SPI bus). In some examples, the BIOS 336 may send a lock signal to the bus controller 328 to disable the bus 332. In some examples, locking the bus 332 may be performed as described in FIG. 1 , FIG. 2, or a combination thereof. [0058] FIG. 4 is a flow diagram illustrating an example of a method 400 for determining whether to lock or unlock a bus. The method 400 or a method 400 element may be performed by an electronic device, computing device, or apparatus (e.g., computing device 102, apparatus 338, laptop computer, smartphone, tablet device, etc.). For example, the method 400 may be performed by the computing device 102 described in FIG. 1 or the apparatus 338 described in FIG. 3.

[0059] At 402, an electronic device may determine whether an update is pending. For instance, a BIOS of an electronic device may determine whether an update for instructions (e.g., firmware) of a logic device is pending. In some examples, determining whether an update is pending may be performed as described in FIG. 1 , FIG. 2, FIG. 3, or a combination thereof. In some examples, the electronic device (e.g., BIOS) may check a flag corresponding to a logic device. For instance, the electronic device may request a latest version number of firmware from a remote server. The electronic device may compare the latest version number of firmware to a current version number of the firmware for the logic device of the electronic device. In a case that the current version number is not the same as the latest version number, the electronic device may download the firmware with the latest version number and set an update flag. For instance, the update flag may be a value stored in memory or a register accessible to the BIOS. The BIOS may read the update flag and may determine that an update is pending in a case that the update flag is set.

[0060] In a case that no update is pending, the electronic device may lock the bus at 404. In some examples, locking the bus may be performed as described in FIG. 1 , FIG. 2, FIG. 3, or a combination thereof. For example, the BIOS may set an output enable signal to deactivate a buffer coupled to the bus, thereby locking the bus.

[0061] A boot sequence may be performed for a case where no update is pending in some examples. For instance, the electronic device may power up and determine that no update is pending for a first logic device or a second logic device. The BIOS may assert an output enable signal with a high value to isolate the local memories (e.g., SPI flash devices) of the first logic device and the second logic device. The electronic device may allow the first logic device and the second logic device to initialize using respective firmware in local memories (e.g., flash memory). In some examples, the first logic device may perform a cyclic redundancy check (CRC) of a bitstream. In a case that the CRC of the bitstream is successful, the first logic device may authenticate the bitstream. In a case that the first logic device and the second logic device are initialized successfully, the first logic device and the second logic device may set a status register value(s) indicating successful initialization. The electronic device may check the status register value(s) (at a pre-ready to boot stage, for instance). In a case that the status check is successful, the electronic device (e.g., BIOS) may lock the bus. The first logic device and the second logic device may continue to operate.

[0062] In a case that an update is pending, the electronic device may unlock the bus at 406. In some examples, unlocking the bus may be performed as described in FIG. 1 , FIG. 2, FIG. 3, or a combination thereof. For example, the BIOS may set an output enable signal to activate a buffer coupled to the bus, thereby unlocking the bus. Unlocking the bus may facilitate loading the updated firmware to a corresponding logic circuit.

[0063] Some examples of the techniques described herein may provide a control sequence for updating firmware. In some examples, the control sequence may include isolating a bus. For instance, an SPI bus (or a higher or lower speed bus) may be utilized). In some examples, a BIOS may control the update procedure. For instance, when an update is ready to flash or during a recovery procedure, the BIOS may take control of the bus and drive the firmware images to the hardware devices. The BIOS may control reset signals on hardware devices and initiate the update sequence. For instance, the BIOS may drive reset signals to a first hardware device and to a second hardware device to tri-state their internal buses, allowing the BIOS to become the interface (e.g., SPI) master. The BIOS may drive a first firmware image to a slave interface for a first hardware device and may drive a different second firmware image to a second local memory (e.g., SPI flash NOR device) for a second hardware device. When the firmware images are written to respective local memories, the BIOS may de-assert a reset signal(s) and issue a reboot for the new firmware images to get loaded.

[0064] An update boot sequence may be performed for a case where an update is pending in some examples. For instance, the electronic device may power up and determine that an update is pending for a first logic device or for a second logic device, or that respective updates are pending for the first logic device and the second logic device. The BIOS may assert an output enable signal with a low value to enable a path to local memory (e.g., flash memory) of the first logic device, of the second logic device, or a combination thereof.

[0065] To update the second logic device, in some examples, the electronic device may call a second logic device update driver. The second logic device update driver may be executed to perform the following operations:

[0066] The BIOS may assert a reset signal (with a low value, for instance) to the second logic device. The BIOS may select interface (e.g., SPI) pins on a multiplexer. The BIOS may proceed with a firmware update to local memory (e.g., SPI flash) of the second logic device, where a second selection signal is asserted when commands are sent. After the update is completed, the BIOS may de-assert the second selection signal. The reset signal to the second logic device may remain asserted.

[0067] To update the first logic device, in some examples, the electronic device may call a first logic device update driver. The first logic device update driver may be executed to perform the following operations:

[0068] The BIOS may send a command(s) through an interface (e.g., SPI) with a first selection signal to enable an interface bridge for the first logic device. In some examples, the assertion of the first selection signal (to a low value, for instance) may occur with a quantity of time before activity on an interface (e.g., bus), which may allow a buffer to be active to support the interface activity. The BIOS may proceed with a firmware update to local memory (e.g., SPI flash) of the first logic device. After the update is completed, the BIOS may de-assert the first selection signal. The BIOS may change (e.g., revert) the interface signal on the multiplexer pin(s). The BIOS may de-assert an enable signal. The BIOS may de-assert the reset signal to the second logic device. The BIOS may perform a platform reset that includes power cycling the first logic device and the second logic device. The BIOS may proceed with a boot sequence.

[0069] Some examples of the techniques described herein may be utilized in a case of corrupted instructions (e.g., firmware with an error(s)) stored in logic device memory (e.g., SPI flash). In some examples, the following operations may be performed for a recovery scenario or procedure:

[0070] An electronic device may power up. A BIOS may determine that there is no pending update (e.g., firmware update) for a first logic device or for a second logic device. In some examples, the BIOS may have asserted an output enable signal (in a high state, for instance) to isolate the local memories, but the output enable path is not locked. The BIOS may allow the first logic device and the second logic device to initialize using the respective local memories (e.g., SPI flashes). The electronic device (e.g., BIOS) may check a status register(s) of the first logic device, the second logic device, or a combination thereof. In a case that the status check fails (e.g., the status register indicates that the first logic device or the second logic device did not initialize successfully), the BIOS may initiate a recovery procedure and access a recovery package (e.g., recovery firmware, last firmware version, etc.) from a storage device (e.g., from an ESP on a hard drive). The BIOS may assert a first reset signal and a second reset signal (e.g., may set the first reset signal and the second reset signal to low values). The BIOS may assert the output enable signal (to a low value, for instance).

[0071] The BIOS may perform operations to update the second logic device. For example, the BIOS may assert a second selection signal (to a low value, for instance). The BIOS may proceed to update the local memory (e.g., SPI flash) of the second logic device. After the update is completed, the BIOS may de- assert the second selection signal. The reset signal to the second logic device may remain asserted.

[0072] The BIOS may perform operations to update the first logic device. For example, the BIOS may assert a first selection signal (to a low value, for instance). The BIOS may send a command(s) through an interface (e.g., SPI) to enable an interface bridge (e.g., SPI bridge) for the first logic device. The BIOS may proceed to update the local memory (e.g., SPI flash) of the first logic device. After the update is completed, the BIOS may de-assert the first selection signal. The BIOS may de-assert the output enable signal. The BIOS may de- assert the first reset signal and the second reset signal. In some examples, a platform reset may be performed after the update (e.g., after a recovery procedure). For example, the BIOS may power cycle the first logic device and the second logic device. The electronic device (e.g., BIOS) may proceed with a boot sequence. In some examples, a recovery procedure may be performed without a following platform reset. For instance, the BIOS may allow the first logic device and the second logic device to initialize using the respective local memories (e.g., SPI flashes). The electronic device (e.g., BIOS) may check a status register(s) of the first logic device, the second logic device, or a combination thereof. In a case that the status check passes (e.g., the status register indicates that the first logic device and the second logic device initialized successfully), the first logic device and the second logic device may continue operation. [0073] FIG. 5 is a flow diagram illustrating an example of a method 500 for instruction updates to hardware devices. The method 500 or a method 500 element may be performed by an electronic device, computing device, or apparatus (e.g., computing device 102, apparatus 338, laptop computer, smartphone, tablet device, etc.). For example, the method 500 may be performed by the BIOS 104 of the computing device 102 described in FIG. 1 , by the BIOS 207 described in FIG. 2, or the BIOS 336 of the apparatus 338 described in FIG. 3. In some examples, the method 500 may be performed during a boot sequence.

[0074] At 502, a BIOS may detect a pending firmware update corresponding to a first logic device. In some examples, detecting a pending firmware update may be performed as described in FIG. 1 , FIG. 2, FIG. 3, FIG. 4, or a combination thereof.

[0075] At 504, the BIOS may set an output enable signal to a first enable state. In some examples, setting an output enable signal may be performed as described in FIG. 1 , FIG. 3, FIG. 4, or a combination thereof. For example, the first enable state may be utilized to unlock a bus.

[0076] At 506, the BIOS may set a reset signal corresponding to a second logic device to a first reset state. In some examples, setting a reset signal may be performed as described in FIG. 1 , FIG. 2, FIG. 3, or a combination thereof. [0077] At 508, the BIOS may set a selection signal to a first selection state. In some examples, setting a selection signal may be performed as described in FIG. 1 , FIG. 2, FIG. 3, or a combination thereof. For example, the BIOS may set a selection signal to the first logic device.

[0078] At 510, the BIOS may load firmware to the first logic device. In some examples, the firmware may be loaded to the first logic device as described in FIG. 1 , FIG. 2, FIG. 3, or a combination thereof. For example, the BIOS may send updated firmware to the first logic device. The updated firmware may be stored in a first memory that is coupled to the first logic device.

[0079] At 512, the BIOS may set the output enable signal to a second enable state. In some examples, setting the output enable signal may be performed as described in FIG. 1 , FIG. 2, FIG. 3, or a combination thereof. In some examples, the second enable state may be utilized to lock a bus. For example, the BIOS may set the output enable signal to lock a bus.

[0080] At 514, the BIOS may power cycle the first logic device. In some examples, the BIOS may power cycle the first logic device by power cycling the electronic device, the BIOS, the first logic device, or a combination thereof. For example, the BIOS may remove power from the first logic device to power cycle the first logic device.

[0081] In some examples of the techniques described herein, a hardware device, logic circuit, or logic device may interface with a BIOS with an SPI. Some devices may interface with a BIOS with an I2C or USB interface. In some examples of the techniques described herein, access to non-volatile storage of a hardware device, logic circuit, or logic device may be direct (e.g., a BIOS may have direct access to the non-volatile storage). Some examples of access to non-volatile storage for devices may be indirect. Some examples of the techniques described herein may provide increased firmware updating speed. Some examples of the techniques described herein may have a root of trust in a BIOS or embedded controller. Some examples of the techniques described herein may provide a lock scheme where an interface (e.g., GPIO) from a BIOS or embedded controller to a bus controller is used to lock a bus (e.g., SPI bus) directly.

[0082] Some of the techniques described herein may provide hardware and chipset agnostic approaches to update firmware. Some examples of the techniques described herein may provide hardware approaches that allow a BIOS to grant access for a firmware component to the BIOS or the hardware device. Some examples of the techniques may enable locking down access before exiting a BIOS trust boundary. In a case of a pending firmware update, a BIOS may put the hardware device in a reset state and may allow the BIOS gain access to the firmware component. The BIOS may then directly program the new firmware to the firmware component and perform a reset upon completion of the firmware update. In a case of no pending firmware update, in some examples, the BIOS may lock down the hardware device within a trust boundary so that no access of the firmware component is allowed from a host device (e.g., CPU, OS, etc.). Some of the examples described herein may provide increased speed on the firmware update data path, thereby reducing firmware update time, which may be helpful for relatively large firmware updates.

[0083] As used herein, items described with the term “or a combination thereof” may mean an item or items. For example, the phrase “A, B, C, or a combination thereof” may mean any of: A (without B and C), B (without A and C), C (without A and B), A and B (but not C), B and C (but not A), A and C (but not B), or all of A, B, and C.

[0084] While various examples are described herein, the disclosure is not limited to the examples. Variations of the examples described herein may be within the scope of the disclosure. For example, operation(s), function(s), aspect(s), or element(s) of the examples described herein may be omitted or combined.