PROTECTION

FIELD

Embodiments and examples of the invention are in the field of semiconductors and integrated circuits (ICs) and electrostatic discharge (ESD) protection for semiconductor and IC devices. More particularly, embodiments and examples of the invention relate to insulator-metal transition (IMT) devices for ESD protection.

BACKGROUND

Electrostatic discharge (ESD) protection is a necessary requirement for protecting semiconductor devices and integrated circuits (ICs) and preventing such devices from being severely damaged or destroyed by electrostatic discharge. Typically, input and output (I/O) connections to ICs or device under test (DUT) use a pair of front end diodes as ESD protection devices. A PN diode is configured going in a positive current direction and sinks positive current from a positive pulse discharge to a rail or ground in protecting the DUT. A NP diode is configured going in a negative current direction and sinks negative current from a negative pulse discharge in protecting the DUT. The pair of front end diodes for ESD protection requires space to fabricate the devices. Thus, as ICs become more compact, space requirements for ESD protection become tighter and more restricted.

BRIEF DESCRIPTION OF THE DRAWINGS

The appended drawings illustrate examples and are, therefore, exemplary embodiments and not considered to be limiting in scope.

FIG. 1 is one example of an electrostatic discharge (ESD) protection circuit using an insulator-metal transition (IMT) device.

FIG. 2 is one example of a current (I) versus voltage (V) graph for the IMT device of

FIG. 1.

FIG. 3 is one example of a cross-sectional view of the IMT device of FIG. 1.

FIG. 4 is one exemplary operation for connecting the IMT device in the ESD protection circuit of FIG. 1.

FIGS. 5A-5E are cross-sectional views of examples of IMT devices for the ESD protection circuit of FIG. 1.

FIG. 6 is one example of a data processing or computing system having integrated circuits (ICs) which can use the ESD protection circuit and IMT devices disclosed herein. DETAILED DESCRIPTION

Embodiments and examples are disclosed for insulator-metal transition (IMT) devices for electrostatic discharge (ESD) protection. According to one example, an apparatus includes a device under test (DUT) coupled to a rail and ground; and an insulator-metal transition (IMT) device coupled to the DUT to protect the DUT from electrostatic discharge (ESD). The IMT device includes a selector type of material configured to change from an insulating state to a conducting state with an application of an electric field that generates a voltage exceeding a threshold voltage of the IMT device, wherein the threshold voltage of the IMT device is greater than a power supply voltage to the DUT. Such selector type of material can include a Mott type IMT layer, Peierls type IMT layer, oxide type IMT layer, semiconductor type IMT layer, and a chalcogenide type IMT layer.

In one example, the IMT device is configured to turned on when the threshold voltage of the IMT device is exceeded caused by a positive or negative ESD pulse and sinks a current to ground or a voltage source. In one example, the threshold voltage is greater than a power supply voltage to the DUT. By using the IMT devices disclosed herein, a pair of diodes need not be fabricated in the front end of the DUT for ESD protection thereby freeing up the front end of a device for other purposes.

In the following description, numerous and specific details are set forth, such as device layering, in order to provide a thorough understanding of the examples and embodiments of the present invention. It will be apparent that the examples and embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features, such as specific semiconductor fabrication processes, have not been described so as to avoid obscuring the details of the exemplary embodiments.

ESD Protection Circuit Using an IMT Device Example

FIG. 1 is one example of an electrostatic discharge (ESD) protection circuit 100 using an insulator-metal transition (IMT) device 107 to protect a device under test (DUT) 106 from electrostatic discharge. Referring to FIG. 1, DUT 106 includes an input 109 and an output 110. DUT 106 can be coupled to a rail 102 providing a power supply to the DUT, e.g., V _D voltage, and a ground 104. In one example, DUT 106 can be an equipment under test, unit under test, or a semiconductor device, circuit, integrated circuit (IC) or product having an input. In some examples, DUT 106 and IMT device 107 can be formed on package or semiconductor substrates. Although one DUT 106 and IMT device 107 are shown in FIG. 1, any number of IMT devices 107 can be implemented to provide ESD protection to any number of corresponding DUTs 106. In one example, rail 102 can provide a supply a power source or voltage (VD) to DUT 106 and be grounded by way of ground 104 for ESD circuit 100.

In one example, IMT device 107 is coupled between input 109 of DUT 106 and the ground 104 coupled to DUT 106. In the following examples, IMT device 107 includes a selector material, e.g., a metal-insulator or insulator- metal transition material, which can change from an insulating state to a conducting state with an application of an electric field. For example, when an electric field is applied the selector material for IMT device 106, the selector material can act as a conductor, and the selector material can return to the insulator state when no electric field is applied.

In one example, the selector material for the IMT device 107 is configured to be symmetric with respect to voltage, that is, the selector material switch from an insulating to a conducting state for both positive and negative voltage. Examples of IMT device 107 and exemplary selector materials are disclosed in FIGS. 3 and 5A-5E where a selector material can be an insulator-metal transition (IMT) material as disclosed herein. By using IMT device 107 with an IMT material, a pair of diodes need not be fabricated in the front end freeing up the front end of ESD protection 100 for other purposes.

FIG. 2 is one example of a current (I) versus voltage (V) graph 200 for IMT device 107 of FIG. 1. The IV graph 200 for IMT device 107 of FIG. 2 shows characteristics which are symmetrical in both the positive and negative voltages. For purposes of discussion, the positive voltage is referred to in FIG. 2. In the IV graph, for voltages and current up to VT, IT, IMT device 107 acts like an insulator in which the input 109 to DUT 106 is not affected. High voltage VH and high current ¾ are shown preceding VT and IT for IMT device 107. In one example, the IMT device 107 is configured to have a threshold voltage V _T > a power supply voltage V _D to the DUT 106.

In one example, during a positive ESD pulse above VT, IT _, IMT device 107 turns on and acts as a conductor and sinks any current I ₀ N at input 109 either to ground 104 or rail 102 providing ESD protection to DUT 106. IMT device 107 operates in the same manner in the negative voltage but for a -VT, -IT and -ION providing ESD protection for a negative ESD pulse. In one example, when an ESD event is over, the IMT device 107 returns to an insulator state and no longer affects DUT 106. In one example, for IMT device 107, the VT for the IMT material is higher than the power supply of the circuit, e.g., the power supply or voltage VD provided on rail 102 of FIG. 1, or the maximum voltage for input 109 of DUT 106 can receive in either postive or negative direction. Examples of IMT Devices for ESP Protection

FIG. 3 is one example of a cross-sectional view of an IMT device 300 which can represent the cross-sectional view of IMT device 107 of FIG. 1. Referring to FIG. 3, IMT device 300 includes a top electrode layer 302, an insulator-metal transition (IMT) layer 304, and bottom electrode layer 306. Examples of top and bottom electrode layers 302 and 306 can be any type of metal or conductor such as copper Cu, aluminum Al, platinum Pt or any other type of conductive material, metal or alloy. IMT layer 304 can include any type of selector material can change from an insulating state to a conducting state with an application of an electric field on top and bottom electrode layers 302 and 306. Examples of types of IMT materials for IMT layer 304 can include Mott type IMT layer, Peierls transition type IMT layer, oxide type IMT layer, and semiconductor compositional type IMT layer, and compositional chalcogenide type IMT layer as disclosed in FIGS. 5A-5E which can have varying VT and IT for IMT device 300. IMT layer 304 can include more than one layer including multiple types or combinations of selector materials. In one example, top and bottom electrode layers 302 and 306 and IMT layer 304 can be formed in package or semiconductor substrates using standard processing and layering techniques.

FIG. 4 is one exemplary operation 400 for connecting the IMT device 300 of FIG. 3 in the ESD protection circuit of FIG. 1. At step 402, top electrode layer 302 of FIG. 3 can connect or be coupled to input 109 of DUT 106 in FIG. 1. At step 404, bottom electrode layer 304 can connect or be coupled to ground 104 coupled to DUT 106. In one example, for such a connection configuration, when a positive ESD pulse is applied to top and bottom electrode layers 302 and 306 and exceeds the VT, IT for IMT layer 304, IMT device 300 turns on and acts as a conductor and sinks any current I ₀ N at input 109 either to ground 104 or rail 102 providing ESD protection to DUT 106. IMT device 300 also operates in a similar manner for a negative ESD pulse and sinks any negative current -ION at input 109 either to ground 104 or rail 102 providing ESD protection to DUT 106.

FIGS. 5A-5E are cross-sectional views of examples of IMT devices 500, 510, 520, 530 and 540 with varying types of IMT layers. In the following examples of FIGS. 5A-5E, IMT layers 504, 514, 524, 534 and 544 can include selector materials, which can change from an insulating state to a conducting state with an application of an electric field to respective top and bottom electrodes.

Referring to FIG. 5A, IMT device 500 includes top and bottom electrode layers 502 and 506 and a Mott type IMT layer 504 formed in between electrode layers 502 and 506. In one example, Mott type IMT layer 504 includes Mott insulators which are a class of materials which can conduct current under conventional band theories, but also act as insulators when measured particularly at low temperatures. This effect can be attributed to electron-electron interactions, which are not considered in conventional band theory. Examples of materials for Mott type IMT layer 504 can include vanadium oxide V0 ₂ , samarium nickel oxide SmNi0 ₃ , titanium oxides T1 ₃ O5 and Ti ₂ 0 ₃ , and lanthanum cobalt oxide LaCo0 ₃ , and niobium oxide NbQ?.

Referring to FIG. SB, IMT device 510 includes top and bottom electrode layers 512 and 516 and a Peierls type IMT layer 514 formed in between electrode layers 502 and 506. In one example, Peierls type IMT layer 514 includes Peierls type materials, which can include a distortion of a periodic lattice of a one-dimensional crystal. Examples of materials for Peierls type IMT layer 514 can include niobium oxide Nb0 ₂ . Referring to FIG. 5C, IMT device 520 includes top and bottom electrode layers 522 and 526 and oxide type IMT layer 524 formed in between electrode layers 522 and 526. In one example, oxide type IMT layer 524 includes oxide type materials, examples of which can include hafnium oxide Hf0 ₂ , titanium oxide T1O2, and silicon dioxide Si02. In one example, for IMT device 520 top and bottom electrode layers 522 and 526 can be fast diffusers in oxide such as copper Cu, silver Ag, and nickel Ni. Such fast diffusers can create highly recombination-active precipitates in silicon Si.

Referring to FIG. 5D, IMT device 530 includes top and bottom electrode layers 532 and 536 and semiconductor type IMT layer 534 formed in between electrode layers 532 and 536. In one example, semiconductor IMT layer 524 includes silicon Si and germanium Ge and top and bottom electrode layers 532 and 536 being fast diffusers such as copper Cu, silver Ag, and nickel Ni in silicon Si and germanium Ge. Referring to FIG. 5E, IMT device 540 includes top and bottom electrode layers 542 and 546 and chalcogenide type IMT layer 544 formed in between electrode layers 542 and 546. Chalcogenide type IMT layer 544 can include a metal alloy having a chalcogen, which are elements in group 16 of the periodic table. In one examples, materials for chalcogenide type IMT layer 544 can include tellurium Te, selenium Se, and sulfur

S and top and bottom electrode layers 542 and 546 being fast diffusers such as copper Cu, silver Ag, and nickel Ni in silicon Si and germanium Ge.

Example Computing System for ESP Protection with IMT Devices FIG. 6 is a schematic of an exemplary computing or data processing system 600 having electronic packages or integrated circuits (ICs) having the IMT devices disclosed herein for ESD protection. As shown, computing or data processing system 600 (also referred to as electronic system 600) can include and utilize integrated circuit (die) 610 and 611, which can be electronic packages, having ESD protection using IMT devices as disclosed in FIGS. 1-5E. Examples of electronic system 600 include a mobile device such as a netbook computer or a wireless smart phone, a desktop computer, a hand-held reader, a server system, or a supercomputer or high- performance computing system.

In one example, electronic system 600 is a computer system that includes a system bus 620 to electrically couple the various components of electronic system 600. System bus 620 can be a single bus or any combination of busses according to various embodiments. Electronic system 600 includes a voltage source 630 that provides power to integrated circuit dies 610 and 611. In some examples, voltage source 630 supplies current to integrated circuit dies 610 and 611 through system bus 620. Voltage source 630 can provide power to other components such as passive devices 655, input devices 670, display 650, audio devices 660, and memory devices 640 including memory devices 642, 644, 646 and 648.

Integrated circuit dies 610 and 611 are electrically coupled to system bus 620 and includes any circuit, or combination of circuits on one or more silicon dies or tiles. In one example, integrated circuit die 610 includes a processor 612 that can be of any type. As used herein, processor 612 may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, CPU or another processor. In one example, SRAM embodiments are found in memory caches of the processor. Other types of circuits that can be included in integrated circuit 610 are a custom circuit or an application- specific integrated circuit (ASIC), such as communications circuit 614 for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems, or a communications circuit for servers. In one example, integrated circuit 610 includes on-die memory 616 such as static random-access memory (SRAM). In another example, integrated circuit 610 includes embedded on-die memory 616 such as embedded dynamic random-access memory (eDRAM).

In one example, integrated circuit 610 is complemented with a subsequent integrated circuit 611 having similar components such as on-die memory, SRAM, and eDRAM 617, processor 613, and communications circuit 615. In one example, integrated circuit dies 610 and 611 include ESD protection circuits with IMT devices disclosed herein to protect integrated circuit dies 610 and 611 and internal components from ESD. For example, an ESD protection circuit with an IMT device is provided for input or output connections for the integrated circuit dies 610 or 611 or components for integrated circuit dies 610 or 611. In other examples, ESD protection circuits with IMT devices disclosed herein can be provided for any electronic package implemented in electronic system 600.

In one example, electronic system 600 also includes an external memory 640 that in turn may include one or more memory elements suitable to the particular application, such as a main memory 642 in the form of RAM, one or more hard drives 644, and/or one or more drives that handle removable media 646, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory 640 may also be embedded memory 948 such as the first die in a die stack, according to an embodiment.

In one example, electronic system 600 also includes a display device 650, an audio output 660. In one example, electronic system 600 includes an input device such as a controller 670 that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system 600. In an embodiment, an input device 670 is a camera. In an embodiment, an input device 670 is a digital sound recorder. In an embodiment, an input device 770 is a camera and a digital sound recorder.

As shown herein, integrated circuit dies 610 or 611 or other electronic package components shown in FIG. 6 can be implemented in a number of different embodiments having ESD protection circuits with IMT devices as disclosed in FIGS. 1-5E for electronic system 600. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the several disclosed electronic package substrates with integrated lithium ion TFBs. A foundation substrate may be included, as represented by the dashed line of FIG. 6. Passive devices 655 may also be included, as is also depicted in FIG. 6.

Examples and embodiments of the present invention include package-integrated thin film lithium ion battery and methods for fabricating the same are described.

One example is an apparatus including a device under test (DUT) coupled to a rail and ground, an insulator-metal transition (IMT) device coupled to the DUT to protect the DUT from electrostatic discharge (ESD). The IMT device is configured to change from an insulating state to a conducting state with an application of an electric field that generates a voltage exceeding a threshold voltage of the IMT device. The threshold voltage of the IMT device is greater than a power supply voltage to the DUT.

In one example, the IMT device is turned on when the threshold voltage of the IMT device is exceeded caused by a positive or negative ESD pulse and sinks a current to ground or a voltage source.

In one example, the IMT device includes a top electrode layer, a bottom electrode layer, and an insulator-metal transition material layer formed in between the top and bottom electrode layers. In one example, the top electrode layer of the IMT device is coupled to an input of the DUT and the bottom electrode layer is coupled to the ground for the DUT.

In one example, insulator-metal transition material layer includes at least one of a Mott type IMT layer, Peierls type IMT layer, oxide type IMT layer, semiconductor type IMT layer, and a chalcogenide type IMT layer.

In one example, the Mott type IMT layer includes vanadium oxide V0 ₂ , samarium nickel oxide SmNiOs, titanium oxides T1 ₃ O ₅ and Ti ₂ (¾, and lanthanum cobalt oxide LaCo0 ₃ , and niobium oxide Nb0 ₂ .

In one example, the Peierls type IMT layer includes niobium oxide Nb0 ₂ .

In one example, the oxide type IMT layer includes hafnium oxide Hf0 ₂ , titanium oxide

T1O ₂ , and silicon dioxide Si02, and wherein the top and bottom electrode layers include fast diffusers including copper Cu, silver Ag, and nickel Ni.

In one example, the semiconductor type IMT layer includes silicon Si and germanium Ge, wherein the top and bottom electrode layers include fast diffusers including copper Cu, silver Ag, and nickel Ni in the silicon Si or germanium Ge.

In one example, the chalcogenide IMT layer includes a metal allow including a chalcogen including tellurium Te, selenium Se, and sulfur S, and wherein the top and bottom electrode layers include fast diffusers including copper Cu, silver Ag, and nickel Ni.

One example of an electrostatic discharge (ESD) protection device includes top and bottom electrode layers, and a selector layer formed between the top and bottom electrode layers. The top electrode layer is coupled to an input of a device under test (DUT) and the bottom electrode layer is coupled to a ground for the DUT. The selector layer is configured to change from an insulating state to a conducting state with an application of an electric field that generates a voltage exceeding a threshold voltage of the selector layer to provide ESD protection to the DUT. The threshold voltage is greater than a power supply voltage to the DUT.

In one example, the ESD protection device turns on when the threshold voltage of the IMT device is exceeded caused by a positive or negative ESD pulse and sinks a current to ground or a voltage source.

In one example, the selector tor layer includes an insulator-metal transition (IMT) material.

In one example, the IMT material includes at least one of vanadium oxide V0 ₂ , samarium nickel oxide SniNi0 ₃ , titanium oxides T1 ₃ O5 and Ti ₂ 0 ₃ , lanthanum cobalt oxide LaCoOs, niobium oxide Nb0 ₂ , hafnium oxide Hf0 ₂ , titanium oxide T1O2, silicon dioxide Si02, silicon Si, germanium Ge, tellurium Te, selenium Se, and sulfur S. In one example, the top and bottom electrode layers include fast diffusers including copper Cu, silver Ag, and nickel Ni.

One example of a method includes connecting a top electrode of an insulator-metal transition (IMT) device to an input of a device under test (DUT); and connecting a bottom electrode of the IMT device to a ground for the DUT. The IMT device also includes an IMT layer that is configured to change from an insulating state to a conducting state with an application of an electric field that generates a voltage exceeding a threshold voltage of the IMT device providing electrostatic discharge (ESD) protection to the DUT. The threshold voltage for the IMT device is greater than a power supply voltage to the DUT.

In one example, the IMT device is turned on when the threshold voltage of the IMT device is exceeded caused by a positive or negative electrostatic discharge (ESD) pulse; and sinks a current to ground or a voltage source when the IMT device is turned on in providing ESD protection to the DUT.

On example includes an electronic system including a system bus, and a plurality of integrated circuits coupled to the system bus. Each integrated circuit includes at least one electrostatic discharge (ESD) protection circuit. The EST protection circuit includes an insulator-metal transition (IMT) device configured to change from an insulating state to a conducting state with an application of an electric field that generates a voltage exceeding a threshold voltage of the IMT device. The threshold voltage of the IMT device is greater than a power supply voltage to the integrated circuit.

In one example, the IMT device is turned on when the threshold voltage of the IMT device is exceeded caused by a positive or negative ESD pulse and sinks a current to ground or a voltage source.

In one example, the IMT device includes a top electrode layer, a bottom electrode layer, and an insulator-metal transition material layer formed in between the top and bottom electrode layers.

In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.