Title:
INTEGRATED CIRCUIT ARRANGEMENT COMPRISING ISOLATING TRENCHES AND A FIELD EFFECT TRANSISTOR, AND ASSOCIATED PRODUCTION METHOD
Document Type and Number:
WIPO Patent Application WO2004102667
Kind Code:
A3
Abstract:
The invention relates to a memory circuit arrangement comprising a memory cell region (12) that contains a plurality of memory cell transistors (T00 to T21). The memory cell transistors (T00, T01) in a column are selected by means of a selection transistor (TD0). Said selection transistor (TD0) is a triple control-region transistor, whose control region extends as far as isolation trenches (G0, G1). The latter (G0, G1) also isolate the memory cell transistors (T00, T10) of different columns in the memory cell field (12). Said arrangement increases the level of integration.
Inventors:
KAKOSCHKE RONALD (DE)
SCHULER FRANZ (DE)
SCHULER FRANZ (DE)
Application Number:
PCT/EP2004/050718
Publication Date:
January 06, 2005
Filing Date:
May 05, 2004
Export Citation:
Assignee:
INFINEON TECHNOLOGIES AG (DE)
KAKOSCHKE RONALD (DE)
SCHULER FRANZ (DE)
KAKOSCHKE RONALD (DE)
SCHULER FRANZ (DE)
International Classes:
H01L21/336; H01L21/8247; H01L27/115; (IPC1-7): H01L27/115; H01L21/8247; H01L21/336; H01L29/788
Foreign References:
| EP0282716A1 | 1988-09-21 | |||
| US4945069A | 1990-07-31 | |||
| US6033959A | 2000-03-07 | |||
| US20020011612A1 | 2002-01-31 |
Other References:
KATSUHIKO HIEDA ET AL: "EFFECTS OF A NEW TRENCH-ISOLATED TRANSISTOR USING SIDEWALLL GATES", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE INC. NEW YORK, US, vol. 36, no. 9 - I, 1 September 1989 (1989-09-01), pages 1615 - 1619, XP000087125, ISSN: 0018-9383
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