The invention relates to a novel integrated circuit (IC) chip assembly and method of assembling an IC chip with external circuitry.

According to a first aspect of the invention there is provided an integrated circuit assembly comprising a discrete electrical component and a chip having a layered structure that defines integrated circuitry including processing circuitry for processing data received from the discrete electrical component; wherein the layer structure of the chip includes: first and second outer layers providing respective first and second electrical contacts by which the discrete electrical component makes electrical connection with the chip; and multiple inner layers between the first and second outer layers that include: a partitioned semiconductor layer defining multiple regions that are each electrically isolated from one another by a partition; wherein one or more of the multiple regions provide a substrate for integrated electronic devices of the processing circuitry; one or more device layers in and/or on the substrate to provide the integrated electrical devices of the processing circuitry; a trace layer lying between the partitioned semiconductor layer and the first outer layer, the trace layer being electrically conductive and patterned to provide conductive features for electrically interconnecting the integrated electronic devices of the processing circuitry, and the processing circuitry to the first electrical contact; in which the layer structure defines bypass circuit including a vertical bipolar junction transistor (BJT) to provide electrical connection between the second contact and the processing circuitry via the trace layer; and wherein another of the multiple regions of the semiconductor layer provide a base region of the vertical BJT.

According to a second aspect of the invention there is provided an integrated circuit chip having a layered structure that defines an integrated circuit including processing circuitry for processing data received from a discrete electrical component connected to it; wherein the layer structure of the chip includes: first and second outer layers providing respective first and second electrical contacts by which the discrete electrical component makes electrical connection with the chip; and multiple inner layers between the first and second outer layers that include: a partitioned semiconductor layer defining multiple regions that are each electrically isolated from one another by the partition; wherein one or more of the regions provide a substrate for integrated electronic components of the processing circuitry; one or more device layers in and/or on the substrate to provide the electrical devices of the processing circuitry; a trace layer lying between the semiconductor layer and the first outer layer, the trace layer being electrically conductive and patterned to provide conductive features for electrically interconnecting the integrated electronic devices, and for connecting the processing circuitry to the first electrical contact; in which the layer structure defines circuitry including a vertical bipolar junction transistor (BJT) to provide electrical connection between the second contact and the processing circuitry via the trace layer; and wherein another of the multiple regions of the semiconductor layer provide a base region of the vertical BJT.

The following may apply to either aspect of the invention.

Through this arrangement signals received at the second contact, pass through the base of the vertical BJT, e.g. from the collector to the emitter, thus connecting the second contact to the trace layer and thus to processing circuitry, by-passing the substrate, without the need for additional interconnection layers or metallic vias between the outer layers.

Consequently, the layer structure may be constructed using metallic layers only to provide the first and second contacts.

The trace layer may be comprised from doped polysilicon. Alternatively, though less preferred, it may be comprised from a metal.

The processing circuitry may comprise a rectifier circuit, and the bypass circuit is arranged to pass an alternating current signal received at the second contact to the rectifier circuit. The multiple inner layers between the first and second outer layers may further include a collector layer comprised from a semiconductor material; the collector layer lying between the partitioned semiconductor layer and the second outer layer, and in direct contact with the partitioned semiconductor layer so as to provide a collector region of the vertical BJT.

The collector may be in direct contact with the second contact in addition to being in direct contact with the partitioned semiconductor layer. As such the collector of the BJT may provide an input and/or output of the chip.

The bypass circuit may include a first diode positioned within the bypass circuit between a base of the transistor and the second contact, and which is implemented by a junction between a further region of the multiple regions of the partitioned semiconductor layer and the collector layer, and which connects to the base region through the trace layer. Through this arrangement a signal is present at the second contact produces a leakage current through the diode switching the vertical BJT ON.

The bypass circuit may include a second diode positioned within the bypass circuit between the second contact and the processing circuitry, and which is implemented by a junction between another region of the multiple regions of the partitioned semiconductor layer and the collector layer, and which connects to the processing circuitry through the trace layer. Through the combination of the vertical BJT and second diode in parallel the by-pass circuit is able to carry alternating current signals between the discrete electrical component and the rectifier circuit.

The layer structure may be arranged such that multiple of the multiple regions provide separate base regions for respective multiple separate vertical BJTs of the integrated circuitry, and in which the collector layer provides a common collector for the multiple vertical BJTs.

The regions of the partitioned semiconductor layer may be partitioned from one another by one or more trenches that extend wholly through the semiconductor layer, and optionally into the collector layer. The integrated circuit assembly may comprise an RFID assembly and the discrete electrical component may comprise an antenna.

Where the layer structure is arranged such that another of the multiple regions provides a separate base region of a second vertical BJT of the integrated circuitry, and in which the collector layer provides a collector for the second multiple vertical BJT, the second vertical BJT may provide connection between an output of the processing circuitry and the antenna through the second contact.

According to a third aspect of the invention there is provided an integrated circuit assembly comprising a discrete electrical component and a chip having a layered structure that provides an integrated circuit; wherein the chip is surface mounted onto a face of the discrete electrical component such as to provide electrical interconnection between the electrical component and the integrated circuit, characterised in that the chip is oriented relative to the discrete electrical component such that the layers of the layered structure are oriented non-parallel with the face o the discrete electrical component.

An integrated circuit assembly may comprise a first metallic layer provides a first face of the chip, and a second metallic layer provides a second face of the chip, the second face facing a direction opposite to the first face; and in which the first and second metallic layers provide electrical contacts with the electrical component.

The first metallic layer may provide substantially the whole of the first face of the chip and the second metallic layer may provide substantially the whole of the second face of the chip

The discrete electrical component may comprise a substrate carrying an electrically conductive trace, wherein the trace comprises one or more sections that extend from one side of the chip to another side of the chip passing directly underneath the chip.

The discrete electrical component may comprise an antenna.

According to a fourth aspect of the invention there is provided an electrical circuit for implementation in an integrated circuit chip providing connection between a first terminal of the chip and a processing and recertify circuitry of the chip in order to carry an AC signal between the first terminal and the processing and recertify circuitry; wherein the electrical circuit comprises: a bipolar junction transistor (BJT) arranged so that: its collector connected to the first terminal; its emitted is connected to a first input of a rectifier circuit of the processing and rectifying circuitry;its base is connected to the first terminal though a first diode; the circuit also comprising a second diode connected between the first terminal and the first input of a rectifier circuit, across the BJT; wherein the first diode is selected such that when the voltage at the first terminal is positive the first diode is reversed biased and allows a leakage current through it sufficient to turn the transistor ON.

The invention will now be described by way of example with reference to the following figures in which:

Figure 1A is simplified schematic section view of a radio frequency identification (RFID) assembly;

Figure IB is a simplified schematic plan view of the RFID assembly;

Figure l is a simplified circuit diagram of the integrated circuitry of the chip;

Figure 3 is a simplified schematic section of the chip; and

Figure 4 illustrates a simplified schematic of a variant RFID assembly.

Figure 1A shows, schematically, a section view through a passive RFID device 1. The RFID device 1 comprises an antenna 10 on which is mounted a semiconductor chip 20 providing integrated circuitry that carries out storage and processing functions of the device 1.

The antenna 10 comprises a substrate 11 of an electrically insulating material, such as a polyester. The substrate 11 may take the form of a thin flexible film. The substrate 11 carries an electrically conductive track 12 that extends between contact pads 13A 13B to receive an alternating current signal outputted from the chip 20 and propagate corresponding radio frequency signals into space and vice versa. The substrate 11 also includes a protective, electrically insulating, coating 14 that lies over the conductive track 12. Windows in the coating 14 leave the contact pads 13 exposed for connection to the chip 20.

The semiconductor chip 20 has a stacked multi-layered structure that forms the integrated electrical components and traces of the integrated circuitry.

The semiconductor chip 20 is mounted onto the substrate 11 in an orientation such that layers 21 of the stacked multi-layered structure lie in planes that are substantially orthogonal to a surface 15 of the antenna 10 provided by the coating 14 against which the chip 20 is mounted. Expressed another way, the axis x-x (stacking axis) about which the layers 21 of the chip 20 are stacked, lie substantially parallel to the surface 15.

With this arrangement both outer layers 21 A, 2 IB of the stack, conventionally the ‘bottom’ and ‘top’ layers, have principle faces 21AF 21BF that are exposed.

Taking advantage of this arrangement, the outer layers 21 A 21B are metallic to provide contacts for connection to the antenna 10. The chip 20 is positioned such that the first outer layer 21A lies immediately adjacent a first of the antenna contact pads 13A and the second outer layer 2 IB lies immediately adjacent a second of the antenna contact pads 13B. A conventional bonding technique, e.g. soldering, is used to mechanically fasten and electrically connect the outer layers 21A 21B of the chip 20 to the contact pads 13 A 13B of the antenna 10.

The track 12, which takes a circuitous route between the contact pads 13, comprises one or more sections 13C that extend from one side of the chip to an opposite side of the chip by passing directly underneath the chip 20 as shown in Fig IB. Where the tracks pass under the chip 20, they remain electrically isolated from the chip 20 by the coating 14.

With reference to Figure 2, the integrated circuitry of the microchip 20 includes a power circuit 30, a rectifier circuit 31 having first and second alternating current (AC) inputs 31 A, 3 IB and a direct current (DC) output 31C, and RFID circuitry 32. The two inputs 31 A 3 IB of the rectifier circuit 31 are connected to the respective two antenna terminals 13 A 13B of the antenna 10. The first input 31 A is connected to the antenna terminal via a power circuit 30.

The power circuit 30 carries AC signals between the antenna 10 and the first input 31 A of the rectifier circuit 31 so as to allow AC signals to be carried there between. The power circuit 30 takes a form that can be implemented by the layer structure of the chip 20 to route the AC signals from the first contact 21 without need of metal layers within the layered structure in addition to those used to provide contacts 21 A 21B.

The power circuit 30 comprises a bipolar junction transistor 30A. The collector of the transistor 30A is connected to the antenna 10 and the emitter to the first input 31 A. The base of the transistor 30A is also connected to the antenna 10 through a first diode 30B with the first diode’s 30A anode connected to the base of the transistor 30A. A second diode 30C is arranged across the transistor 30A between the antenna 10 and the first input 31 A of the rectifier circuit 31.

When the AC voltage at the collector is positive, a leakage current through the reverse biased diode 30B switches the transistor ON allowing current to flow between the collector emitter terminals of the transistor to input 31 A. When the AC voltage at the collector is negative, diode 30C is forward bias allowing current to flow from the first input 31 towards the antenna 10.

The rectifier circuit 31 provides a modulated direct current (DC) signal at its output 31C which is received at an input 32A of RFID circuitry 32. The modulated direct current (DC) is used by the RFID circuitry 32 both to power the circuitry 32 and as a data input signal as is conventional in passive RFID devices.

The RFID circuitry 32 provides the conventional functions of storing and processing data, and modulating and demodulating signals. An RF output 32B of the RFID circuitry 32 is connected to the antenna 10 through a transistor 33 which modulates the impedance across the antenna 10 in order to transmit RF signals through the antenna 10. As the particular functioning and features of the RFID circuitry 32 can be conventional and are not pertinent to the present invention, they are not described here in further detail.

Like the power circuitry 30, the transistor 33 is a means that can be implemented by the layer structure of the chip 20 to connect the output of the RFID circuitry 32 to the first contact 21 without incorporating additional metallic layers into the structure.

Figure 3 is a simplified schematic illustrating an example stacked layer structure for the chip 20 to provide the integrated circuitry of Fig 2 and that allows for the provision of contacts on the outer layers of the stack. The structure is comprised from layers of different semiconductor materials, e.g. n and p doped silicon, polysilicon, metal as well as one or more electrical insulating layers, e.g. silicon oxide. The structure is fabricated using techniques known to those skilled in the art as well as those described in W02020074930.

The structure comprises a monocrystalline N type layer 200 on which is deposited a monocystalline P type layer 201. Both the N type layer 200 and P type layer 201 may be grown using an epitaxy process.

Extending through the P layer 201 are trenches 202 formed by etching, e.g. by a deep reactive ion etching (DRIE) process such as the Bosch process. The trenches 202 have a depth sufficient to extend entirely through the P layer 201 and into the N layer 200. This ensures each trench 202 extends through the laterally extending PN junction between the N layer 201 and P layer 202. The trenches 202 act to subdivide the P layer 202 into a plurality of regions 201 A, 20 IB, 201C, 20 ID each electrically isolated from one another by the trenches 202. Each of a number of P regions 20 IB (only one shown in Fig 3) provides separate base regions for separate vertical bipolar junction NPN transistors in the circuitry. For example, to implement the circuit of Fig 2, three separate regions 201B are needed to implement the bipolar NPN transistor 30A in the power circuit 30, the NPN transistor 3 ID in the bridge 31 and the NPN transistor 33 at the RFID output 32B. Fig 3 shows the base region for the transistor 30A. One or more further regions 201 A may be included for any NPN transistors needed in the RFID circuitry 32.

One or more separate regions 201C provide a substrate for the electronic devices (other than those implemented by vertical NPN transistors) of the rectifier circuit 31 and RFID logic circuitry 32.

Regions 201A and 201D are used to provide respective diodes 30B and 30C of circuit 30 of Fig 2 as further detailed below.

A highly doped N region 205 is formed in each region 20 IB to provide respective emitter regions of the separate vertical transistors.

Additionally, multiple separate weaker doped N regions 206 (only two shown) are formed in each region 201C to provide base regions for lateral PNP transistors and other electronic components, e.g. diodes, of the RFID circuitry logic and the rectifier circuit (see items 154 of Fig 3 in W02020074930 and associated text that describes in greater detail an example process for forming the circuitry).

An electrically insulating silicon dioxide layer 207 lies over (e.g. substantially the entire) die and which fills the trench 202. A pattern of windows 208 are formed in the oxide layer 207 to expose portions of the N regions 205, 206 and of the P regions 201 A, 201B, 201D.

A patterned layer of doped polysilicon 209 is provided over the oxide layer 207. The polysilicon pattern layer provides conductive traces of the integrated circuitry, including: between the integrated electrical devices of rectifier circuit 31 and RFID circuitry 32, between the transistor 30A and diode 30C and the rectifier circuit 31; between the second input 3 IB of the rectifier circuit and the first contact 2 IB for connection to the antenna 10; and between the diode 3 OB and transistor 30 A.

Contact between the polysilicon traces and the N regions 205,206 and the P regions 201A, 201B, 201D is made through the windows 208.

Over the polysilicon layer 209 is provided a second electrically insulating silicon dioxide layer 210 within which one or more contact windows 211 are formed to connect the desired traces provided by the polysilicon layer 209 with a metal contact layer 212 which lies on the second silicon oxide layer 210 and which provides one of the chip contacts 2 IB with the antenna. A second metallic layer 213 provided on the underside (from the view point of Fig 3) of the N type layer 200 provide the other chip contact 21A.

The N layer 200, region 20 IB and N region 205 provide the respective collector, base and emitter regions of the transistor 30A. The emitter is connected to the rectifier circuit 31 through the polysilicon 209. The collector is connected to the antenna 10 through the contact 21 A.

Layer 200 provides a common collector for each vertical NPN transistor within the circuit, e.g. in this example each of transistors 30A, 33 and 3 ID.

Diode 30B is provided through the junction between the N layer 200 and region 201 A. The anode of diode 30B connects to the base of the transistor 30A via a connection provided by the polysilicon layer 209.

Diode 30C is provided through the junction between the N layer 200 and region 201D. A window 208 provides connection between the anode of diode 30C and the polysilicon track 209 that connects between the emitter of the transistor 30A and the rectifier input 31 A. Figure 4, shows a variant RFID assembly which an alternative mounting arrangement between the chip and the antenna. In this example the antenna is a spiralled metal wire. This arrangement is suitable for being interred within a carrier body. Although the invention has been described in relation to an RFID assembly, it is equally applicable to other devices where it is desired to mount a chip onto external circuitry, particularly passive devices where a data signal and power supply are provided through the same chip contacts.

It will be appreciated that the circuitry could instead be implemented using vertical PNP transistors by reversing the N and P layers.

With reference to Fig 1, the chip is favourably mounted on its side such that the layers run 90 degrees to the surface 15 as this is an easy arrangement to use. Nevertheless, the chip may be mounted at other angles such that the layers run non-parallel with surface 15.