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Title:
INTEGRATED CIRCUIT DEVELOPMENT SYSTEM
Document Type and Number:
WIPO Patent Application WO2004114166
Kind Code:
A3
Abstract:
Embodiments of the invention include a system for an integrated circuit development. Elements of the development system include hardware and software objects. These objects can be instanced, ordered, parameterized, and connected in a software environment to implement different functions. Once in software, the description defines the topology and the properties of a set of objects and hence the overall function. These objects are hierarchically composed from a set of primitive objects. By using a piece of hardware that can model any primitive object set as pre established encapsulated hardware objects, the topology and properties define a piece of hardware that can perform the desired, implemented, functions. Using embodiments of the invention, circuit designers can design hardware systems with little or no knowledge of hardware or hardware design, requiring only a high-level software description.

Inventors:
JONES ANTHONY MARK (US)
WASSON PAUL M (US)
Application Number:
PCT/US2004/019510
Publication Date:
December 29, 2005
Filing Date:
June 18, 2004
Export Citation:
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Assignee:
AMBRIC INC (US)
JONES ANTHONY MARK (US)
WASSON PAUL M (US)
International Classes:
G06F5/08; G06F17/50; (IPC1-7): G06F17/50; G06F5/06
Domestic Patent References:
WO2002080044A22002-10-10
WO1999039288A21999-08-05
Foreign References:
US6308229B12001-10-23
Other References:
LU ET.AL.: "Performance Analysis and Efficient Implementation of Latency Insensitive Systems", TECHNICAL REPORT TR-ECE03-06, March 2003 (2003-03-01), SCHOOL OF ELECTRICAL & COMPUTER ENGINEERING, PURDUE UNIVERSITY, XP002337839, Retrieved from the Internet [retrieved on 20050722]
CHELCEA T ET AL: "A low-latency FIFO for mixed-clock systems", IEEE COMPUT SOCIETY, 27 April 2000 (2000-04-27), Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era, pages 119 - 126, XP010379677
CARLONI L P ET AL: "A methodology for correct-by-construction latency insensitive design", COMPUTER-AIDED DESIGN, 1999. DIGEST OF TECHNICAL PAPERS. 1999 IEEE/ACM INTERNATIONAL CONFERENCE ON SAN JOSE, CA, USA 7-11 NOV. 1999, PISCATAWAY, NJ, USA,IEEE, US, 7 November 1999 (1999-11-07), pages 309 - 315, XP010363870, ISBN: 0-7803-5832-5
RUIBING LU ET AL: "Performance optimization of latency insensitive systems through buffer queue sizing of communication channels", IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN. ICCAD 2003. IEEE/ACM DIGEST OF TECHNICAL PAPERS. SAN JOSE, CA, NOV. 9 - 13, 2003, IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, NEW YORK, NY : ACM, US, 9 November 2003 (2003-11-09), pages 227 - 231, XP010677157, ISBN: 1-58113-762-1
CASU M R ET AL: "Issues in implementing latency insensitive protocols", DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2004. PROCEEDINGS FEB. 16-20, 2004, PISCATAWAY, NJ, USA,IEEE, vol. 2, 16 February 2004 (2004-02-16), pages 1390 - 1391, XP010684987, ISBN: 0-7695-2085-5
CHANDRANMENON G P ET AL: "RECONSIDERING FRAGMENTATION AND REASSEMBLY", PROCEEDINGS OF THE 17TH ANNUAL ACM SYMPOSIUM ON PRINCIPLES OF DISTRIBUTED COMPUTING.PODC 1998. PUERTO VALLARTA, MEXICO, JUNE 28 - JULY 2, 1998, ACM SIGACT - SIGMOD SYMPOSIUM ON PRINCIPLES OF DISTRIBUTED COMPUTING, NEW YORK, NY : ACM, US, 28 June 1998 (1998-06-28), pages 21 - 29, XP002921718, ISBN: 0-89791-877-7
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