BACKGROUND ART There is a constant drive in the semiconductor industry to increase the speed at which integrated circuit devices operate. This drive is fueled by consumer demand for faster and more efficient products made using various integrated circuit devices. Modem integrated circuit devices are comprised of thousands of semiconductor devices, e. g., transistors, formed above a semiconducting substrate. Multiple levels of conductive interconnections are required to electrically interconnect these discrete semiconductor devices. In one embodiment, these intercon- nections are accomplished by forming a plurality of conductive lines in a layer of dielectric material at one level, and forming a plurality of conductive plugs in another layer of dielectric material at an adjacent level. The conductive plugs are used to connect the various lines that exist in alternating layers. Of course, other forms of conductive elements. such as a conductive island, may be formed at various levels on an integrated circuit device.

One factor that tends to affect the speed at which electrical signals may traverse along these conductive lines is the capacitance between these lines, i. e., the line-to-line capacitance. All other things being equal, the greater the line-to-line capacitance between adjacent conductive lines, the slower the speed at which electrical signals will traverse along one of the conductive lines. Similarly, all other things being equal, the greater the line- to-line capacitance, the more power the device, e. g., a microprocessor, will consume when operating. This is because more energy is required to charge the structure having the higher capacitance. Such increased power consumption may also result in excessive heat buildup in the device during operation.

Efforts to reduce the line-to-line capacitance have included, among other things, the formation of various types of dielectric materials having a relatively low dielectric constant between the conductive lines. One illustrative example of such techniques is depicted in Figure I wherein a plurality of conductive lines or paths 16 and optional anti-reflective coatings 18 are formed above a semiconducting substrate 14. A process layer 10, comprised of a dielectric material having a relatively low dielectric constant, e. g., hydrogen silsesquioxane (HSQ), is formed above the semiconducting substrate 14. Thereafter, another dielectric layer 12 comprised of, for example, silicon dioxide, may also be formed above the dielectric layer 10. Openings or vias 21 may then be formed in the process layer 12 using traditional photolithography and etching methods. Conductive plugs (not shown) are thereafter formed in the vias 21 to establish electrical connections with the conductive lines 16. Of course, the separate dielectric layers 10,12 could be replaced with a single dielectric layer that extends from the substrate 14 to a height equivalent to a surface 23 of the dielectric layer 12. i. e.. a dielectric layer that is formed completely over the conductive lines 16 and anti-reflective coatings 18. Despite the use of materials having relatively low dielectric constants positioned between the conductive lines 16. there is still a need within the semiconductor industry for even further reductions in the line-to-line capacitance between adjacent conductive lines.

The present invention is directed to a method and integrated circuit device for solving or at least reducing the effects of some or all of the aforementioned problems.

DISCLOSURE OF INVENTION The present invention is directed to an integrated circuit device having a plurality of conductive interconnections and a method for making same. The method comprises forming a plurality of conductive lines and forming a first layer of material between adjacent conductive lines. The method further comprises forming a second layer of material above the first layer of material and forming a plurality of openings in the second layer of material. The method further comprises removing a portion of the first layer of material through the openings to define an air gap positioned between the adjacent conductive lines.

The integrated circuit device is comprised of at least two conductive lines separated by an air gap. The device further comprises a layer of material positioned above the conductive lines and the air gap.

BRIEF DESCRIPTION OF THE DRAWINGS The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which: Figure) is an illustrative prior art integrated circuit device having a plurality of conductive lines formed thereon; Figure 2 is one illustrative embodiment of an integrated circuit device partially formed in accordance with the present invention; Figure 3 is the device depicted in Figure 2 after the dielectric material has been removed from between the adjacent conductive lines; Figure 4 is a plan view of a portion of the device shown in Figure 3 ; Figure 5 is the device depicted in Figure 3 after yet another non-conformal or non-gap-filling dielectric layer has been positioned above the device shown in Figure 3; Figure 6 is another illustrative embodiment of an integrated circuit device partially formed in accordance with the present invention; Figure 7 is the device depicted in Figure 6 after the dielectric material has been removed from between adjacent conductive lines; Figure 8 is a plan view of a portion of the device shown in Figure 7 ; Figure 9 is a cross-sectional view of the device depicted in Figure 8 after a conformal process layer has been formed thereabove : and Figure 10 is a cross-sectional view of the device depicted in Figure 9 after illustrative conductive plugs have been formed above the illustrative conductive lines.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

MODE (S) FOR CARRYING OUT THE INVENTION Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers'specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development

effort might be complex and time-consuming, but woutd nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

The present invention will now be described with reference to Figures 2-10. Although the various regions and structures of a semiconductor device are depicted in the drawings as having very precise, sharp configurations and profiles. those skilled in the art recognize that, in reality, these regions and structures are not as precise as indicated in the drawings. Additionally, the relative sizes of the various features depicted in the drawings may be exaggerated or reduced as compared to the size of those feature sizes on fabricated devices. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention.

In general, the present invention is directed to the formation of an air gap between conductive interconnections on an integrated circuit device. Two illustrative embodiments of the invention are disclosed herein. The first embodiment is disclosed in Figures 2-5, and the second embodiment is disclosed in Figures 6-10.

As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of technologies, e. g., NMOS, PMOS, CMOS, etc., and is readily applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc.

As shown in Figure 2, a plurality of conductive lines 16 may be formed above a semiconducting substrate 26. Although not required, if desired, the conductive lines 16 may also have an optional anti-reflective coating 18 formed thereabove. The conductive lines 16 and anti-reflective coatings 18 are formed using known techniques for formation of such layers, e. g., chemical vapor deposition, sputtering, electrochemical deposition, physical vapor deposition, etc., and are patterned using traditional photolithography techniques. The particular methods used to form the conductive lines 16 and, if used, anti-reflective coatings 18 should not be considered a limitation of the present invention.

The conductive lines 16 may be comprised of a variety of conductive materials, such as a metal or metal alloy, e. g., aluminum, aluminum alloys, titanium, copper, copper alloys, tungsten, cobalt or titanium silicide, polysilicon, etc. The thickness of the process layer (not shown) used to form the conductive lines 16 may be varied as a matter of design choice. In one illustrative embodiment, the conductive lines 16 are comprised of aluminum alloy having a height above a surface 25 of a substrate 26 that ranges from approximately 4000-20,000 A.

Similarly, if used, the anti-reflective coating 18 may be comprised of a variety of materials, such as titanium nitride (TiN). In one illustrative embodiment, the anti-reflective coating 18 is comprised of titanium nitride having a thickness ranging from approximately 0.02-0.2mm (200-2000 A).

After the formation of the conductive lines 16 and, if used, anti-reflective coatings 18, a process layer 24 is formed above the substrate 26. The process layer 24 may be comprised of a variety of materials. As will be readily apparent upon a complete reading of the present disclosure, the process layer 24 is a sacrificial layer, ie., at least portions of the process layer 24 will be removed during further processing, as described below. The process layer 24 may be formed from a variety of materials. For example. the process layer 24 may be comprised of a material having a dielectric constant less than approximately four, e. g., an organic-based dielectric material such as a poly (imide), a poly (arylene ether), a divinyl siloxane benzocyclobutane, a poly (tetrafluoroethylene), a poly (paraxylylene), an aromatic hydrocarbon, porous analogs of these materials, etc. The process layer 24 could also be comprised of a material having a dielectric constant less than approximately seven, e. g.. a silicon-based dielectric material, such as fluorosilicate glass (FSG), hydrogen silsesquioxane (HSQ), silicon dioxide, silicon nitride, silicon oxynitride, etc. After the process layer 24 is formed, it may be, if desired, subjected to a chemical

mechanical polishing or plasma etch-back process to planarize a surface 27. Alternatively, the process layer 24 could be comprised of a material and/or formed by a technique that results in a self-planarized layer 24.

Thereafter, as shown in Figure 2, a second process layer 20 is formed above the process layer 24. The <BR> <BR> <BR> <BR> process layer 20 may be comprised of a variety of materials, e. g., an organic-based dielectric material (such as those described above) or a silicon-based dielectric material (such as those described above). The process layer 20 may be formed by a variety of techniques known for forming such layers, e. g., chemical vapor deposition, sputtering, spin-on, etc., and the thickness of the process layer 20 may be varied as a matter of design choice. The particular method used to form the process layer 20 should not be considered to be a limitation of the present invention. In one illustrative embodiment, the process layer 20 is comprised of a deposited layer of silicon dioxide having a thickness ranging from approximately 0.5-0.8mm (5000-8000 A).

Ultimately, the materials of construction for both the process layer 24 and the process layer 20 are selected such that the process layer 24 may be selectively removed with respect to the process layer 20. This selective removal may be accomplished by, for example, dry (plasma or reactive ion) etching, oxidation, photon degradation, thermal degradation, thermally oxidative degradation, or chemical dissolution (wet etching). For <BR> <BR> <BR> <BR> example, if it is desired that the process layer 24 be subsequently removed by an etching process, e. g.. a plasma oxygen etch, then the materials of construction for the process layer 24 and the process layer 20 must be selectively etchable with respect to one another.

As shown in Figures 2-5, the next operation involves the formation of a plurality of openings 22 in the process layer 20. The openings 22 are used to provide access for removal of portions of the process layer 24 lying underneath the process layer 20 between the conductive lines 16. This process results in the formation of an air gap 28 (see Figure 3) between the conductive lines 16.

The size, configuration, and spacing of the openings 22 are matters of design choice that may vary depending upon a particular application. For example, the openings 22 may be of any shape, e. g.. circular, square, elliptical, oval, rectangular, etc. The number, size and spacing of the openings 22 may be varied as a matter of design choice or as required by a particular application. For example, the number, size and spacing may depend, in part, on the material used to make the process layer 24, the amount of the process layer 24 to be removed through each of the openings 22, the edge-to-edge spacing between adjacent conductive lines 16, and the particular removal process used. In one illustrative embodiment where etching is the selected method of removal. and the process layer 24 is comprised of a layer of thermally-labile polymers approximately 0.4-2. Omm (4000-20.000 A) thick, the process layer 20 is comprised of a layer of silicon dioxide approximately 0.4-2.0mm (4000-20,000 A) thick, and the spacing between the edges 35 of the conductive lines 16 is approximately 0.7-lmm (7000-10. 000 A), the openings 22 are generally circular in cross-section and have a diameter of approximately 0.5mm (5000 A). In one illustrative embodiment, the openings 22 are located approximately equidistant between edges 35 of the conductive lines 16 and have a center-to-center spacing along the conductive lines 16 of approximately 0.5mm (5000 A) apart, although other configurations and patterns may also be used. Of course, a variety of different hole sizes and densities may be used with a variety of different processes.

If thermal degradation or thermally enhanced oxidation is chosen as the method of removal. the first process layer 24 may be comprised of, for example, thermally-labile polymers, polynorbomene, polyimide, polyparaxylylene, polytetrafluoroethylene, or like materials, and the process layer 20 may be comprised of, for example, silicon dioxide, fluorinated silicon oxide, silicon nitride, silicon oxynitride, or like materials. To remove

the process layer 24 between the adjacent conductive lines 16. the device is heated to a temperature ranging from approximately 250-500°C for approximately 1-60 minutes using a tube furnace or a rapid thermal anneal process.

As stated previously, this selective removal may be accomplished by any method, including etching, oxidation, thermal degradation, chemical dissolution (wet chemistry), etc. Of course, during this process, portions <BR> <BR> <BR> of the process layer 20 may be also removed, e. g., the openings 22 may become slightly larger, but, in general, the process layer 20 will not be removed during the removal of the portions of the process layer 24 under the openings 22.

As will be readily recognized by those skilled in the art, the present method allows the formation of air gaps 28 between adjacent conductive lines 16.. The formation of an air gap 28, having a dielectric constant of at least equal to or slightly greater than one, effectively reduces the line-to-line capacitance between the conductive lines 16. Of course, during the formation of the air gaps 28 using the processes disclosed herein, the removal of the process layer 24 may not be complete, i. e., some portions of the process layer 24 may remain under the process layer 20. For example, portions of the process layer 24 may remain adjacent the conductive lines 16 and/or substrate 26. Nevertheless, the formation of the air gaps 28, even if a portion of the process layer 24 is not removed, provides a lower line-to-line capacitance between adjacent conductive lines 16. Additionally, although the present invention has been disclosed in the context of the formation of air gaps 28 between a plurality of conductive lines 16 formed above a semiconducting substrate 26, those skilled in the art will recognize that the present invention may be used on conductive lines 16 formed well above the surface of the substrate 26, i. e., in multi-layer interconnect systems.

Next, as shown in Figure 5, a process layer 30 is formed above the process layer 20. The process layer 30 may be comprised of a variety of different materials, such as, for example, silicon dioxide, silicon oxynitride, silicon nitride, fluorinated silicon oxide, etc., having a thickness ranging between 0.4-0.8mm (4000-8000 A).

Preferably, the process layer 30 is comprised of a dielectric material with poor gap filling capabilities such that the openings 22 in the process layer 20 are not completely filled. In one illustrative embodiment, the process layer 30 is comprised of a deposited layer of silicon dioxide having a thickness ranging from approximately 0.4-0.8mm (4000-8000 A). After the process layer 30 is formed, vias can be patterned, etched and filled with metal to make electrical contact to conductive lines 116. Subsequent conductive lines can be formed on top of the vias (repetitive layer as shown in Figure 5).

Another illustrative embodiment of the present invention is depicted in Figures 6-10. As shown in Figure 6, a plurality of conductive lines 116 may be formed above a semiconducting substrate 126. Although not required, if desired, the conductive lines 116 may also have an optional anti-reflective coating 118 formed thereabove. The conductive lines 116 and anti-reflective coatings 118 are formed using known techniques for formation of such layers, e. g., chemical vapor deposition, sputtering, physical vapor deposition, electrochemical deposition, etc., and are patterned using traditional photolithography techniques. The particular methods used to form the conductive lines 116 and, if used, anti-reflective coatings 118 should not be considered a limitation of the present invention.

The conductive lines 116 may be comprised of a variety of conductive materials, such as a metal or metal <BR> <BR> <BR> alloy, e. g., aluminum, aluminum alloys, titanium, copper, copper alloys, tungsten, cobalt or titanium silicide, polysilicon, etc. The thickness of the process layer (not shown) used to form the conductive lines 116 may be varied as a matter of design choice. In one illustrative embodiment, the conductive lines 116 are comprised of aluminum alloy having a height above the surface 125 of the substrate 126 that ranges from approximately 0.4-

2.0mm (4000-20.000 A). Similarly, if used, the anti-reflective coating 118 may be comprised of a variety of materials, such as titanium nitride (TiN). In one illustrative embodiment, the anti-reflective coating 118 is comprised of titanium nitride having a thickness ranging from approximately 0.02-0.2mm (200-2000 A).

After the formation of the conductive lines 116 and, if used, anti-reflective coatings 118, a process layer 124 is formed above the substrate 126. The process layer 124 may be comprised of a variety of materials, such as those set forth above for the process layer 24. As will be readily apparent upon a complete reading of the present disclosure, the process layer 124 is a sacrificial layer, i. e., at least portions of the process layer 124 will be removed during further processing, as described below. After the process layer 124 is formed, it may be, if desired, subjected to a chemical mechanical polishing or plasma etch-back process to planarize a surface 127. Alter- natively, the process layer 124 could be comprised of a material and/or formed by a technique that results in a self- planarized layer 124.

Thereafter, as shown in Figure 6, a second process layer 120 is formed above the process layer 124. The process layer 120 may be comprised of a variety of materials, such as those set forth above for the process layer 20.

The process layer 120 may be formed by a variety of techniques known for forming such layers, e. g., chemical vapor deposition, sputtering, spin-on, etc., and the thickness of the process layer 120 may be varied as a matter of design choice. The particular method used to form the process layer 120 should not be considered to be a limita- tion of the present invention. In one illustrative embodiment, the process layer 120 is comprised of a deposited layer of silicon dioxide having a thickness ranging from approximately 0.5-0.8mm (5000-8000 A).

Ultimately, the materials of construction for both the process layer 124 and the process layer 120 are selected such that the process layer 124 may be selectively removed with respect to the process layer 120. This selective removal may be accomplished by, for example, dry etching, oxidation, thermal degradation, or chemical dissolution (wet etching). For example, if it is desired that the process layer 124 be subsequently removed by an <BR> <BR> <BR> <BR> etching process, e. g., a plasma oxygen etch, then the materials of construction for the process layer 124 and the process layer 120 must be selectively etchable with respect to one another.

As shown in Figures 6-10, the next operation involves the formation of a plurality of openings 122 in the process layer 120 above the conductive lines 116. The gaps 133 extending beyond the conductive lines 116 are used to provide access for removal of portions of the process layer 124 lying underneath the process layer 120 between the conductive lines 116. This process results in the formation of an air gap 128 (see Figure 7) between the conductive lines 116. The size of the gap 133 may be varied as a matter of design choice or as required by a particular application. In one embodiment, as shown in Figures 7 and 8, the distance between an edge 137 of the process layer 120 and an edge 139 of the anti-reflective coating 118 (or an edge 135 of the conductive line 116 when the anti-reflective coating is not used) ranges from approximately 0.01-lmm (100-10,000 A). In one illustrative embodiment, the openings 122 are sized and positioned so as to define a gap 133 between the process layer 120 and the conductive line 116 on each side of the conductive line 116. Of course, the openings 122 may be positioned symmetrically or asymmetrically with respect to the conductive lines 116. Additionally, the opening 122 may not extend entirely across or along the conductive lines 116, i. e., the openings 122 could be positioned such that only one gap 133 is formed adjacent the conductive line 116 by that particular opening 122. Other configurations of the openings 122 and their positioning relative to the conductive lines 116 are, of course, possible.

The size, configuration, and spacing of the openings 122 are matters of design choice that may vary depending upon a particular application. For example, the openings 122 may be of any shape, e. g., circular,

square, elliptical, rectangular, etc. The number, size and spacing of the openings 122 may be varied as a matter of design choice or as required by a particular application. For example, the number, size and spacing may depend, in part, on the material used to make the process layer 124, the amount of the process layer 124 to be removed through each of the openings 122, the edge-to-edge spacing between adjacent conductive lines 116, and the particular removal process used. In one illustrative embodiment, where selective etching is the selected method of removal, and the process layer 124 is comprised of a layer of organic polymer approximately 0.4-2.0mm (4000- 20,000 A) thick, the process layer 120 is comprised of a layer of silicon dioxide approximately 0.4-2.0mm (4000- 20,000 A) thick, and the spacing between the edges 135 of the conductive lines 116 is approximately 0.7-l. Omm (7000-10, 000 A), the openings 122 are generally square in cross-section and have a side length of approximately 0.5mm (5000 A). In one illustrative embodiment, as shown in Figures 7 and 8, the openings 122 are symmetrically positioned above the conductive lines 116 and have an edge-to-edge spacing between them along the conductive lines 116 of approximately 0.5mm (5000 A), although other configurations and patterns may also be used.

As described above with respect to the previous embodiment of the present invention, this selective removal may be accomplished by any method, including etching, oxidation, thermal degradation, chemical dissolution (wet chemistry), etc. Of course, during this process, portions of the process layer 120 may be also removed, e. g., the openings 122 may become slightly larger, but, in general, the process layer 120 will not be removed during the removal of the portions of the process layer 124.

As will be readily recognized by those skilled in the art, the present method allows the formation of air gaps 128 between adjacent conductive lines 16. The formation of an air gap 128, having a dielectric constant of approximately one, effectively reduces the line-to-line capacitance between the conductive lines 116. Of course, during the formation of the air gaps 128 using the processes disclosed herein, the removal of the process layer 124 may not be complete, ie., some portions of the process layer 124 may remain under the process layer 120. For example, portions of the process layer 124 may remain adjacent the conductive lines 116 and/or substrate 126.

Nevertheless, the formation of the air gaps 128, even if a portion of the process layer 124 is not removed, provides a lower line-to-line capacitance between adjacent conductive lines 116. Additionally, although the present invention has been disclosed in the context of the formation of air gaps 128 between a plurality of conductive lines 116 formed above a semiconducting substrate 126, those skilled in the art will recognize that the present invention may be used on conductive lines 116 formed well above the surface of the substrate 126, ie., in multi-layer inter- connect systems.

Next, as shown in Figure 9, a conformal process layer 132 comprised of a dielectric material is formed above the process layer 120 and in the opening 122. The process layer 132 may be comprised of a variety of different materials, such as, for example, silicon dioxide, silicon oxynitride, silicon nitride, having a thickness ranging between (100-500 A), and chemically vapor deposited organic polymers. Preferably, the process layer 132 is comprised of a dielectric material with poor gap filling capabilities such that the material used to make the process layer 132 does not extend into the air gap 128 through the gap 133. In one illustrative embodiment, the process layer 132 is comprised of a deposited layer of silicon dioxide having a thickness ranging from approximately 100-500 A formed by a conformal plasma enhanced chemical vapor deposition process.

In one embodiment, the next process involves the removal of a portion of the process layer 132 positioned above the anti-reflective coating 118. This process may be accomplished by a variety of techniques, such as an anisotropic etching of the process layer 132 which results in the structure of the process layer 132 shown in Figure 9. Thereafter, conductive plugs 134 may be formed above the anti-reflective coating 118 between the remaining

portions of the process layer 132, as shown in Figure 9. The conductive plugs 134 may be formed by a variety of well-known techniques, and may be comprised of a variety of conductive materials, such as copper and copper alloys, aluminum and aluminum alloys, tungsten. titanium, tantalum, or other like materials, as well as alloys of such materials.

The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.