Background

[0001] For the past several decades, the scaling of features in integrated circuits (ICs) has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize the performance of each device and each contact becomes increasingly significant. Careful design of transistors may help with such an optimization.

Brief Description of the Drawings

[0002] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0003] FIG. 1 provides a perspective view of an example IC device implementing a nanoribbon transistor, in accordance with some embodiments.

[0004] FIG. 2 provides a perspective view of an example IC device implementing a fin-based fieldeffect transistor (FinFET), in accordance with some embodiments.

[0005] FIGS. 3A-3B provide top-down views of example IC devices with non-angled elongated semiconductor structures, in accordance with some embodiments.

[0006] FIGS. 4A-4B provide top-down views of example IC devices with angled elongated semiconductor structures, in accordance with some embodiments.

[0007] FIGS. 5A-5Q. provide schematic illustrations of cross-sectional side views of example IC devices integrating non-angled and angled transistors, in accordance with some embodiments.

[0008] FIGS. 6A-6F provide top-down views of example IC devices with angled elongated semiconductor structures patterned according to different patterning techniques, in accordance with some embodiments.

[0009] FIGS. 7A-7G provide top-down views of results of various processes of a loop trimming method of manufacturing an IC device with angled elongated semiconductor structures, in accordance with some embodiments.

[0010] FIGS. 8A-8F provide top-down views of alternative arrangements of various components of the IC device that may be manufactured using the method shown in FIGS. 7A-7G, in accordance with some embodiments. [0011] FIGS. 9A-9D provide top-down views of various processes of a staggered via formation method of manufacturing an IC device that integrates angled elongated semiconductor structures with a regular array of vias, in accordance with some embodiments.

[0012] FIG. 10 provides top views of a wafer and dies that may include one or more IC devices with angled transistors in accordance with any of the embodiments disclosed herein.

[0013] FIG. 11 is a cross-sectional side view of an IC package that includes an IC device with angled transistors in accordance with any of the embodiments disclosed herein.

[0014] FIG. 12 is a cross-sectional side view of an IC device assembly that includes an IC device with angled transistors in accordance with any of the embodiments disclosed herein.

[0015] FIG. 13 is a block diagram of an example computing device that includes an IC device with angled transistors in accordance with any of the embodiments disclosed herein.

[0016] FIG. 14 is a block diagram of an example processing device that includes an IC device with angled transistors in accordance with any of the embodiments disclosed herein.

Detailed Description

[0017] IC devices with angled transistors, and related assemblies and methods, are disclosed herein. The devices, assemblies, and methods of this disclosure each have several innovative aspects, no single one of which is solely responsible for all the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.

[0018] For purposes of illustrating IC devices with angled transistors, proposed herein, it might be useful to first understand phenomena that may come into play in such arrangements. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.

[0019] A field-effect transistor (FET), e.g., a metal-oxide-semiconductor (MOS) FET (MOSFET), is a three-terminal device that includes source, drain, and gate terminals and uses electric field to control current flowing through the device. A FET typically includes a semiconductor channel material, a source region and a drain region provided in the channel material, and a gate stack that includes at least a gate electrode material and, optionally, may also include a gate insulator, where the gate stack is provided over a portion of the channel material between the source region and the drain region.

[0020] Recently, FETs with non-planar architectures, such as FinFETs (also sometimes referred to as "wrap around gate transistors" or "tri-gate transistors") and nanoribbon/nanowire transistors (also sometimes referred to as "gate all-around (GAA) transistors"), have been extensively explored as alternatives to transistors with planar architectures.

[0021] In a FinFET, an elongated semiconductor structure (i.e., an elongated structure that includes a semiconductor material) shaped as a fin extends away from a base (e.g., from a semiconductor substrate or any suitable support structure). A portion of a fin that is closest to the base may be enclosed by an insulator material. Such an insulator material, typically an oxide, is commonly referred to as a "shallow trench isolation" (STI), and the portion of the fin enclosed by the STI is referred to as a "subfin portion" or simply a "subfin." A gate stack may wrap around an upper portion of the fin (i.e., the portion farthest away from the base). The portion of the fin around which the gate stack wraps is referred to as a "channel" or a "channel portion" of a FinFET. A semiconductor material of the channel portion is commonly referred to as a "channel material" of the transistor. FinFETs are sometimes referred to as "tri-gate transistors" because, in use, such transistors may form conducting channels on three "sides" of the channel portion of the fin. A source region and a drain region are provided in the fin on the opposite sides of the gate stack, forming, respectively, a source and a drain of a FinFET.

[0022] In a nanoribbon transistor, a gate stack may be provided around a portion of an elongated semiconductor structure called "nanoribbon", forming a gate on all sides of the nanoribbon. The "channel" or the "channel portion" of a nanoribbon transistor is the portion of the nanoribbon around which the gate stack wraps. Such transistors are sometimes referred to as "GAA transistors" because, in use, such transistors may form conducting channels on all "sides" of the channel portion of the nanoribbon. A source region and a drain region are provided in the nanoribbon on each side of the gate stack, forming, respectively, a source and a drain of a nanoribbon transistor. In some settings, the term "nanoribbon" has been used to describe an elongated semiconductor structure that has a substantially rectangular transverse cross-section (i.e., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term "nanowire" has been used to describe a similar structure but with a substantially circular or square transverse cross-sections. In the following, a single term "nanoribbon transistor" is used to describe all non-planar transistors where a gate stack wraps around substantially all sides of an elongated semiconductor structure, independent of the shape of the transverse cross-section. Thus, as used herein, the term "nanoribbon transistor" is used to cover transistors with elongated semiconductor structures that have substantially rectangular transverse cross-sections (possibly with rounded corners), transistors with elongated semiconductor structures that have substantially square transverse cross-sections (possibly with rounded corners), transistors with elongated semiconductor structures that have substantially circular or elliptical/oval transverse cross-sections, as well as transistors with elongated semiconductor structures that have any polygonal transverse cross-sections.

[0023] As the foregoing illustrates, both FinFETs and nanoribbon transistors are built based on elongated semiconductor structures. A longitudinal axis of such structures may be defined as a line that is the shortest line between a source region and a drain region of a FinFET or a nanoribbon transistor. Typically, such a line extends substantially parallel to a support structure (e.g., a die, a chip, a substrate, a carrier substrate, or a package substrate) on/in which a transistor resides and is one of lines of symmetry for the transistor (at least for the idealized version of the transistor that does not reflect unintended manufacturing variations that may affect the real-life geometry of the transistor). Conventionally, FinFETs and nanoribbon transistors are oriented on a support structure so that the longitudinal axes of their elongated semiconductor structures (i.e., fins or nanoribbons, respectively) are parallel to the front and back faces of the support structure and are either perpendicular or parallel to different edges of the support structure, in particular, being either perpendicular or parallel to different edges of the front face or the back face of the support structure. In contrast to such conventional implementations, embodiments of the present disclosure provide IC devices with angled transistors, where a transistor is referred to as "angled" if a longitudinal axis of the elongated semiconductor structure based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to edges of front or back faces of a support structure on/in which the transistor resides, e.g., at an angle between 10 degrees and 80 degrees with respect to at least one of the edges of front or back faces of the support structure (since not just one but two angles may be defined among any two lines crossing one another, the two angles adding together to be 180 degrees, for the angled structures/transistors, angles referred to herein refer to the smaller of the two angles for any given pair of two lines). Angled transistors provide a promising way to increasing densities of transistors, in particular, of FinFETs and nanoribbon transistors, on the limited real estate of semiconductor chips, and embodiments of the present disclosure provide solutions for layout and patterning of angled transistors, as well as for integration of angled and non-angled transistors.

[0024] In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, in context of source/drain (S/D) regions, the term "region" may be used interchangeably with the terms "contact" and "terminal" of a transistor. In another example, as used herein, the term "connected" means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term "coupled" means either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term "circuit" means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. If used, the terms "oxide," "carbide," "nitride," "sulfide," etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, sulfur, etc., the term "high-k dielectric" refers to a material having a higher dielectric constant (k) than silicon oxide, while the term "low-k dielectric" refers to a material having a lower k than silicon oxide. The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 20%, e.g., within +/- 5% or within +/- 2%, of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between the elements, generally refer to being within +/- 1-20% of a target value, e.g., +/- 1-10% of a target value or +/- 1-5% of a target value, based on the context of a particular value as described herein or as known in the art.

[0025] The terms "over," "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0026] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation "A/B/C" means (A), (B), and/or (C).

[0027] The description may use the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0028] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, analogous elements designated in the present drawings with different reference numerals after a dash, e.g., edges 303-1, 303-2, 303-3, and 303-4 may be collectively referred to together without the reference numerals after the dash, e.g., as "edges 303." In order to not clutter the drawings, if multiple instances of certain elements are illustrated, only some of the elements may be labeled with a reference sign. A plurality of drawings with the same number and different letters may be referred to without the letters, e.g., FIGS. 5A-5Q. may be referred to as "FIG. 5."

[0029] In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so "ideal" when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not- perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of presence of IC devices with angled transistors as described herein.

[0030] Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0031] Various IC devices with angled transistors as described herein may be implemented in, or associated with, one or more components associated with an IC or/and may be implemented between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

[0032] FIG. 1 provides a perspective view of an example IC device 100 implementing a nanoribbon transistor 110, in accordance with some embodiments. The nanoribbon transistor 110 is one example of an angled transistor that may be included in various IC devices and assemblies described herein.

[0033] Turning to the details of FIG. 1, the IC device 100 may include a semiconductor material, which may include one or more semiconductor materials, formed as a nanoribbon 104 (i.e., an elongated semiconductor structure) extending substantially parallel to a support structure 102. The transistor 110 may be formed on the basis of the nanoribbon 104 by having a gate stack 106 at least partially wrap around a portion of the nanoribbon referred to as a "channel portion" and by having source and drain regions, shown in FIG. 1 as a first S/D region 114-1 and a second S/D region 114-2, on either side of the gate stack 106. In some embodiments, a layer of oxide material (not specifically shown in FIG. 1) may be provided between the support structure 102 and the gate stack 106.

[0034] The IC device 100 shown in FIG. 1, as well as IC devices shown in other drawings of the present disclosure, is intended to show relative arrangements of some of the components therein, and the IC device 100, or portions thereof, may include other components that are not illustrated (e.g., electrical contacts to the S/D regions 114 of the transistor 110, additional layers such as a spacer layer around the gate stack 106 of the transistor 110, etc.). For example, although not specifically illustrated in FIG. 1, a dielectric spacer may be provided between a first S/D contact that may be coupled to a first S/D region 114-1 of the transistor 110 and the gate stack 106 as well as between a second S/D contact that may be coupled to a second S/D region 114-2 of the transistor 110 and the gate stack 106 in order to provide electrical isolation between the source, gate, and drain contacts (in general, "contacts" described herein may also be referred to as "electrodes"). In another example, although not specifically illustrated in FIG. 1, at least portions of the transistor 110 may be surrounded in an insulator material, such as any suitable interlayer dielectric (ILD) material. In some embodiments, such an insulator material may be a high-k dielectric including elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used for this purpose may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In other embodiments, the insulator material surrounding portions of the transistor 110 may be a low-k dielectric material. Some examples of low-k dielectric materials include, but are not limited to, silicon dioxide, carbon-doped oxide, silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fused silica glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.

[0035] Implementations of the present disclosure may be formed or carried out on any suitable support structure 102, such as a substrate, a die, a wafer, or a chip. The support structure 102 may, e.g., be the wafer 2000 of FIG. 10, discussed below, and may be, or be included in, a die, e.g., the singulated die 2002 of FIG. 10, discussed below. The support structure 102 may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a SOI substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride or gallium antimonide, or other combinations of group lll-V materials (i.e., materials from groups III and V of the periodic system of elements), group ll-VI (i.e., materials from groups II and IV of the periodic system of elements), or group IV materials (i.e., materials from group IV of the periodic system of elements). In some embodiments, the substrate may be non-crystalline. In some embodiments, the support structure 102 may be a printed circuit board (PCB) substrate. Although a few examples of materials from which the support structure 102 may be formed are described here, any material that may serve as a foundation upon which an IC device with angled transistors as described herein may be built falls within the spirit and scope of the present disclosure. [0036] The nanoribbon 104 may take the form of a nanowire or nanoribbon, for example. In some embodiments, an area of a transverse cross-section of the nanoribbon 104 (i.e., an area in the x-z plane of the example coordinate system x-y-z shown in FIG. 1) may be between about 25 and 10000 square nanometers, including all values and ranges therein (e.g., between about 25 and 1000 square nanometers, or between about 25 and 500 square nanometers). The transverse cross-section of the nanoribbon 104 is cross-section along a plane perpendicular to a longitudinal axis 120 of the nanoribbon 104, where the longitudinal axis 120 may, e.g., be along the y-axis of the example coordinate system shown in FIG. 1. In some embodiments, a width of the nanoribbon 104 (i.e., a dimension measured in a plane parallel to the support structure 102 and in a direction perpendicular to the longitudinal axis 120, e.g., along the x-axis of the example coordinate system shown FIG. 1) may be at least about 3 times larger than a thickness (or a "height") of the nanoribbon 104 (i.e., a dimension measured in a plane perpendicular to the support structure 102, e.g., along the z-axis of the example coordinate system shown in FIG. 1), including all values and ranges therein, e.g., at least about 4 times larger, or at least about 5 times larger. It should be noted that FIG. 1 illustrates the x- y-z coordinate system being aligned so that the longitudinal axis 120 is along the y-axis only for the ease of explanations of this particular drawing. In other drawings, angled transistors are explained with reference to their longitudinal axes being somewhere in the x-y plane but not aligned with either y-axis or x-axis because the edges of the support structure are assumed to be aligned with those axes and the transistors are angled, meaning that they are at an angle between 10 degrees and 80 degrees with respect to y-axis and/or x-axis. Thus, when the transistor 110 is an angled transistor of any of the subsequent drawings, the longitudinal axis 120 is not aligned with the y-axis as shown in FIG. 1 but at an angle between 10 degrees and 80 degrees with respect to y-axis.

[0037] Although the nanoribbon 104 illustrated in FIG. 1 is shown as having a rectangular crosssection, the nanoribbon 104 may instead have a cross-section that is rounded at corners or otherwise irregularly shaped, and the gate stack 106 may conform to the shape of the nanoribbon 104. The terms "front face" and "back face" of a nanoribbon may refer to the faces of the nanoribbon 104 that are substantially parallel to the support structure 102, the term "sidewall" (or "side face") of a nanoribbon may refer to the opposing faces of the nanoribbon 104 that are substantially perpendicular to the support structure 102 and extend in a direction of the longitudinal axis 120 of the nanoribbon 104, while the term "end" of a nanoribbon may refer to the opposing faces of the nanoribbon 104 that are substantially perpendicular to the longitudinal axis 120 of the nanoribbon 104.

[0038] The nanoribbon 104 may be formed of one or more semiconductor materials, together referred to as a "channel material." In general, channel materials of any of the angled transistors described herein, e.g., the channel material of the transistor 110, may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the channel material may include a substantially monocrystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the channel material may include a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb). In some embodiments, the channel material may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel material may include a combination of semiconductor materials.

[0039] For some example N-type transistor embodiments (i.e., for the embodiments where the transistor in which the channel material is included is an N-type metal-oxide-semiconductor (NMOS) transistor), the channel material may include a lll-V material having a relatively high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material may be a ternary lll-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some ln _x Gai. _x As fin embodiments, In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., lno.7Gao.3As). For some example P-type transistor embodiments (i.e., for the embodiments where the transistor in which the channel material is included is a P-type metal-oxide- semiconductor (PMOS) transistor), the channel material may advantageously be a group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7.

[0040] In some embodiments, the channel material may be a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, the channel material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, and black phosphorus, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc.

[0041] As noted above, the channel material may include IGZO. IGZO-based devices have several desirable electrical and manufacturing properties. IGZO has high electron mobility compared to other semiconductors, e.g., in the range of 20-50 times than amorphous silicon. Furthermore, amorphous IGZO (a-IGZO) transistors are typically characterized by high band gaps, low-temperature process compatibility, and low fabrication cost relative to other semiconductors. IGZO can be deposited as a uniform amorphous phase while retaining higher carrier mobility than oxide semiconductors such as zinc oxide. Different formulations of IGZO include different ratios of indium oxide, gallium oxide, and zinc oxide. One particular form of IGZO has the chemical formula lnGaO ₃ (ZnO) ₅ . Another example form of IGZO has an indium:gallium:zinc ratio of 1:2:1. In various other examples, IGZO may have a gallium to indium ratio of 1:1, a gallium to indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and/or a gallium to indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10). IGZO can also contain tertiary dopants such as aluminum or nitrogen.

[0042] In some embodiments, any of the angled transistors described herein, e.g., the transistor 110, may be a thin-film transistor (TFT). A TFT is a special kind of a FET made by depositing active semiconductor material over a support (e.g., a support structure as described above) that may be a non-conducting support. Some such materials may be deposited at relatively low temperatures, which allows depositing them within the thermal budgets imposed on back-end fabrication to avoid damaging the front-end components such as the logic devices of an IC device in which the transistor may be included. Thus, in some embodiments, the channel material of any of the angled transistors described herein, e.g., the transistor 110, may be a semiconductor material deposited at relatively low temperatures, and may include any of the oxide semiconductor materials described above. [0043] In other embodiments, instead of being deposited at relatively low temperatures as described above with reference to the TFTs, the channel material of any of the angled transistors described herein, e.g., the transistor 110, may be epitaxially grown in what typically involves relatively high-temperature processing. In such embodiments, the channel material may include any of the semiconductor materials described above, including oxide semiconductor materials. In some such embodiments, the channel material may be epitaxially grown directly on a semiconductor layer of a support structure over which the transistor will be fabricated, in a process known as "monolithic integration." In other such embodiments, the channel material of any of the angled transistors described herein, e.g., the transistor 110, may be epitaxially grown on a semiconductor layer of another support structure and then the epitaxially grown layer of the channel material may be transferred, in a process known as a "layer transfer," to a support structure over which the transistor will reside, in which case the latter support structure may but does not have to include a semiconductor layer prior to the layer transfer. Layer transfer advantageously allows forming non- planar transistors, such as FinFETs or nanoribbon transistors, over support structures or in layers that do not include semiconductor materials (e.g., in the back end of an IC device). Layer transfer also advantageously allows forming transistors of any architecture (e.g., non-planar or planar transistors) without imposing the negative effects of the relatively high-temperature epitaxial growth process on devices that may already be present over a support structure.

[0044] A channel material that is deposited at relatively low temperatures is typically a polycrystalline, polymorphous, or amorphous semiconductor, or any combination thereof. A channel material that is epitaxially grown is typically a highly crystalline (e.g., monocrystalline or single-crystalline) material. Therefore, whether the channel material of any of the angled transistors described herein, e.g., the transistor 110, is deposited at relatively low temperatures or epitaxially grown can be identified by inspecting grain size of the active portions of the channel material (e.g., of the portions of the channel material that form channels of transistors). An average grain size of a channel material of any of the angled transistors described herein, e.g., the transistor 110, being between about 0.5 and 1 millimeters (in which case the material may be polycrystalline) or smaller than about 0.5 millimeter (in which case the material may be polymorphous or amorphous) may be indicative of the channel material having been deposited (e.g., in which case the transistors in which such a channel material is included are TFTs). On the other hand, an average grain size of a channel material of any of the angled transistors described herein, e.g., the transistor 110, being equal to or greater than about 1 millimeter (in which case the material may be a single-crystal material) may be indicative of the channel material having been epitaxially grown and included in the final device either by monolithic integration or by layer transfer.

[0045] In some embodiments, the channel material of any of the angled transistors described herein, e.g., the transistor 110, may include a two-dimensional (2D) semiconductor material, i.e., a semiconductor material with a thickness of a few nanometers or less, where electrons in the material are free to move in the 2D plane but their restricted motion in the third direction is governed by quantum mechanics. In some such embodiments, such a channel material may include a single atomic monolayer of a 2D semiconductor material, while, in other such embodiments, such a channel material may include five or more atomic monolayers of a 2D semiconductor material. Examples of 2D materials that may be used to implement the channel material of any of the angled transistors described herein include, but are not limited to, graphene, hexagonal boron nitride, or transition-metal chalcogenides. [0046] A gate stack 106 including a gate electrode material 108 and, optionally, a gate insulator 112, may wrap entirely or almost entirely around a portion of the nanoribbon 104 as shown in FIG. 1, with the channel portion of the transistor 110 being the active region (channel region) of the channel material in the portion of the nanoribbon 104 wrapped by the gate stack 106. The gate insulator 112 is not shown in the perspective drawing of the IC device 100 shown in FIG. 1 but is shown in an inset 130 of FIG. 1, providing a cross-sectional side view of a portion of the nanoribbon 104 with a gate stack 106 wrapping around it. As shown in FIG. 1, the gate insulator 112 may wrap around a transversal portion/cross-section of the nanoribbon 104, and the gate electrode material 108 may wrap around the gate insulator 112.

[0047] The gate electrode material 108 may include at least one P-type work function metal or retype work function metal, depending on whether the transistor 110 is a PMOS transistor or an NMOS transistor. P-type work function metal may be used as the gate electrode material 108 when the transistor 110 is a PMOS transistor and N-type work function metal may be used as the gate electrode material 108 when the transistor 110 is an NMOS transistor. For a PMOS transistor, metals that may be used for the gate electrode material 108 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode material 108 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode material 108 may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further layers may be included next to the gate electrode material 108 for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer.

[0048] In some embodiments, the gate insulator 112 may include one or more high-k dielectrics including any of the materials discussed herein with reference to the insulator material that may surround portions of the transistor 110. In some embodiments, an annealing process may be carried out on the gate insulator 112 during manufacture of the transistor 110 to improve the quality of the gate insulator 112. The gate insulator 112 may have a thickness that may, in some embodiments, be between about 0.5 nanometers and 3 nanometers, including all values and ranges therein (e.g., between about 1 and 3 nanometers, or between about 1 and 2 nanometers), although, in other embodiments, the thickness of the gate insulator 112 may be greater than 3 nanometers. In some embodiments, the gate stack 106 may be surrounded by a gate spacer, not shown in FIG. 1. Such a gate spacer would be configured to provide separation between the gate stack 106 and source/drain contacts of the transistor 110 and could be made of a low-k dielectric material, some examples of which have been provided above. A gate spacer may include pores or air gaps to further reduce its dielectric constant.

[0049] In some embodiments, the gate insulator 112 may include a hysteretic material or a hysteretic arrangement, which, together, may be referred to as a "hysteretic element." Transistors 110 in which the gate insulator 124 includes a hysteretic element may be described as "hysteretic transistors" and may be used to implement hysteretic memory. Hysteretic memory refers to a memory technology employing hysteretic materials or arrangements, where a material or an arrangement may be described as hysteretic if it exhibits the dependence of its state on the history of the material (e.g., on a previous state of the material). Ferroelectric (FE) and antiferroelectric (AFE) materials are examples of hysteretic materials. Layers of different materials arranged in a stack to exhibit charge-trapping phenomena is an example of a hysteretic arrangement.

[0050] A FE or an AFE material is a material that exhibits, over some range of temperatures, spontaneous electric polarization, i.e., displacement of positive and negative charges from their original position, where the polarization can be reversed or reoriented by application of an electric field. In particular, an AFE material is a material that can assume a state in which electric dipoles from the ions and electrons in the material may form a substantially ordered (e.g., substantially crystalline) array, with adjacent dipoles being oriented in opposite (antiparallel) directions (i.e., the dipoles of each orientation may form interpenetrating sub-lattices, loosely analogous to a checkerboard pattern), while a FE material is a material that can assume a state in which all of the dipoles point in the same direction. Because the displacement of the charges in FE and AFE materials can be maintained for some time even in the absence of an electric field, such materials may be used to implement memory cells. Because the current state of the electric dipoles in FE and AFE materials depends on the previous state, such materials are hysteretic materials. Memory technology where logic states are stored in terms of the orientation of electric dipoles in (i.e., in terms of polarization of) FE or AFE materials is referred to as "FE memory," where the term "ferroelectric" is said to be adopted to convey the similarity of FE memories to ferromagnetic memories, even though there is typically no iron (Fe) present in FE or AFE materials.

[0051] A stack of alternating layers of materials that is configured to exhibit charge-trapping is an example of a hysteretic arrangement. Such a stack may include as little as two layers of materials, one of which is a charge-trapping layer (i.e., a layer of a material configured to trap charges when a volage is applied across the material) and the other one of which is a tunnelling layer (i.e., a layer of a material through which the charge is to be tunneled to the charge-trapping layer). The tunnelling layer may include an insulator material such as a material that includes silicon and oxygen (e.g., silicon oxide), or any other suitable insulator. The charge-trapping layer may include a metal or a semiconductor material that is configured to trap charges. Because the trapped charges may be kept in a charge-trapping arrangement for some time even in the absence of an electric field, such arrangements may be used to implement memory cells. Because the presence and/or the number of trapped charges in a charge-trapping arrangement depends on the previous state, such arrangements are hysteretic arrangements. Memory technology where logic states are stored in terms of the amount of charge trapped in a hysteretic arrangement may be referred to as "chargetrapping memory."

[0052] Hysteretic memories have the potential for adequate non-volatility, short programming time, low power consumption, high endurance, and high-speed writing. In addition, hysteretic memories may be manufactured using processes compatible with the standard complementary metal-oxide-semiconductor (CMOS) technology. Therefore, over the last few years, these types of memories have emerged as promising candidates for many growing applications.

[0053] In some embodiments, the hysteretic element of the gate insulator 112 may be provided as a layer of a FE or an AFE material. Such an FE/AFE material may include one or more materials that can exhibit sufficient FE/AFE behavior even at thin dimensions, e.g., such as an insulator material at least about 5%, e.g., at least about 7% or at least about 10%, of which is in an orthorhombic phase and/or a tetragonal phase (e.g., as a material in which at most about 95-90% of the material may be amorphous or in a monoclinic phase). For example, such materials may be based on hafnium and oxygen (e.g., hafnium oxides), with various dopants added to ensure sufficient amount of an orthorhombic phase or a tetragonal phase. Some examples of such materials include materials that include hafnium, oxygen, and zirconium (e.g., hafnium zirconium oxide (HfZrO, also referred to as HZO)), materials that include hafnium, oxygen, and silicon (e.g., silicon-doped (Si-doped) hafnium oxide), materials that include hafnium, oxygen, and germanium (e.g., germanium-doped (Ge-doped) hafnium oxide), materials that include hafnium, oxygen, and aluminum (e.g., aluminum-doped (Aldoped) hafnium oxide), and materials that include hafnium, oxygen, and yttrium (e.g., yttrium-doped (Y-doped) hafnium oxide). However, in other embodiments, any other materials which exhibit FE/AFE behavior at thin dimensions may be used as the hysteretic element and are within the scope of the present disclosure.

[0054] In other embodiments, the hysteretic element of the gate insulator 112 may be provided as a stack of alternating layers of materials that can trap charges. In some such embodiments, the stack may be a two-layer stack, where one layer is a charge-trapping layer and the other layer is a tunnelling layer. The tunnelling layer may include an insulator material such as a material that includes silicon and oxygen (e.g., silicon oxide), or any other suitable insulator. The charge-trapping layer may include an electrically conductive material such as a metal, or a semiconductor material. In some embodiments, the charge-trapping layer may include a sub-stoichiometric material (i.e., a material that includes less than a stochiometric amount of a reagent). The sub-stoichiometric material may include vacancies in concentration of at least about 10 ¹⁸ vacancies per cubic centimeter, e.g., in concentration between about 10 ¹⁸ vacancies per cubic centimeter and about 10 ²² -10 ²³ vacancies per cubic centimeter. As known in the art, vacancies refer to cites where atoms (e.g., oxygen or nitrogen) that should be present are missing, thus providing a defect in a material. For example, the sub-stoichiometric material of any of the hysteretic elements described herein may include oxygen and the vacancies may be oxygen vacancies, or the sub-stoichiometric material may include nitrogen and the vacancies may be nitrogen vacancies. During operation, charges may be trapped in the vacancies of the sub-stoichiometric material. Thus, implementing a sub- stoichiometric material with vacancies is one way to provide a charge-trapping layer of a hysteretic arrangement. In general, any material that has defects that can trap charge may be used in/as a charge-trapping layer. Such defects are very detrimental to operation of logic devices and, therefore, typically, deliberate steps need to be taken to avoid presence of the defects. However, for memory devices, such defects are desirable because charge-trapping may be used to represent different memory states of a memory cell.

[0055] In some embodiments of the hysteretic element being provided as a stack of alternating layers of materials that can trap charges, the stack may be a three-layer stack where an insulator material is provided on both sides of a charge-trapping layer. In such embodiments, a layer of an insulator material on one side of the charge-trapping layer may be referred to as a "tunnelling layer" while a layer of an insulator material on the other side of the charge-trapping layer may be referred to as a "field layer."

[0056] In various embodiments of the hysteretic element being provided as a stack of alternating layers of materials that can trap charges, a thickness of each layer the stack may be between about 0.5 and 10 nanometers, including all values and ranges therein, e.g., between about 0.5 and 5 nanometers. In some embodiment of a three-layer stack, a thickness of each layer of the insulator material may be about 0.5 nanometers, while a thickness of the charge-trapping layer may be between about 1 and 8 nanometers, e.g., between about 2.5 and 7.5 nanometers, e.g., about 5 nanometers. In some embodiments, a total thickness of the hysteretic element provided as a stack of alternating layers of materials that can trap charges (i.e., a hysteretic arrangement) may be between about 1 and 10 nanometers, e.g., between about 2 and 8 nanometers, e.g., about 6 nanometers. [0057] Turning to the S/D regions 114 of the transistor 110, in some embodiments, the S/D regions may be highly doped, e.g., with dopant concentrations of about 10 ²¹ dopants per cubic centimeter, in order to advantageously form Ohmic contacts with the respective S/D electrodes, although these regions may also have lower dopant concentrations and may form Schottky contacts in some implementations. Irrespective of the exact doping levels, the S/D regions of a transistor may be the regions having dopant concentration higher than in other regions, e.g., higher than a dopant concentration in the channel portion (i.e., in a channel material extending between the first S/D region 114-1 and the second S/D region 114-2), and, therefore, may be referred to as "highly doped" (HD) regions. The channel portion of the transistor 110 may include semiconductor materials with doping concentrations significantly smaller than those of the S/D regions 114.

[0058] The S/D regions 114 of the transistor 110 may generally be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the nanoribbon 104 to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the nanoribbon 104 may follow the ion implantation process. In the latter process, portions of the nanoribbon 104 may first be etched to form recesses at the locations of the future S/D regions 114. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 114. In some implementations, the S/D regions 114 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the S/D regions 114 may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 114. In some embodiments, a distance between the first and second S/D regions 114 (i.e., a dimension measured along the longitudinal axis 120 of the nanoribbon 104) may be between about 5 and 40 nanometers, including all values and ranges therein (e.g., between about 22 and 35 nanometers, or between about 20 and 30 nanometers).

[0059] In some embodiments, angled transistors described herein may be implemented in memory arrays. In some such embodiments, an angled transistor may be coupled to a storage element, thus forming a 1T-1X memory cell of a memory array, where "IT" in the term "1T-1X memory cell" indicates that the memory cell includes one transistor (T), and where "IX" in the term "1T-1X memory cell" indicates that the memory cell includes one storage element (X). In other embodiments, an angled transistor may be coupled to multiple storage elements, or an angled transistor may be coupled to another transistor, to form one or more memory cells of a memory array, all of which being within the scope of the present disclosure. Generally, a storage element may be any suitable IC component that can be programmed to a target data state (e.g., corresponding to a particular charged stored on the storage element or corresponding to a particular resistance state of the storage element) by applying an electric field or energy (e.g., positive or negative voltage or current pulses) to the storage element for a particular duration. In various embodiments, a storage element may be a capacitor, a resistive storage element, a resistive random-access memory (RRAM) device, a metal filament memory device, a phase change memory (PCM) device, a magnetic random-access memory (MRAM) device, etc.

[0060] An example of using the transistor 110 as a part of a memory cell is illustrated in FIG. 1, showing that the IC device 100 may include a memory cell 160 that includes the transistor 110 and a storage element 166, electrically coupled to the S/D region 114-2. In various embodiments, the storage element 166 may include one of a capacitor, a magnetoresistive material, a ferroelectric material, or a resistance-changing material. In some embodiments, the storage element 166 may include two electrodes 167-1 and 167-2, separated by a memory material 169. One example of the electrodes 167 and the memory material 169 of the storage element 166 is schematically illustrated within the dashed contour of an inset 162 of FIG. 1, although, in other embodiments, the spatial arrangement of the memory material 169 and the electrodes 167 may be different as long as the memory material 169 is spatially between the electrode 167-1 and the electrode 167-2 (e.g., the memory material 169 does not have to be a planar layer but may be arranged in any kind of a three- dimensional arrangement). The memory material 169 may be any suitable material that can put into a target state by applying an electric field or energy (e.g., positive or negative voltage or current pulses) to one or both electrodes 167 of the storage element 166 for a particular duration, thus programming the storage element 166 to a target data state (e.g., corresponding to a particular charged stored on the storage element 166 or corresponding to a particular resistance state of the storage element 166). Such a storage element 166 may be electrically coupled to the S/D region 114-2 by coupling the electrode 167-1 of the storage element 166 to the S/D region 114-2 (e.g., in some embodiments, the electrode 167-1 of the storage element 166 and a contact to the S/D region 114-2 may be a shared contact of a suitable electrically conductive material).

[0061] As an example, a dynamic random-access memory (DRAM) cell may include a storage element 166 in a form of a capacitor for storing a bit value, or a memory state (e.g., logical "1" or "0") of the cell, and an access transistor, implemented as the transistor 110, controlling access to the cell (e.g., access to write information to the cell or access to read information from the cell). Such a memory cell may be referred to as a "1T-1C memory cell," highlighting the fact that it uses one transistor (i.e., "IT" in the term "1T-1C memory cell") and one capacitor (i.e., "1C" in the term "1T- 1C memory cell"). In such embodiments, the electrodes 167 may be capacitor electrodes, and the memory material 169 may be a capacitor insulator. In some embodiments, the memory material 169 of such a capacitor may be a dielectric material. In other embodiments, the memory material 169 of such a capacitor may be a hysteretic element, e.g., as described above with reference to the embodiments where the gate insulator 112 is a hysteretic element.

[0062] In another example, the storage element 166 may be a resistive storage element (also referred to herein as a "resistive switch") that includes the memory material 169 that is a resistancechanging material, i.e., during operation the memory material 169 can be switched between two different nonvolatile states: a high resistance state (HRS) and a low resistance state (LRS). The state of a resistive storage element may be used to represent a data bit (e.g., logical "1" for HRS and logical "0" for LRS, or vice versa). A resistive storage element may have a voltage threshold beyond which the resistive storage element is in the LRS; driving a resistive storage element into the LRS may be referred to as SET (with an associated SET threshold voltage). Similarly, a resistive storage element may have a voltage threshold beyond which the resistive storage element is in the HRS; driving a resistive storage element into the HRS may be referred to as RESET (with an associated RESET threshold voltage).

[0063] In another example, the storage element 166 may be a RRAM device; in such embodiments, the memory material 169 may include an oxygen exchange layer (e.g., hafnium) and an oxide layer, as known in the art.

[0064] In yet another example, the storage element 166 may be a metal filament memory device (e.g., a conductive bridging random-access memory (CBRAM) device); in such embodiments, the memory material 169 may include a solid electrolyte, and one of the electrodes 167 of the storage element 166 may be an electrochemically active material (e.g., silver or copper), and the other of the electrodes 167 of the storage element 166 may be an inert material (e.g., an inert metal), as known in the art. A chemical barrier layer (e.g., tantalum, tantalum nitride, or tungsten) may be disposed between the electrochemically active electrode and the solid electrolyte to mitigate diffusion of the electrochemically active material into the solid electrolyte, in some such embodiments.

[0065] In some embodiments, the storage element 166 may be a PCM device; in such embodiments, the memory material 169 may include a chalcogenide or other phase change memory material.

[0066] In some embodiments, the storage element 166 may be a MRAM device; in such embodiments, the memory material 169 may include a thin tunnel barrier material, and the electrodes 167 of the storage element 166 may be magnetic (e.g., ferromagnetic). As known in the art, MRAM devices may operate on the principle of tunnel magnetoresistance between two magnetic layers (e.g., the electrodes of the storage element 166) separated by a tunnel junction (e.g., the memory material of the storage element 166). An MRAM device may have two stable states: when the magnetic moments of the two magnetic layers are aligned parallel to each other, an MRAM device may be in the LRS, and when aligned antiparallel, an MRAM device may be in the HRS.

[0067] FIG. 2 provides a perspective view of an example IC device 200 implementing a FinFET 210, in accordance with some embodiments. The FinFET 210 is another example of an angled transistor that may be included in various IC devices and assemblies described herein.

[0068] The IC device 200 shown in FIG. 2 is intended to show relative arrangements of some of the components therein, and the IC device 200, or portions thereof, may include other components that are not illustrated. For example, although not specifically illustrated in FIG. 2, a dielectric spacer may be provided between a first S/D contact that may be coupled to a first S/D region 214-1 of the transistor 210 and the gate stack 206 as well as between a second S/D contact that may be coupled to a second S/D region 214-2 of the transistor 210 and the gate stack 206 in order to provide electrical isolation between the source, gate, and drain contacts. In another example, although not specifically illustrated in FIG. 2, at least portions of the transistor 210 may be surrounded in an insulator material, such as any suitable ILD material.

[0069] Turning to the details of FIG. 2, the IC device 200 may include a semiconductor material, which may include one or more semiconductor materials, formed as a fin 204 extending away from a support structure 202. A FinFET 210 may be formed on the basis of the fin 204 by having a gate stack 206 at least partially wrap around a channel portion of the fin 204 and by having source and drain regions, shown in FIG. 2 as a first S/D region 214-1 and a second S/D region 214-2, on either side of the gate stack 206. As shown in FIG. 2, the gate stack 206 includes a gate electrode material 208 and a gate insulator 212, each of which wraps entirely or almost entirely around the channel portion of the fin 204, although in other embodiments of the IC device 200 the gate insulator 212 may be absent. Descriptions provided above with reference to the support structure 102, the gate stack 106, the gate electrode material 108, the gate insulator 112, and the S/D regions 114 are applicable to, respectively, the support structure 202, the gate stack 206, the gate electrode material 208, the gate insulator 212, and the S/D regions 214, and, therefore, in the interests of brevity, are not repeated. FIG. 2 further illustrates an STI 216, enclosing sidewalls of a subfin portion 218 of the fin 204. The STI 216 may include any of the insulator materials described above, e.g., any suitable ILD materials. Descriptions provided above with reference to the channel material of the transistor 110 are applicable to the semiconductor material of at least a channel portion of the fin 204 (e.g., of at least a portion of the fin 204 wrapped by the gate stack 206) and, therefore, in the interests of brevity, are not repeated.

[0070] A longitudinal axis 220 of the fin 204 may be along the y-axis of the example coordinate system shown in the present drawings. The FinFET 210 may have a gate length (i.e., a distance between the first and second S/D regions 214-1, 214-2), a dimension measured along the longitudinal axis 220, which may, in some embodiments, be between 2 and 60 nanometers, including all values and ranges therein (e.g., between 5 and 20 nanometers, or between 5 and 30 nanometers). Although the fin 204 is illustrated in FIG. 2 as having a rectangular cross-section in an x-z plane, the fin 204 may instead have a cross-section that is rounded or sloped at the "top" of the fin 204, and the gate stack 206 may conform to this rounded or sloped fin 204. In use, the FinFET 210 may form conducting channels on three "sides" of the fin 204, potentially improving performance relative to single-gate transistors (which may form conducting channels on one "side" of a channel material or substrate) and double-gate transistors (which may form conducting channels on two "sides" of a channel material or substrate). It should be noted that, similar to FIG.

1, FIG. 2 illustrates the x-y-z coordinate system being aligned so that the longitudinal axis 220 is along the y-axis only for the ease of explanations of this particular drawing. In other drawings, angled transistors are explained with reference to their longitudinal axes being somewhere in the x-y plane but not aligned with either y-axis or x-axis because the edges of the support structure are assumed to be aligned with those axes and the transistors are angled, meaning that they are at an angle between 10 degrees and 80 degrees with respect to y-axis and/or x-axis. Thus, when the FinFET 210 is an angled transistor of any of the subsequent drawings, the longitudinal axis 220 is not aligned with the y-axis as shown in FIG. 2 but at an angle between 10 degrees and 80 degrees with respect to y-axis.

[0071] An example of using the FinFET 210 as a part of a memory cell is illustrated in FIG. 2, showing that the IC device 200 may include a memory cell 260 that includes the FinFET 210 and a storage element 266, electrically coupled to the S/D region 214-2. In some embodiments, the storage element 266 may include two electrodes 267-1 and 267-2, separated by a memory material 269. One example of the electrodes 267 and the memory material 269 of the storage element 266 is schematically illustrated within the dashed contour of an inset 262 of FIG. 2, although, in other embodiments, the spatial arrangement of the memory material 269 and the electrodes 267 may be different as long as the memory material 269 is spatially between the electrode 267-1 and the electrode 267-2 (e.g., the memory material 269 does not have to be a planar layer but may be arranged in any kind of a three-dimensional arrangement). Descriptions provided above with reference to the storage element 166, the electrodes 167, and the memory material 169 are applicable to, respectively, the storage element 266, the electrodes 267, and the memory material 269, and, therefore, in the interests of brevity, are not repeated.

[0072] Either the nanoribbon 104 or the fin 204 may be an elongated semiconductor structure based on which any of the angled transistors described herein may be built (i.e., any of the angled transistors may be implemented as, e.g., the transistor 110 or the FinFET 210). Differences between non-angled elongated semiconductor structures and angled elongated semiconductor structures are described with reference to FIGS. 3A-3B and FIGS. 4A-4B. In particular, FIGS. 3A-3B illustrate example IC devices 300 with non-angled elongated semiconductor structures 304, in accordance with some embodiments, while FIGS. 4A-4B illustrate example IC devices 300 with angled elongated semiconductor structures 306. A number of elements labeled in FIGS. 3A-3B and FIGS. 4A-4B, as well in some of the subsequent drawings (e.g., FIGS. 6A-6F) with reference numerals are indicated in these drawings with different patterns in order to not clutter the drawings with too many reference numerals, with a legend showing the correspondence between the reference numerals and patterns being provided to the right of FIGS. 3A-3B and FIGS. 4A-4B. For example, the legend illustrates that FIGS. 3A-3B and FIGS. 4A-4B use different patterns to show a support structure 302, non-angled elongated semiconductor structures 304, and angled elongated semiconductor structures 306.

[0073] The IC devices 300 shown in FIGS. 3A-3B and FIGS. 4A-4B are intended to show relative arrangements of some of the components therein, and the IC devices 300, or portions thereof, may include other components that are not illustrated. For example, although not specifically illustrated in FIGS. 3A-3B and FIGS. 4A-4B, the IC devices 300 may include transistors implemented in, or based on, the elongated semiconductor structures 304, 306, which transistors would include gate stacks, S/D regions, and other portions, e.g., as described above with reference to FIGS. 1 and 2. In another example, although not specifically illustrated in FIGS. 3A-3B and FIGS. 4A-4B, at least portions of the elongated semiconductor structures 304, 306 may be surrounded in an insulator material, such as any suitable ILD material.

[0074] As shown in FIGS. 3A-3B and FIGS. 4A-4B, the IC device 300 may include a support structure 302, which may include four edges 303, individually shown as an edge 303-1, 303-2, 303-3, and 303- 4. The edges 303 may be edges of either the front face of the support structure 302 or the back face of the support structure 302, depending on whether the non-angled elongated semiconductor structures 304 and the angled elongated semiconductor structures 306 are provided on the front face or the back face of the support structure 302. The support structure 302 may be any of the support structures 102/202, described herein. The support structure 302 is rectangular and, therefore, adjacent ones of the edges 303 are at 90 degrees with respect to one another (e.g., the edges 303-1 and 303-2 are adjacent and at 90 degrees with respect to one another, the edges 303-2 and 303-3 are adjacent and at 90 degrees with respect to one another, and so on).

[0075] As shown in FIGS. 3A-3B, a plurality of parallel non-angled elongated semiconductor structures 304 may be provided over the support structure 302. The non-angled elongated semiconductor structures 304 shown in FIGS. 3A-3B are parallel because their longitudinal axes 320 are parallel to one another (only one such longitudinal axis 320 is shown in each of FIGS. 3A-3B in order to not clutter the drawings). The elongated semiconductor structures 304 shown in FIGS. 3A- 3B are "non-angled" because their longitudinal axes 320 are at angles of either 0 degrees or 90 degrees with respect to all edges 303 of the support structure 302. For example, in FIG. 3A, the longitudinal axes 320 are at an angle of 0 degrees with respect to each of the edges 303-1 and 303-3 and are at an angle of 90 degrees with respect to each of the edges 303-2 and 303-4, while, in FIG. 3B, the longitudinal axes 320 are at an angle of 90 degrees with respect to each of the edges 303-1 and 303-3 and are at an angle of 0 degrees with respect to each of the edges 303-2 and 303-4. One or more transistors (e.g., transistors 110 and/or FinFETs 210) may be formed along any and each of the non-angled elongated semiconductor structures 304, thus forming non-angled transistors as described herein.

[0076] As shown in FIGS. 4A-4B, a plurality of parallel angled elongated semiconductor structures 306 may be provided over the support structure 302. The angled elongated semiconductor structures 306 shown in FIGS. 4A-4B are parallel because their longitudinal axes 320 are parallel to one another (only one such longitudinal axis 320 is shown in each of FIGS. 4A-4B in order to not clutter the drawings). The elongated semiconductor structures 306 shown in FIGS. 4A-4B are "angled" because their longitudinal axes 320 are at angles of neither 0 degrees nor 90 degrees with respect to any of the edges 303 of the support structure 302. In particular, in each of FIGS. 4A-4B, the longitudinal axes 320 are at an angle between about 10 degrees and 80 degrees with respect to each of the edges 303. One or more transistors (e.g., transistors 110 and/or FinFETs 210) may be formed along any and each of the angled elongated semiconductor structures 306, thus forming angled transistors as described herein.

[0077] In various embodiments, both the non-angled elongated semiconductor structures 304 and the angled elongated semiconductor structures 306 may be provided over a single support structure 302, with some examples of such embodiments shown in FIGS. 5A-5Q.

[0078] FIGS. 5A-5Q. provide schematic illustrations of cross-sectional side views of example IC devices 310 integrating non-angled and angled transistors, in accordance with some embodiments. The IC devices 310 may be examples of a combination of the IC devices 300 shown in FIGS. 3A-3B and the IC devices 300 shown in FIGS. 4A-4B. To that end, FIGS. 5A-5Q. illustrate some of the same reference numerals as those shown in FIGS. 3A-3B and FIGS. 4A-4B to indicate similar or analogous elements as those that were described with reference FIGS. 3A-3B and FIGS. 4A-4B, so that descriptions of those are not repeated for FIGS. 5A-5Q. Each of the IC devices 310 illustrates the support structure 302, as described above, the support structure having a first face 312-1 and a second face 312-2 (the second face 312-2 being opposite the first face 312-1, where one of the faces 312 may be the front face/side of the support structure 302 and the other one of the faces 312 may be the back face/side of the support structure 302), a layer 314 of non-angled elongated semiconductor structures (referred to in the following as a "non-angled layer 314)" with at least one non-angled transistor 315, and a layer 316 of angled elongated semiconductor structures (referred to in the following as an "angled layer 316)" with at least one angled transistor 317.

[0079] FIG. 5A illustrates the details of the non-angled layer 314 and the angled layer 316. In particular, FIG. 5A illustrates that the non-angled layer 314 may include N non-angled elongated semiconductor structures 304 as described with reference to FIGS. 3A-3B, and that at least one of the N non-angled elongated semiconductor structures 304 may include a non-angled transistor 315. FIG. 5A further illustrates that the angled layer 316 may include M angled elongated semiconductor structures 306 as described with reference to FIGS. 4A-4B, and that at least one of the M angled elongated semiconductor structures 306 may include an angled transistor 317. Each of N and M may be an integer equal to or greater than one.

[0080] In order to not clutter the drawings, the details of the non-angled layer 314 and the angled layer 316 are only shown in FIG. 5A and FIGS. 5B-5Q. only illustrate these layers and one example transistor in each of these layers. Furthermore, although FIGS. 5A-5Q only illustrate one non-angled transistor 315 in the non-angled layer 314 and one angled transistor 317 in the angled layer 316, this is also only in order to not clutter the drawings, and in various other embodiments of the IC devices 310, any of the N non-angled elongated semiconductor structures 304 of the non-angled layer 314 may include any number of zero or more non-angled transistor 315 and any of the M angled elongated semiconductor structures 306 of the angled layer 316 may include any number of zero or more angled transistor 317. Any of the non-angled transistors 315 may be formed along any of the non-angled elongated semiconductor structures 304 as, e.g., the nanoribbon transistor 110 or the FinFET 210 (possibly coupled to the storage element 166/266, as described above), and any of the angled transistors 317 may be formed along any and each of the angled elongated semiconductor structures 306 as, e.g., the nanoribbon transistor 110 or the FinFET 210 (possibly coupled to the storage element 166/266, as described above). Thus, any of the non-angled transistors 315 and the angled transistors 317 may include a source region (e.g., one of the S/D regions 114/214), a drain region (e.g., another one of the S/D regions 114/214), and a channel region (e.g., a portion of the nanoribbon 104 or the fin 204 that is wrapped by the gate stack 106/206) spatially between the source region and the drain region, as described above, where, for the non-angled transistor 315, the shortest line extending between the source region and the drain region (i.e., the longitudinal axis 120/220) is substantially parallel to at least one of the edges 303 of the support structure 302, and, for the angled transistor 317, the shortest line extending between the source region and the drain region (i.e., the longitudinal axis 120/220) is at an angle between 10 degrees and 80 degrees with respect to the same one of the edges 303 of the support structure 302. The edges 303 are not shown in FIGS. 5A-5Q, but these are the edges 303 as shown in FIGS. 3 and 4 and are the edges of either the first face 312-1 or the second face 312-2 of the support structure 302 shown in FIGS. 5A- 5Q.

[0081] FIG. 5A illustrates an embodiment where the non-angled transistor 315 is provided over a first region of the first face 312-1 of the support structure 302 and the angled transistor 317 is provided over a second region, not overlapping with the first region, of the first face 312-1 of the support structure 302 (i.e., both the non-angled transistor 315 and the angled transistor 317 are provided over the same face 312-1, or on the same side, of the support structure 302, side-by-side with one another).

[0082] In some embodiments of the IC device 310 of FIG. 5A, the support structure 302 may be a substrate of a semiconductor material or may be a substrate having a surface that includes a layer of a semiconductor material, and the transistors 315 and 317 may be monolithically formed on the same face 312 of the support structure 302 so that channel regions of these transistors include the semiconductor material of the support structure 302. In other embodiments of the IC device 310 of FIG. 5A, some of the transistors 315 and 317 may be monolithically formed on the first face 312-1 of the support structure 302 while some others may be provided over the same face 312-1 using the layer transfer process, as described above. In still other embodiments of the IC device 310 of FIG. 5A, all the transistors 315 and 317 may be provided over the same face 312-1 using the layer transfer process. Unless described otherwise, these variations are generally applicable to other embodiments of the IC device 310 as shown in FIGS. 5B-5Q, with the modification that the transistors 315 and 317 do not have to be provided over the same face in a side-by-side manner as shown in FIG. 5A but are provided as shown in FIGS. 5B-5Q.

[0083] FIGS. 5B and 5C illustrate embodiments of the IC devices 310 where the transistors 315 and 317 are provided on the opposite faces 312, e.g., the non-angled transistor 315 may be provided over the first face 312-1, while the angled transistor 317 may be provided over the second face 312- 2. For example, in some embodiments, the support structure may 302 be a substrate of a semiconductor material or may be a substrate having a surface of the first face 312-1 and a surface of the second face 312-2 that includes a layer of a semiconductor material, and the non-angled and angled transistors 315, 317 may be monolithically formed on different faces 312 of the support structure 302 so that channel regions of these transistors include the semiconductor material. The embodiments of FIGS. 5B and 5C may differ in where projections of the transistors 315, 317 onto the support structure 302 (i.e., footprints of the transistors 315, 317) may be located with respect to one another. In particular, FIG. 5B illustrates an embodiment where a projection of the angled transistor 317 onto the support structure 302 fully overlaps with, or is within, a projection of the non-angled transistor 315 onto the support structure 302 or the projection of the non-angled transistor 315 onto the support structure 302 fully overlaps with, or is within, the projection of the angled transistor 317 onto the support structure 302. On the other hand, FIG. 5C illustrates an embodiment where a projection of the angled transistor 317 onto the support structure 302 is offset with respect to (e.g., does not overlap, or overlaps by less than about 75%, e.g., overlaps by less than about 25%) a projection of the non-angled transistor 315 onto the support structure 302. In some embodiments, any of the transistors 315, 317 of the IC devices 310 of FIGS. 5A-5C may be monolithically integrated on the support structure 302, so that the channel regions of these transistors include the channel materials that are from different portions of the semiconductor material of the support structure 302.

[0084] FIGS. 5D-5O illustrate embodiments of the IC devices 310 where the non-angled and angled layers 314 and 316 are provided over the same face 312 (e.g., the first face 312-1) of the support structure 302, stacked above one another, with a bonding layer 318 and/or a redistribution layer (RDL) 324 therebetween. Such embodiments may be advantageous in terms of, e.g., reducing parasitic effects and/or reducing delay in exchanging signals between the transistors and other devices of the non-angled and angled layers 314 and 316 because no support structure 302 is present between these layers.

[0085] FIGS. 5D-5I, 5K-5L, and 5N-5O illustrate embodiments where the non-angled transistor 315 is in a first layer over the first face 312-1 of the support structure 302, the angled transistor 317 is in a second layer over the first face 312-1 of the support structure 302 (i.e., the first and second layers are over the same face 312-1 of the support structure 302 and are closer to the first face 312-1 of the support structure 302 than to the second face 312-2 of the support structure 302), and the IC device further includes a bonding layer 318 between the first layer and the second layer. The IC devices 310 of FIGS. 5D-5I, 5K-5L, and 5N-5O may be fabricated by forming the non-angled layer 314 with one or more non-angled transistors 315 on a first IC die, forming the angled layer 316 with one or more angled transistors 317 on a second IC die, and then bonding these two IC dies together using hybrid bonding, with a bonding layer 318 therebetween. For example, the IC devices 310 of FIGS. 5D-5I, 5K-5L, and 5N-5O may be fabricated using hybrid manufacturing, where the non-angled layer 314 is first formed on a first IC die, the angled layer 316 is formed on a second IC die, and these two IC dies are then bonded together using hybrid manufacturing, with a bonding layer 318 therebetween. As used herein, "hybrid manufacturing" refers to fabricating an IC device (e.g., a microelectronic assembly) by bonding together at least two IC dies fabricated by different manufacturers, using different materials, or different manufacturing techniques. In some embodiments, bonding of the faces of the first and second IC dies may be performing using insulator-insulator bonding, e.g., as oxide-oxide bonding, where an insulating material of the first IC die is bonded to an insulating material of the second IC die. In some embodiments, the bonding material 318 may be present in between the faces of the first and second IC dies that are bonded together. To that end, the bonding material may be applied to the one or both faces of the first and second IC dies that should be bonded and then the first and second IC dies are put together, possibly while applying a suitable pressure and heating up the assembly to a suitable temperature (e.g., to moderately high temperatures, e.g., between about 50 and 200 degrees Celsius) for a duration of time. In some embodiments, the bonding material 318 may be an adhesive material that ensures attachment of the first and second IC dies to one another. In some embodiments, the bonding material 318 may be an etch-stop material. In some embodiments, the bonding material 318 may be both an etch-stop material and have suitable adhesive properties to ensure attachment of the first and second IC dies to one another. In some embodiments, the bonding material 318 may include silicon, nitrogen, and carbon, where the atomic percentage of any of these materials may be at least 1%, e.g., between about 1% and 50%, indicating that these elements are added deliberately, as opposed to being accidental impurities which are typically in concentration below about 0.1%. Having both nitrogen and carbon in these concentrations in addition to silicon is not typically used in conventional semiconductor manufacturing processes where, typically, either nitrogen or carbon is used in combination with silicon, and, therefore, could be a characteristic feature of the hybrid bonding. Using an etch-stop material at the interface (i.e., the interface between the first and second IC dies) that includes include silicon, nitrogen, and carbon, where the atomic percentage of any of these materials may be at least 1%, e.g., SiOCN, may be advantageous in terms that such a material may act both as an etch-stop material, and have sufficient adhesive properties to bond the first and second IC dies together. In addition, an etch-stop material at the interface between the first and second IC dies that includes include silicon, nitrogen, and carbon, where the atomic percentage of any of these materials may be at least 1%, may be advantageous in terms of improving etch selectivity of this material with respect to etch-stop materials that may be used in different of the first and second IC dies. In some embodiments, no bonding material 318 may be used, but there will still be a bonding interface resulting from the bonding of the first and second IC dies to one another. Such a bonding interface may be recognizable as a seam or a thin layer in the microelectronic assembly, using, e.g., selective area diffraction (SED), even when the specific materials of the insulators of the first and second IC dies that are bonded together may be the same, in which case the bonding interface would still be noticeable as a seam or a thin layer in what otherwise appears as a bulk insulator (e.g., bulk oxide) layer.

[0086] The embodiments of FIGS. 5D-5I, 5K-5L, and 5N-5O differ in whether the non-angled transistors 315 or the angled transistors 317 are at the bottom of the stack (i.e., closer to the support structure 302), and whether the bonding is a face-to-face (F2F) bonding or face-to-back (F2B) bonding between the non-angled and angled layers 314 and 316.

[0087] FIGS. 5D-5F and FIGS. 5K-5L illustrate that the angled layer 316 and, therefore, the angled transistor 317, may be at the bottom of the stack (i.e., closer to the first face 312-1 of the support structure 302 than the non-angled layer 314 and, therefore, than the non-angled transistors 315). [0088] FIG. 5D illustrates an embodiment there the bonding layer 318 may be in between and in contact with each of the angled layer 316 at the bottom of the bonding layer 318 and the nonangled layer 314 at the top of the bonding layer 318.

[0089] FIG. 5E illustrates an embodiment, where a metallization stack 322 may be present between (e.g., in contact with each of) the bonding layer 318 and the non-angled layer 314. As is known in the art, a metallization stack refers to a collection of several levels, or several layers, in which electrically conductive lines are provided, with electrically conductive vias providing electrical connectivity between conductive lines of different layers. Together, electrically conductive lines and vias may be referred to as "interconnects," where the term "interconnect" may be used to describe any element formed of an electrically conductive material for providing electrical connectivity to one or more components associated with an IC or/and between various such components. In context of an IC die/chip, the term "interconnect" may refer to both conductive lines/wires (also sometimes referred to as "lines" or "metal lines" or "trenches") and conductive vias (also sometimes referred to as "vias" or "metal vias"). In general, a term "conductive line" may be used to describe an electrically conductive element isolated by a dielectric material typically comprising an interlayer low-k dielectric that is provided within the plane of the IC die/chip. On the other hand, the term "conductive via" may be used to describe an electrically conductive element that interconnects two or more conductive lines of different levels of a metallization stack. To that end, a via may be provided substantially perpendicularly to the plane of an IC die/chip or a support structure over which an IC structure is provided and may interconnect two conductive lines in adjacent levels or two conductive lines in not adjacent levels. Sometimes, metal lines and vias may be referred to as "conductive lines/traces" and "conductive vias", respectively, to highlight the fact that these elements include electrically conductive materials such as, but not limited to, metals. Metallization stacks are typically provided in back end of line (BEOL) layers of an IC die, i.e., in layers that are further away from the die than front-end of line (FEOL) layers where front-end transistors are implemented. Therefore, presence of the metallization stack 322 between the bonding layer 318 and the non-angled layer 314, and the bonding layer 318 being between the metallization stack 322 and the angled layer 316 may be indicative of the metallization stack 322 being originally (i.e., before bonding) a part of a first IC die that includes the non-angled layer 314 with the metallization stack 322 being originally on top of the non-angled layer 314, where the first IC die is then bonded, face down, to the front face of a second IC die that includes the angled layer 316. In other words, FIG. 5E illustrates an embodiment of a F2F bonding between the non-angled and angled layers 314, 316, with the angled layer 316 being at the bottom (i.e., closer to the support structure 302).

[0090] FIG. 5F illustrates an embodiment, where the non-angled layer 314 is between (e.g., in contact with each of) the bonding layer 318 and the metallization stack 322. Presence of the nonangled layer 314 between the bonding layer 318 and the metallization stack 322 may be indicative of the metallization stack 322 being originally (i.e., before bonding) a part of a first IC die that includes the non-angled layer 314 with the metallization stack 322 being on top of the non-angled layer 314, where the first IC die is then bonded, back side down, to the front face of a second IC die that includes the angled layer 316. In other words, FIG. 5F illustrates an embodiment of a F2B bonding between the angled layer 316 and the non-angled layer 314, with the angled layer 316 being at the bottom (i.e., closer to the support structure 302). This may be done as follows. Once the nonangled layer 314 is formed over the first IC die, and the metallization stack 322 is formed over the non-angled layer 314, a carrier substrate may be attached to the top of the first IC die (e.g., the carrier substrate may be attached so that the metallization stack 322 is between the non-angled layer 314 and the carrier substrate). Such a carrier substrate may be any support structure capable of providing mechanical stability to the non-angled layer 314 and the metallization stack 322. The first IC die may then be flipped over (i.e., placing the carrier substrate at the bottom for further processing) so that the first IC die may be thinned (e.g., gradually removed) from the back side, e.g., thinned until the non-angled layer 314 is exposed. At this point, the carrier substrate may provide the mechanical stability to the arrangement. Such a first IC die with the non-angled layer 314 being exposed from the back side of the first IC die may then be bonding to the front side (e.g., to the angled layer 316) of the second IC die. [0091] FIGS. 5G-5I and FIGS. 5N-5O illustrate that the non-angled layer 314 and, therefore, the nonangled transistor 315, may be at the bottom of the stack (i.e., closer to the first face 312-1 of the support structure 302 than the angled layer 316 and, therefore, than the angled transistors 317). [0092] FIG. 5G illustrates an embodiment there the bonding layer 318 may be in between and in contact with each of the non-angled layer 314 at the bottom and the angled layer 316 at the top of the bonding layer 318 (i.e., FIG. 5G is similar to FIG. 5D but with the top and bottom layers with respect to the bonding layer 318 being reversed).

[0093] FIG. 5H illustrates an embodiment, where a metallization stack 322 may be present between (e.g., in contact with each of) the bonding layer 318 and the angled layer 314. The presence of the metallization stack 322 between the bonding layer 318 and the angled layer 316, and the bonding layer 318 being between the metallization stack 322 and the non-angled layer 314 may be indicative of the metallization stack 322 being originally (i.e., before bonding) a part of a second IC die that includes the angled layer 316 with the metallization stack 322 being originally on top of the angled layer 316, where the second IC die is then bonded, face down, to the front face of a first IC die that includes the non-angled layer 314. In other words, FIG. 5H illustrates an embodiment of a F2F bonding between the non-angled and angled layers 314, 316, with the non-angled layer 314 being at the bottom (i.e., closer to the support structure 302).

[0094] FIG. 51 illustrates an embodiment, where the angled layer 316 is between (e.g., in contact with each of) the bonding layer 318 and the metallization stack 322. Presence of the angled layer 316 between the bonding layer 318 and the metallization stack 322 may be indicative of the metallization stack 322 being originally (i.e., before bonding) a part of a second IC die that includes the angled layer 316 with the metallization stack 322 being on top of the angled layer 316, where the second IC die is then bonded, back side down, to the front face of a first IC die that includes the non-angled layer 314. In other words, FIG. 51 illustrates an embodiment of a F2B bonding between the angled layer 316 and the non-angled layer 314, with the non-angled layer 314 being at the bottom (i.e., closer to the support structure 302). This may be done as follows. Once the angled layer 316 is formed over the second IC die, and the metallization stack 322 is formed over the angled layer 316, a carrier substrate may be attached to the top of the second IC die (e.g., the carrier substrate may be attached so that the metallization stack 322 is between the angled layer 316 and the carrier substrate). Such a carrier substrate may be any support structure capable of providing mechanical stability to the angled layer 316 and the metallization stack 322. The second IC die may then be flipped over (i.e., placing the carrier substrate at the bottom for further processing) so that the second IC die may be thinned (e.g., gradually removed) from the back side, e.g., thinned until the angled layer 316 is exposed. At this point, the carrier substrate may provide the mechanical stability to the arrangement. Such a second IC die with the angled layer 316 being exposed from the back side of the second IC die may then be bonding to the front side (e.g., to the non-angled layer 314) of the first IC die.

[0095] FIGS. 5J-5O illustrate embodiments where, similar to FIGS. 5D-5I, there is no support structure 302 between the non-angled and angled layers 314, 316, but where a RDL 324 is present therebetween.

[0096] FIG. 5J illustrates an embodiment there the RDL 324 may be in between and in contact with each of the angled layer 316 at the bottom of the RDL 324 and the non-angled layer 314 at the top of the RDL 324. The RDL 324 may be similar to the bonding layer 318 in that it may provide means for mechanically attaching the angled layer 316 and the non-angled layer 314 together. However, in addition to mechanical stability, as the name "RDL" suggests, it contains interconnects that provide electrical connectivity between IC components of the angled layer 316 (angled transistors 317 being one non-limiting example of such IC components) and IC components of the non-angled layer 314 (non-angled transistors 315 being one non-limiting example of such IC components). To that end, the RDL 324 may include any arrangement of interconnects (i.e., conductive vias and/or conductive lines), configured to provide such electrical connectivity. In some embodiments, the RDL 324 may be implemented using staggered via formation, as described below with reference to FIG. 9.

[0097] FIG. 5K illustrates an embodiment of the IC device 310 similar to that shown in FIG. 5E, except that it further includes the RDL 324 between (e.g., in contact with each of) the angled layer 316 and the bonding layer 318, so the bonding layer 318 is now between (e.g., in contact with each of) the RDL 324 and the metallization stack 322.

[0098] FIG. 5L illustrates an embodiment of the IC device 310 similar to that shown in FIG. 5F, except that it also further includes the RDL 324 between (e.g., in contact with each of) the angled layer 316 and the bonding layer 318, so the bonding layer 318 is now between (e.g., in contact with each of) the RDL 324 and the non-angled layer 314.

[0099] FIG. 5M illustrates an embodiment there the RDL 324 may be in between and in contact with each of the non-angled layer 314 at the bottom of the RDL 324 and the angled layer 316 at the top of the RDL 324.

[0100] FIG. 5N illustrates an embodiment of the IC device 310 similar to that shown in FIG. 5H, except that it further includes the RDL 324 between (e.g., in contact with each of) the non-angled layer 314 and the bonding layer 318, so the bonding layer 318 is now between (e.g., in contact with each of) the RDL 324 and the metallization stack 322.

[0101] FIG. 50 illustrates an embodiment of the IC device 310 similar to that shown in FIG. 51, except that it also further includes the RDL 324 between (e.g., in contact with each of) the non- angled layer 314 and the bonding layer 318, so the bonding layer 318 is now between (e.g., in contact with each of) the RDL 324 and the angled layer 316.

[0102] FIGS. 5P and 5Q. illustrate embodiments of the IC devices 310 where the transistors 315 and 317 are provided on the same face 312 of the support structure 302 (e.g., on the first face 312-1) but some may be nested within the others. In particular, FIG. 5P illustrates an embodiment where the angled transistor 317 is one of a plurality of angled transistors 317 provided over the first face 312-1 of the support structure 302 and the non-angled transistor 315 is nestled among the plurality of angled transistors 317. On the other hand, FIG. 5Q. illustrates an embodiment where the non-angled transistor 315 is one of a plurality of non-angled transistors 315 provided over the first face 312-1 of the support structure 302 and the angled transistor 317 is nestled among the plurality of non-angled transistors 315. In some embodiments, any of the transistors 315, 317 of the IC devices 310 of FIGS. 5P and 5Q. may be monolithically integrated on the support structure 302, so that the channel regions of these transistors include the channel materials that are from different portions of the semiconductor material of the support structure 302.

[0103] FIGS. 6A-6F provide top-down views of example IC devices 324 with angled elongated semiconductor structures 306 patterned according to different patterning techniques, in accordance with some embodiments. The angled elongated semiconductor structures 306 are indicated in FIGS. 6A-6F with the same pattern as that used in FIGS. 4A-4B to show the same elements, to indicate that descriptions provided with respect to the angled elongated semiconductor structures 306 of FIGS. 4A-4B are applicable to FIGS. 6A-6F, and vice versa. Approximate outline of the support structure 302 is shown in FIGS. 6A-6F with a dotted line, with the edges 303 labeled similar to how it was done for FIGS. 3 and 4, and some longitudinal axes 320 are shown in FIGS. 6A-6F also similar to how they were shown in FIGS. 3 and 4.

[0104] The IC devices 324 shown in FIGS. 6A-6F are intended to show relative arrangements of some of the components therein, and the IC devices 300, or portions thereof, may include other components that are not illustrated. For example, although not specifically illustrated in FIGS. 6A-6F, the IC devices 324 may include transistors implemented in, or based on, the angled elongated semiconductor structures 306, which transistors would include gate stacks, S/D regions, and other portions, e.g., as described above with reference to FIGS. 1 and 2. In another example, although not specifically illustrated in FIGS. 6A-6F, at least portions of the angled elongated semiconductor structures 306 may be surrounded in an insulator material, such as any suitable ILD material. The angled elongated semiconductor structures 306 shown in FIGS. 6A-6F may be part of any of the IC devices 310, described with reference to FIG. 5 (e.g., any of the transistors 317 shown in FIG. 5 may be implemented based on any of the angled elongated semiconductor structures 306 shown in FIG. 6), even though the integration of the angled elongated semiconductor structures 306 with nonangled elongated semiconductor structures 304, explained with reference to FIG. 5, is not shown in FIG. 6.

[0105] In various embodiments, the angled elongated semiconductor structures 306 may be fabricated by, first, forming longer angled elongated semiconductor structures of suitable semiconductor materials and then cutting or/and trimming the longer structures to form various angled elongated semiconductor structures 306 as described herein. For example, each of FIGS. 6A- 6F illustrates two angled elongated semiconductor structures 306 formed from a single longer angled elongated semiconductor structure, an example of which is identified within a dashed contour 323 in FIG. 6A for one of the pairs of the angled elongated semiconductor structures 306 shown. As shown in FIG. 6A, two angled elongated semiconductor structures 306 can be formed from a single longer angled elongated semiconductor structure by providing a cut 325, e.g., using a cut line 330, thus forming a pair of angled elongated semiconductor structures 306 with a shared longitudinal axis 320 (the longitudinal axis 320 not shown in FIG. 6A for that pair of angled elongated semiconductor structures 306 but shown in FIG. 6A as a first longitudinal axis 320-1 and a second longitudinal axis 320-2 for similar other two pairs of angled elongated semiconductor structures 306). In various embodiments, such pairs of angled elongated semiconductor structures 306 may be formed by patterning using one or more cut line patterns (e.g., as shown in FIGS. 6A-6D), patterning using one or more cut via patterns (e.g., as shown in FIG. 6E), or patterning using both one or more cut line patterns and one or more cut via patterns (e.g., as shown in FIG. 6F). In general, splitting a semiconductor structure into two portions using a cut line or a cut via refers to providing a line or a via filled with an insulator material (e.g., any of the ILD materials described above, or leaving an opening as a gap) in order to electrically isolate the two portions of what used to previously be continuous semiconductor structure.

[0106] Turning to the details of line patterning, FIG. 6A illustrates a first pair of angled elongated semiconductor structures 306-1 and 306-2, sharing a single longitudinal axis 320-1, and a second pair of angled elongated semiconductor structures 306-3 and 306-4, sharing a single longitudinal axis 320-2. Other pairs of angled elongated semiconductor structures 306 are shown in FIG. 6A but are not labeled in order to not clutter the drawing. A longitudinal axis is said to be shared between a pair of angled elongated semiconductor structures 306 of an individual longitudinal axis 320 of one of the structures 306 of the pair would overlap with an individual longitudinal axis 320 of another one of the structures 306 of the pair. As shown in FIG. 6A, the longitudinal axes 320 of different pairs are parallel to one another and each is at an angle between 10 degrees and 80 degrees with respect to an edge (e.g., the edge 303-1) of the support structure 302. In FIG. 6A, a first end 328-1 and a second end 328-2 may be defined for each of the angled elongated semiconductor structures 306, where two pairs of the ends 328 are labeled for each of the structures 306-1 and 306-2, as an example. The ends 328 may be defined so that, for each of the structures 306, the first end 328-1 is closer towards the bottom of the drawing than the second end 328-2. Thus, for each pair of the structures 306, the first end 328-1 of one of the structures 306 is opposite to, or facing, the second end 328-2 of another one of the structures 306.

[0107] FIG. 6A illustrates patterning using a single cut line 330 because all of the first ends 328-1 of the structures 306 shown in the upper portion of FIG. 6A are along a single line 332-1, and all of the second ends 328-2 of the structures 306 shown in the lower portion of FIG. 6A are along a single line 332-2, parallel go the line 332-1. Thus, the lines 332-1 and 332-2 illustrate boundaries (sidewalls) of the cut line 330 used to cut through the longer angled elongated semiconductor structures (such as the one shown within the contour 323) to form the pairs 306. As a result of using such line patterning, each of a projection of the first end 328-1 of the first angled structure 306-1 onto a plane parallel to the support structure 302 and a projection of the second end 328-2 of the second angled structure 306-2 is a straight line, each of a projection of the first end 328-1 of the third angled structure 306-3 and a projection of the second end 328-2 of the fourth angled structure 306-4 is a straight line, and so on.

[0108] The IC device 324 shown in FIG. 6A illustrates a relatively straightforward implementation where a single cut line 330 is used to make the patterning cut to form all the pairs of the angled elongated semiconductor structures 306. Similar to FIG. 6A, FIG. 6B illustrates patterning using a cut line, but different cut lines 330 are used to form different pairs of the angled elongated semiconductor structures 306. For example, a first cut line 330-1 may be defined by the boundaries of lines 332-11 and 332-21, a second cut line 330-2 may be defined by the boundaries of lines 332-12 and 332-22, and a third cut line 330-3 may be defined by the boundaries of lines 332-13 and 332-23, as illustrated in FIG. 6B. The ends 328 and the longitudinal axes 332 are not specifically shown in FIG. 6B in order to not clutter the drawings, but descriptions of the ends 328 and the axes 332 provided for FIG. 6A are applicable to FIG. 6B except for the differences described.

[0109] One or more cut lines 330 defined by the boundaries of a pair of lines 332-1 and 332-2 shown in FIG. 6A and FIG. 6B all have the same width (e.g., the distance between the lines 332-1 and 332-2 is the same for different cut lines 330 shown in FIGS. 6A-6B). This does not have to be the case, as shown in FIG. 6C. Similar to FIG. 6B, FIG. 6C illustrates patterning using different cut lines 330 to form different pairs of the angled elongated semiconductor structures 306, but, unlike FIG. 6B, the widths of the cut lines 330 are different. For example, a first cut line 330-1 may be defined by the boundaries of lines 332-11 and 332-21, a second cut line 330-2 may be defined by the boundaries of lines 332-12 and 332-22, and a third cut line 330-3 may be defined by the boundaries of lines 332-13 and 332-23, as illustrated in FIG. 6C, which is similar to FIG. 6B. What is different from FIG. 6B is that a distance between the lines 332-11 and 332-21 is different from a distance between the lines 332-12 and 332-22 and from a distance between the lines 332-13 and 332-23. The ends 328 and the longitudinal axes 332 are not specifically shown in FIG. 6B in order to not clutter the drawings, but descriptions of the ends 328 and the axes 332 provided for FIG. 6A are applicable to FIG. 6B except for the differences described.

[0110] FIGS. 6A-6C illustrate embodiments where one or more cut lines 330 that are used to cut the longer angled elongated semiconductor structures to form pairs of the angled elongated semiconductor structures 306 are substantially parallel to one of the edges 303 (e.g., parallel to the edges 303-1 and 303-3) of the support structure 302. However, in other embodiments this may be different, i.e., one or more of the cut lines 330 used to cut any of the longer angled elongated semiconductor structure to form a pair of the angled elongated semiconductor structures 306 may be at an angle that is not 0 degrees or 90 degrees with respect to any of the edges 303). An example of this is shown in FIG. 6D, illustrating a first cut line 330-1, and a second cut line 330-2, each of which is at an angle between 0 degrees and 90 degrees with respect to the edges 303-1 and 303-3, i.e., such cut lines 330 are angled cut lines. Using angled cut lines 330 may result in unique shapes of the ends 328 of individual angled elongated semiconductor structures 306. For example, as is shown for an angled elongated semiconductor structure 306-1, its first end 328-1 is aligned with the angled cut line 330-1 and is, therefore, angled with respect to the edges 303 in the same manner that the cut line 330-1 is angled, but it's second end 328-2 may still be parallel to the edges 303-1 and 303-3. The same is illustrated for other angled elongated semiconductor structures 306 shown in FIG. 6D. [0111] Besides using cut lines 330, in some embodiments, cut vias 340 may be used, e.g., as illustrated in FIG. 6E. Three example cut vias 340-1, 340-2, and 340-3 are shown, each having a substantially elliptical top-down (i.e., cross-sectional for the via) shape, but in other embodiments this shape may be circular, square, rectangular, or any other polygon, possibly with rounded corners. Using cut vias 340 may result in unique shapes of the ends 328 of individual angled elongated semiconductor structures 306. For example, as is shown for an angled elongated semiconductor structure 306-1, its first end 328-1 is aligned with the cut via 330-1 and is, therefore, is curved in the same manner that the boundary of the cut via 340-1 is curved, but its second end 328-2 may still be parallel to the edges 303-1 and 303-3. The same is illustrated for other angled elongated semiconductor structures 306 shown in FIG. 6E. It should be noted that the cut vias 340 shown in FIG. 6E are angled in that their axes 342-1 and 342-2, labeled for the cut via 340-1 as an example, are not parallel or perpendicular to any of the edges 303. However, in other embodiments, the axes 342 of at least some of the cut vias 340 may be aligned with some of the edges 303 (not specifically shown in the present drawings).

[0112] Cut lines 330 and cut vias 340 illustrated in FIGS. 6A-6E provide some examples of how patterning may be performed to perform cuts to split longer angled elongated semiconductor structures into pairs of angled elongated semiconductor structures 306306. In various embodiments, any number of cut lines 330 and any number of cut vias 340 may be used to perform such patterning, either alone or in combination. An example of combining the use of a cut line 330 and a cut via 340 in a single IC device 324 is shown in FIG. 6F, where the angled elongated semiconductor structures 306-1 and 306-2 are formed by performing a cut using a cut via 340, and the angled elongated semiconductor structures 306-3 and 306-4 are formed by performing a cut using a cut line 330. Descriptions of cut lines 330 and cut vias 340 provided above are applicable to the IC device 324 of FIG. 6F and, therefore, in the interest of brevity, are not repeated.

[0113] IC devices with angled transistors, disclosed herein, may be manufactured using any suitable techniques. For example, FIGS. 7A-7G provide top-down views of results of various processes of a loop trimming method of manufacturing an IC device with angled elongated semiconductor structures, in accordance with some embodiments (where FIGS. 8A-8F provide some alternative arrangements that could be realized using the method of FIGS. 7A-7G), while FIGS. 9A-9D provide top-down views of various processes of a staggered via formation method of manufacturing an IC device that integrates angled elongated semiconductor structures (which may, e.g., be manufactured according to any embodiment of the method of FIG. 7, possibly with the variations of FIG. 8) with a regularly spaced array of vias, in accordance with some embodiments.

[0114] The IC devices shown in FIGS. 7-9 are intended to show relative arrangements of some of the components therein, and these IC devices, or portions thereof, may include other components that are not illustrated. For example, although not specifically illustrated in FIGS. 7-9, the IC devices shown in these drawings may include transistors implemented in, or based on, the angled elongated semiconductor structures shown, which transistors would include gate stacks, S/D regions, and other portions, e.g., as described above with reference to FIGS. 1 and 2. In another example, although not specifically illustrated in FIGS. 7-9, at least portions of the angled elongated semiconductor structures, or portions of other elements shown in FIGS. 7-9, may be surrounded in an insulator material, such as any suitable ILD material. The angled elongated semiconductor structures shown in FIGS. 7-9 may be part of any of the IC devices 310, described with reference to FIG. 5 (e.g., any of the transistors 317 shown in FIG. 5 may be implemented based on any of the angled elongated semiconductor structures shown in FIGS. 7-9), even though the integration of the angled elongated semiconductor structures with non-angled elongated semiconductor structures, explained with reference to FIG. 5, is not shown in FIGS. 7-9.

[0115] Although the operations of the manufacturing methods illustrated in FIGS. 7 and 9 are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, the operations may be performed in a different order to reflect the structure of an IC device in which an angled transistor will be included. In addition, the example manufacturing methods illustrated in FIGS. 7 and 9 may include other operations not specifically shown in the drawings, such as various cleaning or planarization operations as known in the art. For example, in some embodiments, a support structure, as well as layers of various other materials subsequently deposited thereon, may be cleaned prior to, after, or during any of the processes of the manufacturing methods illustrated in FIGS. 7 and 9, e.g., to remove oxides, surfacebound organic and metallic contaminants, as well as subsurface contamination. In some embodiments, cleaning may be carried out using, e.g., a chemical solution (such as peroxide), and/or ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g., using hydrofluoric acid (HF)). In another example, the arrangements/devices described herein may be planarized prior to, after, or during any of the processes of the manufacturing methods illustrated in FIGS. 7 and 9 described herein, e.g., to remove overburden or excess materials. In some embodiments, planarization may be carried out using either wet or dry planarization processes, e.g., planarization be a chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface.

[0116] FIG. 7A illustrates an IC device 350A, showing that the loop trimming method may begin with providing a support structure 302 (shown as a dotted rectangular contour) with edges 303, as described above, and providing angled elongated structures 352 of a backbone material 354 (labeled in FIG. 7A for only one of the structures 352 but shown with the same pattern for all of the other structures 352 of FIG. 7A). The angled elongated structures 352 of the backbone material 354 may be provided using any suitable patterning techniques, such as, but not limited to, photolithographic or electron-beam (e-beam) patterning, possibly in conjunction with a suitable etching technique, e.g., a dry etch, such as radio frequency (RF) reactive ion etch (RIE) or inductively coupled plasma (ICP) RIE. In some embodiments, the etch performed in the loop trimming method may include an anisotropic etch, using etchants in a form of e.g., chemically active ionized gas (i.e., plasma) using e.g., bromine (Br) and chloride (Cl) based chemistries. In some embodiments, during the etch of the loop trimming method, the IC structure may be heated to elevated temperatures, e.g., to temperatures between about room temperature and 200 degrees Celsius, including all values and ranges therein, to promote that by-products of the etch are made sufficiently volatile to be removed from the surface. As shown in FIG. 7A, a first alignment line 356-1 and a second alignment line 356-2 may be defined so that first ends 358-1 of the angled elongated structures 352 of the backbone material 354 may be aligned with the first alignment line 356-1, while the second ends 358-2 of the angled elongated structures 352 of the backbone material 354 may be aligned with the second alignment line 356-2.

[0117] FIG. 7B illustrates an IC device 350B which is substantially the same as the IC device 350A (although not all reference numerals shown in FIG. 7A are repeated again in FIG. 7B, in order to not clutter the drawing), showing that the loop trimming method may continue with depositing a liner 360 on the sidewalls of the angled elongated structures 352 of the backbone material 354. The liner 360 may be deposited on the sidewalls using any suitable conformal deposition technique such as atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or/and physical vapor deposition (PVD) processes such as sputter. As a result of conformal deposition, a thickness of the liner 360 may be substantially the same along the sidewalls of the angled elongated structures 352 of the backbone material 354. This means that new first ends 362-1 may be defined as the first ends 358-1 of the angled elongated structures 352 of the backbone material 354 with the liner 360 thereon, and that new second ends 362-2 may be defined as the second ends 362-2 of the angled elongated structures 352 of the backbone material 354 with the liner 360 thereon. Similar to the first ends 358-1, the new first ends 362-1 may still be aligned, but now with a first alignment line 364-1, which is the first alignment line 356-1 moved by a distance corresponding to the thickness of the liner 360, and the new second ends 362-2 may still be aligned, but now with a second alignment line 364-2, which is the second alignment line 356-2 moved by a distance corresponding to the thickness of the liner 360.

[0118] FIG. 7C illustrates an IC device 350C which is substantially the same as the IC device 350B (although not all reference numerals shown in FIGS. 7A-7B are repeated in FIG. 7C, in order to not clutter the drawing), showing that the loop trimming method may continue with removing the backbone material 354, leaving only the liner 360 that was previously deposited on the sidewalls of the angled elongated structures 352 of the backbone material 354. Such removal of the backbone material 354 without substantially removing the liner 360 may be performed using selective etching, provided that the backbone material 354 and the liner 360 have sufficient etch selectivity. As known in the art, two materials are said to have "sufficient etch selectivity" when etchants used to etch one material do not substantially etch the other, enabling selective etching of one material but not the other. Any suitable etching techniques, either anisotropic or isotropic, may be used to selectively remove the backbone material 354. An etch is described as "anisotropic" if etchants remove the material preferentially in one direction and not in all directions, whereas an etch is described as "isotropic" if the etchants can remove material by etching the material in different directions. Dry etch is an example of an anisotropic etch, while wet etch is an example of an isotropic etch.

[0119] FIG. 7D illustrates an IC device 350D which is substantially the same as the IC device 350C (although not all reference numerals shown in FIGS. 7A-7C are repeated again in FIG. 7D, in order to not clutter the drawing), showing that the loop trimming method may then proceed with using the pattern of the liner 360 of the IC device 350C as an etch mask to perform an anisotropic etch (e.g., a dry etch) to remove semiconductor material of the support structure 302 not covered by the etch mask, thus forming angled elongated semiconductor structures 366 that have shapes corresponding to those of the liner 360. Subsequently, the liner 360 may be removed as it has served its purpose, leaving only the angled elongated semiconductor structures 366, as shown in FIG. 7D. Such fabrication method may be used when the angled elongated semiconductor structures 366 serve as a basis for forming the angled elongated semiconductor structures 306 by monolithic integration, using the semiconductor material of the support structure 302 as a channel material of the future angled transistors, as described above.

[0120] The substantially straight portions of the angled elongated semiconductor structures 366 of the IC device 350D may then serve as the angled elongated semiconductor structures that may be patterned to form angled transistors as described above. However, having the loops at the first ends 362-1 and at the second ends 362-2 of the angled elongated semiconductor structures 366 is not desirable. Therefore, FIG. 7E illustrates an IC device 350E which is substantially the same as the IC device 350D (although not all reference numerals shown in FIGS. 7A-7D are repeated again in FIG. 7E, in order to not clutter the drawing), showing that the loop trimming method may then proceed with providing a first cut line 368-1 and a second cut line 368-2 to electrically isolate the loops of the angled elongated semiconductor structures 366 at the first ends 362-1 and at the second ends 362-2 from the straight portions of the angled elongated semiconductor structures 366 (i.e., the portions between the loops at the first ends 362-1 and at the second ends 362-2). In particular, the first cut line 368-1 may be used to electrically isolate loop portions of the first ends 362-1 of some, e.g., all, of the angled elongated semiconductor structures 366, while the second cut line 368-2 may be used to electrically isolate loop portions of the first ends 362-1 of some, e.g., all, of the angled elongated semiconductor structures 366, leaving substantially straight portions 367 of the angled elongated semiconductor structures 366 in between the cute lines 368-1 and 368-2. In FIG. 7E, only two of such substantially straight portions 367 are labeled as portions 367-1 and 367-2, for one of the loops of the angled elongated semiconductor structures 366, but a plurality of such portions 367 are shown (in some of the subsequent drawings, in order to not clutter the drawings, only one of the substantially straight portions 367 is labeled, the portion 367-1). In some embodiments, the first cut line 368-1 may be substantially parallel to the edges 303-2 and 303-4 and substantially perpendicular to the edges 303-1 and 303-3. Similarly, in some embodiments, the second cut line 368-2 may be substantially parallel to the edges 303-1 and 303-3 and substantially perpendicular to the edges 303- 2 and 303-4. Similar to the cut lines 330, described above, the cut lines 368 may be filled with any suitable insulator material to provide the electrical isolation of the loops from the substantially straight portions 367 of the angled elongated semiconductor structures 366.

[0121] A plurality of the U-shaped loop portions of the semiconductor material that is substantially the same as that of the substantially straight portions 367 of the angled elongated semiconductor structures 366 at the first ends 362-1 and a similar plurality of the U-shaped loop portions at the second ends 362-2 would be detectable in the final structures as U-shaped portions of semiconductor materials not electrically connected to anything, just remaining in the final device as consequences of using the loop trimming method as described herein. Thus, in some embodiments, these U-shaped portions of semiconductor materials may be enclosed by an insulator material on all sides.

[0122] As a result of the patterning of FIGS. 7A-7E, if the substantially straight portions 367 of the angled elongated semiconductor structures 366 between the first ends 362-1 and the second ends 362-2 are fins extending away from the support structure 302, then the U-shaped portions would also be extending away from the support structure 302 in a similar manner, and to the same height. On the other hand, if the substantially straight portions 367 of the angled elongated semiconductor structures 366 between the first ends 362-1 and the second ends 362-2 are nanoribbons provided over the support structure 302, then the U-shaped portions would be in the same layer as the nanoribbons, also provided over the support structure 302 in a similar manner, possibly with the same insulator material between them and the support structure 302 as for the nanoribbons.

[0123] In some embodiments, in a direction of longitudinal axes of the angled elongated semiconductor structures 366 (such as the longitudinal axes 320, described above), a dimension of such U-shaped loop portions either at the first ends 362-1 or at the second ends 362-2 would be, at most, 10% of the length of the substantially straight portions 367 of the angled elongated semiconductor structures 366 between the first ends 362-1 and the second ends 362-2. Projections of the U-shaped loop portions of the semiconductor material onto the support structure 302 may be curves, which would be very distinct from the analogous projections of the substantially straight portions 367 of the angled elongated semiconductor structures 366 between the first ends 362-1 and the second ends 362-2, which would be rectangles. In some embodiments, a width of any of the cut lines 368 may be between about 3 nanometers and 1000 nanometers, e.g., between about 5 nanometers and 100 nanometers, or between about 10 nanometers and 75 nanometers.

[0124] The substantially straight portions 367 of the angled elongated semiconductor structures 366 between the first ends 362-1 and the second ends 362-2 may subsequently be patterned according to different patterning techniques, e.g., as described with reference to FIGS. 6A-6F (e.g., the substantially straight portions 367 of the angled elongated semiconductor structures 366 between the first ends 362-1 and the second ends 362-2 may be the longer angled elongated semiconductor structures used as a starting point in the patterning of FIGS. 6A-6F to manufacture individual angled elongated semiconductor structures 306 as described herein).

[0125] In the loop trimming method as described above, the backbone material 354 may include any material that is sufficiently etch-selective with respect to the liner 360, e.g., any of the isolator materials described herein. The liner 360 may be any material that can serve as an etch mask for etching the semiconductor material of the support structure 302 underneath, i.e., the liner 360 may include any material that is sufficiently etch-selective with respect to the semiconductor material of the support structure 302, e.g., a material that includes silicon and nitrogen (e.g., silicon nitride), or any other suitable material. Further variations to the loop trimming method described above are possible and are illustrated in FIGS. 7F and 7G. In the embodiments of these variations, the backbone material 354 and the liner 360 may be chosen differently than described above, depending on which variation of the loop trimming method is implemented.

[0126] FIG. 7F illustrates an IC device 350F that is substantially the same as the IC device 350C, shown in FIG. 7C, except that it is processed further to form the cut lines 368-1 and 368-2 as described with reference to FIG. 7E. Such an embodiment may be used if the liner 360 is already the semiconductor material based on which angled transistors may be formed. Thus, in such an embodiment, the substantially straight portions 367 of the angled elongated semiconductor structures of the liner 360 between the first ends 362-1 and the second ends 362-2 may be the longer angled elongated semiconductor structures used as a starting point in the patterning of FIGS. 6A-6F to manufacture individual angled elongated semiconductor structures 306 as described herein. In such an embodiment, the liner 360 may include any suitable semiconductor material, such as those described with reference to the channel materials of the transistors 110 and 210, as long as it can be deposited as a liner. For example, the liner 360 may include any semiconductor material that may be used in a TFT, such as any of polycrystalline, polymorphous, or amorphous semiconductors described above. In another example of FIG. 7F, the liner 360 may include any 2D semiconductor material, such as any of graphene, hexagonal boron nitride, or transition-metal chalcogenides, described above. Because the backbone material 354 is removed in the embodiment of FIG. 7F, the backbone material 354 may be selected as any material that is sufficiently etch- selective with respect to the liner 360.

[0127] FIG. 7G illustrates an IC device 350G that is substantially the same as the IC device 350B, shown in FIG. 7B, except that it is processed further to form the cut lines 368-1 and 368-2 as described with reference to FIG. 7E. Phrased differently, the IC device 350G is substantially the same as the IC device 350F, shown in FIG. 7F, except that the backbone material 354 is not removed. Similar to FIG. 7F, the embodiment of FIG. 7G may be used if the liner 360 is already the semiconductor material based on which angled transistors may be formed, as described with reference to FIG. 7F. In contrast to the embodiment of FIG. 7F, because the backbone material 354 is not removed in the embodiment of FIG. 7G, the backbone material 354 does not need to, although it may, be selected as a material that is sufficiently etch-selective with respect to the liner 360, but the backbone material 354 does need to provide electrical insulation between individual instances of the substantially straight portions 367 of the angled elongated semiconductor structures of the liner 360 between the first ends 362-1 and the second ends 362-2. Therefore, in the embodiment of FIG. 7G, the backbone material 354 may include any suitable isolator material.

[0128] Although not specifically shown, the loop trimming method as illustrated in FIGS. 7A-7G may further include other manufacturing operations related to fabrication of other components of an angled transistor. For example, the loop trimming method as illustrated in FIGS. 7A-7G may further include patterning the angled elongated structures of the semiconductor materials (e.g., either the angled elongated semiconductor structures 366 if the version of FIG. 7E is implemented or the semiconductor material of the liner 360 if the version of FIG. 7F or FIG. 7G is implemented), e.g., using principles discussed with reference to FIGS. 6A-6F. In another example, the loop trimming method as illustrated in FIGS. 7A-7G may further include forming angled transistors (e.g., transistors 110 and/or transistors 210 as described above) based on the angled elongated structures of the semiconductor materials (e.g., either the angled elongated semiconductor structures 366 if the version of FIG. 7E is implemented or the semiconductor material of the liner 360 if the version of FIG. 7F or FIG. 7G is implemented), as well as integrating at least some of such angled transistors with non-angled transistors (e.g., as described with reference to FIGS. 5A-5Q).

[0129] The loop trimming method described above is not limited to arrangements of various components of the IC devices 350 as shown in FIGS. 7A-7G. Some alternative arrangements of various components of the IC device that may be manufactured using the method shown in FIGS. 7A-7G are shown in FIGS. 8A-8F. Each of FIGS. 8A-8F illustrate an IC device 350 that is similar to the embodiment shown in FIG. 7E but having some differences in arrangement. Therefore, the same or analogous reference numerals as those used in FIG. 7E are used in FIGS. 8A-8F to refer to similar or analogous components, so that only the differences of FIGS. 8A-8F with respect to FIG. 7E are described. Thus, besides the differences of the arrangement of FIGS. 8A-8F, all of the descriptions provided for the loop trimming method of FIGS. 7A-7G are applicable to the IC devices 350 shown in FIGS. 8A-8F. In particular, even though not specifically shown, any of the arrangements of FIGS. 8A- 8F may be alternatively implemented according to the embodiments of FIG. 7F or FIG. 7G instead. In other words, analogous modifications may be applied to the re-arrange the individual components of the embodiments of FIGS. 7F or FIG. 7G to arrive as the arrangements of FIGS. 8A-8F as those described with re-arranging the individual components of the embodiment of FIG. 7E, all of which embodiments being within the scope of the present disclosure.

[0130] In the embodiment of FIG. 7E, the first alignment line 364-1 and the second alignment line 364-2 were perpendicular to one another and aligned with respective edges 303 of the support structure 302. That does not have to be the case in other embodiments. One example is illustrated in FIG. 8A, showing that one of the alignment lines, e.g., the first alignment line 364-1, may be angled with respect to the edges 303, while the other alignment line, e.g., the second alignment line 364-2, may still be aligned (non-angled) with respect to the edges 303. Another example is illustrated in FIG. 8B, showing that both of the alignment lines may be angled with respect to the edges 303.

[0131] FIGS. 8A-8B illustrate that the first and second cut lines 368-1, 368-2 may be parallel to the respective alignment lines 364, e.g., the first cut line 368-1 may be substantially parallel to the first alignment line 364-1, while the second cut line 368-2 may be substantially parallel to the second alignment line 364-2. That does not have to be the case in other embodiments. One example is illustrated in FIG. 8C, showing that one of the cut lines, e.g., the first cut line 368-1, may be angled (i.e., non-parallel) with respect to the first alignment line 364-1, while the other cut line, e.g., the second cut line 368-2, may still be aligned (i.e., parallel) with respect to the respective alignment line, i.e., the second alignment line 364-2. Another example is illustrated in FIG. 8D, showing that both of the cut lines 368 may be angled (i.e., non-parallel) with respect to their respective alignment lines 364. Such embodiments where the cut lines 368 are no parallel to the alignment lines 364 are applicable to any embodiments of the IC devices 350, no matter whether all of the alignment lines 364 are aligned with the edges 303 of the support structure (e.g., as shown in FIGS. 7E-7G) or whether some or all of the alignment lines 364 are angled with respect to the edges 303 of the support structure (e.g., as shown in FIGS. 8A-8D).

[0132] FIGS. 7E-7G and FIGS. 8A-8D illustrate that a single cut line 368-1 is used to disconnect the loops at the first ends 362-1 and another single cut line 368-2 is used to disconnect the loops at the second ends 362-2. That does not have to be the case in other embodiments. One example is illustrated in FIG. 8E, showing that multiple cut lines 368 may be used, some only for one of the ends 362, while others extending over multiples ends 362, to perform the trimming to disconnect the loops at the first ends 362-1 and at the second ends 362-2. The arrangement of five cut lines 368-1 through 368-5, shown in FIG. 8E, is simply illustrative and, in other embodiments of the IC device 350, any number of cut lines 368 may be used, where any of them may be aligned to the edges 303 and/or aligned with the respective alignment lines 364, or not.

[0133] FIGS. 7E-7G and FIGS. 8A-8E illustrate that two or more cut lines 368 is used to disconnect the loops at the first ends 362-1 and at the second ends 362-2. That does not have to be the case in other embodiments. One example is illustrated in FIG. 8F, showing that cut vias 370 may be used to perform trimming to disconnect the loops at the first ends 362-1 and/or at the second ends 362-2. The arrangement of two cut vias 370-1 and 370-2, shown in FIG. 8F, is simply illustrative and, in other embodiments of the IC device 350, any number of cut vias 370 may be used, where any of them may be aligned to the edges 303 and/or aligned with the respective alignment lines 364, or not. Similar to the cut vias 340, described above, the cut vias 370 may be filled with any suitable insulator material to provide the electrical isolation of the loops from the substantially straight portions 367 of the angled elongated semiconductor structures 366.

[0134] FIGS. 9A-9D provide top-down views of various processes of a staggered via formation method of manufacturing an IC device that integrates angled elongated semiconductor structures with a regularly spaced array of vias, in accordance with some embodiments.

[0135] FIG. 9A illustrates an IC device 400A, showing that the staggered via formation method may begin with providing a support structure 302 (shown as a dotted rectangular contour) with edges 303, as described above, and providing the angled elongated semiconductor structures 306 as described above (labeled in FIG. 9A for only one of the structures 306 but shown with the same pattern for all of the other structures 306 of FIG. 9A). The angled elongated semiconductor structures 306 may be provided using any suitable manufacturing techniques, such as, but not limited to using any embodiments of the loop trimming method of FIG. 7 (possibly with variations of FIG. 8), possibly in combination with any of the patterning techniques described with reference to FIG. 6.

[0136] The angled elongated semiconductor structures 306 may serve as a foundation for forming transistors thereon (i.e., angled transistors), e.g., any of the transistors 110, 210, described above. Furthermore, other IC components may further be formed based on the angled elongated semiconductor structures 306, e.g., the memory cells 160, 260, described above. Various IC components (i.e., transistors, storage elements, etc.) formed based on the angled elongated semiconductor structures 306 will have terminals (e.g., the transistors will have gate terminals, drain terminals, and source terminals, the storage elements will have first and second electrode terminals, etc.) to which electrical connections will need to be made to electrically interconnect various IC components to one other and to other components of an IC device, as needed for a particular design. Because there are myriad of ways how different IC components such as transistors and storage elements may be implemented based on the angled elongated semiconductor structures 306 of the IC device 400A, details of these components are not shown in FIG. 9A, and FIG. 9B proceeds with illustrating an IC device 400B, showing that the method further includes providing vias 402 to connect to various terminals of the IC components implemented based on the angled elongated semiconductor structures 306 of FIG. 9A.

[0137] Only one of the vias 402 are labeled in FIG. 9B but a plurality of such vias is shown with the same pattern. Various terminals to which one of the vias 402 is electrically coupled to (e.g., in conductive contact with) are labeled in FIG. 9B and subsequent drawings of FIG. 9 with two-digit references such as 11, 12, 13, 14, 15, 21, 22, and so on, where the first digit represents the row in which the terminals are arranged and the second digit represents the column in which the terminals are arranged. The vias 402 may be provided as to obtain the optimum overlap with the terminals of various IC components formed based on the angled elongated semiconductor structures 306. As a result, the vias 402 may not be arranged perfectly with one another in their respective rows and/or columns. For example, as shown in FIG. 9B, the via 402 coupled to the terminal 12, the via 402 coupled to the terminal 22, the via 402 coupled to the terminal 32, and the via 402 coupled to the terminal 42 (i.e., four vias 402 coupled to different terminals of the same column, column 2) are not aligned in the same manner with respect to any single line of alignment. For vias arranged in a given column, a vertical line of alignment could be used, e.g., the vias of a given column would be aligned if a single vertical line may be drawn, in an x-y plane, that goes through the center of each of the vias. Alternatively, a vertical line of alignment may be a line on one side of all the vias 402 of a given column, as is shown in FIG. 9B with a line 404. However, there is no alignment with respect to the line 404 for the vias 402 of the column 2 because, as is seen in FIG. 9B, not all the vias 402 of the column 2 have their right side along the line 404. Careful analysis of the other vias 402 reveals that the same lack of alignment to a single vertical line applies for the vias 402 of other columns. For the rows of the IC device 400B, the vias 402 coupled to terminals of a given row, are not aligned in the same manner in that the distances between different nearest-neighbor pairs of the vias 402 of a given row are not necessarily the same. For example, for row 1, the vias coupled to the terminals 11 and 12 form one nearest-neighbor pair and the vias coupled to the terminals 12 and 13 form another nearest-neighbor pair, but the distance 406-1 between the vias coupled to the terminals 11 and 12 is not equal to the distance 406-2 between the vias coupled to the terminals 12 and 13, as shown in FIG. 9B. Careful analysis of the other vias 402 reveals that the same lack of alignment applies for the vias 402 of other nearest-neighbor pairs either in the same row 1 or in other rows. [0138] In order to electrically interconnect the IC components based on the angled elongated semiconductor structures 306 of the IC device 400B, the vias 402 need to be coupled to a regular array of vias that could be stacked above them. As used herein, an array of vias is described as "regular" if the vias of the array are arranged in columns and rows where the vias are aligned both in their rows and in their columns. Vias in a given row may be described as "aligned" if the vias of that row may be aligned along a single horizontal line (in the plane of the drawings of FIG. 9) and have the same distance between different nearest-neighbor pairs of vias of that row. Vias in a given column may be described as "aligned" if the vias of that column may be aligned along a single vertical line (in the plane of the drawings of FIG. 9) and have the same distance between different nearest-neighbor pairs of vias of that column. Such a regular array of vias is shown as vias 408 of an IC device 400C of FIG. 9C. The vias 408 are provided as to at least partially overlap with respective vias 402 with a one-to-one correspondence between the vias 408 and the vias 402 in that one of the vias 408 is electrically coupled (e.g., in conductive contact with) one and only one of the vias 402, and vice versa. For example, electrically conductive material at least partially filling the vias 402 and 408 may be in contact for each staggered pair of a via 402 and a via 408. It is the provision of the vias 408 staggered above the vias 402 that gives name "staggered via formation method" to the method illustrated in FIG. 9.

[0139] Ideally, all of the vias 408 would have the largest overlap with the respective vias 402, as greater overlap means lower contact resistance at the interface between a via 402 and a via 408 stacked on top of the via 402. However, as described above, the vias 408 have to be in a regular array, whereas, due to the nature of the angled orientation of the elongated semiconductor structures 306, the vias 402 are not in a regular array. Therefore, the process of arranging the vias 408 on top of the vias 402 may begin by selecting one terminal for which the overlap will be maximized, and then the remainder of the vias 408 will be aligned with respect to the via 408 of the selected terminal, since all of the vias 408 are in a regular array and, therefore, location of one of them dictates the location of the others. As shown in FIG. 9C, such a selected terminal may, e.g., be a terminal 23, indicated in FIG. 9C with a dashed contour around it. Maximizing the overlap between the via 402 and the via 408 at the terminal 23 means setting the location of the via 408 at the terminal 23. The remainder of the vias 408 are then arranged with respect to the via 408 at the terminal 23 by ensuring that the rules of a regular array are implemented. For example, this means that, for the column 3, a distance between the via 408 at the terminal 23 and the via 408 at the terminal 33 is substantially the same as a distance between the via 408 at the terminal 23 and the via 408 at the terminal 13 and is substantially the same as a distance between the via 408 at the terminal 33 and the via 408 at the terminal 43, and that all vias 408 of the column 3 are aligned along a single vertical line (such as the one shown in FIG. 9B, but not specifically shown in FIG. 9C in order to not clutter the drawing).

[0140] Inventors of the present disclosure realized that, when the above-described approach to staggered via formation is implemented, the misalignment between a via 408 and a corresponding via 402 underneath the via 408 increases in all directions starting from the selected terminal for which the alignment was optimized. In other words, the misalignment increases in a radially outward direction (i.e., starting from a certain central point and increasing in all directions from that point). Such radial outward expansion of the misalignment can be seen in FIG. 9C by observing that the misalignment of a pair of vias 402 and 408 is the minimum at the selected terminal 23, is increased somewhat for the nearest-neighbor terminals 13, 24, 33, and 22, is increased a little more for the second-nearest-neighbor terminals 12, 14, 34, and 32, is increased even more for the third- nearest-neighbor terminals 25, 43, and 21 (the third-nearest-neighbor terminal above the terminal 23 is not shown in FIG. 9C), and is increased still further for the terminals further away than the third nearest-neighbor terminals (e.g., the terminals 36 and 46 showing the largest misalignment in the example of FIG. 9C). Such radially outward expansion of the misalignment between the vias 402 and the vias 408 starting from a selected terminal is in sharp contrast with misalignments that may be caused by fabrication process limitations as the latter are typically observed on a wafer starting on one side and increasing in a single direction (e.g., to the other side). Therefore, radially outward expansion of the misalignment between the vias 402 and the vias 408 starting from a selected terminal within an array of terminals is a feature indicative or characteristic of the use of the staggered via formation method as described herein.

[0141] The selected terminal for which the overlap between the vias 402 and 408 is maximized does not have to be substantially in the center of an array of terminals. FIG. 9D illustrates an IC device 400D, showing an alternative arrangement of the vias 402 and the vias 408 staggered thereon according to the method described with reference to FIGS. 9A-9C, but with the selected terminal being the terminal 12. Even for such a terminal, radially outward expansion of the increase in the misalignment between the vias 402 and 408 can be observed.

[0142] In some implementations, there may come a point where the misalignment between the vias 402 and 408 becomes too large and no effective contact can be made between the vias 402 and 408, e.g., as is shown with the great misalignment between the vias 402 and 408 of the terminal 47 in FIG. 9D. Therefore, the method as described with reference to FIGS. 9A-9C may be repeated for another selected terminal in a different portion of an array of terminals. Thus, in some embodiments, the IC device 400 may include multiple selected terminals from which the misalignment radiates outwards, until a certain point.

[0143] It should be noted that while the vias 402 and 408 are shown in FIGS. 9B-9D as having a substantially square top-down shape (i.e., their transverse cross-section), this does not have to be the case. In other embodiments of the IC devices 400, any of the vias 402 and 408 may have other transverse cross-sections, such as rectangular transverse cross-sections (possibly with rounded corners), substantially circular or elliptical/oval transverse cross-sections, or any other polygonal transverse cross-sections (possibly with rounded corners), etc. Furthermore, the lack of alignment illustrated for the vias 402 may be different in different embodiments of the IC devices 400. For example, in some embodiments, the vias 402 coupled to terminals of a given column may not be aligned in the same manner in that the distances between different nearest-neighbor pairs of the vias 402 of a given column are not necessarily the same. In another example, the vias 402 coupled to terminals of a given row may not be aligned in the same manner in that there may not be a single line of alignment (e.g., a single horizontal line for the views of FIG. 9) along which the vias 402 coupled to terminals of a given row are aligned. Any combination of such example misalignments may be present for the arrangements of the vias 402 of the IC devices 400.

[0144] Any of the angled transistors described herein (e.g., as described with reference to FIGS. 1, 2, and 4), as well as any of the non-angled transistors that may be integrated on the same support structure with the angled transistors (e.g., as described with reference to FIG. 5) may be used to implement any suitable components. For example, in various embodiments, transistors described herein may be part of one or more of: a central processing unit, a memory device (e.g., a high- bandwidth memory device), a memory cell, a logic circuit, input/output circuitry, a field programmable gate array (FPGA) component such as an FPGA transceiver or an FPGA logic, a power delivery circuitry, an amplifier (e.g., a lll-V amplifier), Peripheral Component Interconnect Express (PCIE) circuitry, Double Data Rate (DDR) transfer circuitry, a computing device (e.g., a wearable or a handheld computing device), etc.

[0145] The IC devices with angled transistors disclosed herein may be included in any suitable electronic device. FIGS. 10-14 illustrate various examples of apparatuses that may include one or more of the IC devices with angled transistors disclosed herein.

[0146] FIG. 10 illustrates top views of a wafer 2000 and dies 2002 that may include one or more IC devices with angled transistors in accordance with any of the embodiments disclosed herein. In some embodiments, the dies 2002 may be included in an IC package, in accordance with any of the embodiments disclosed herein. For example, any of the dies 2002 may serve as any of the dies 2256 in an IC package 2200 shown in FIG. 11. The wafer 2000 may be composed of semiconductor material and may include one or more dies 2002 having IC structures formed on a surface of the wafer 2000. Each of the dies 2002 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more IC devices with angled transistors as described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of any embodiment of the IC devices with angled transistors as described herein), the wafer 2000 may undergo a singulation process in which each of the dies 2002 is separated from one another to provide discrete "chips" of the semiconductor product. In particular, devices that include one or more angled transistors as disclosed herein may take the form of the wafer 2000 (e.g., not singulated) or the form of the die 2002 (e.g., singulated). The die 2002 may include supporting circuitry to route electrical signals to various memory cells, transistors, capacitors, as well as any other IC components. In some embodiments, the wafer 2000 or the die 2002 may implement or include a memory device (e.g., a hysteretic memory device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 2002. For example, a memory array formed by multiple memory devices may be formed on a same die 2002 as a processing device (e.g., the processing device 2402 of FIG. 11) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0147] FIG. 11 is a side, cross-sectional view of an example IC package 2200 that may include one or more IC devices with angled transistors in accordance with any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a system-in-package (SiP).

[0148] The package substrate 2252 may be formed of a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, etc.), and may have conductive pathways extending through the dielectric material between the face 2272 and the face 2274, or between different locations on the face 2272, and/or between different locations on the face 2274.

[0149] The package substrate 2252 may include conductive contacts 2263 that are coupled to conductive pathways 2262 through the package substrate 2252, allowing circuitry within the dies 2256 and/or the interposer 2257 to electrically couple to various ones of the conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).

[0150] The IC package 2200 may include an interposer 2257 coupled to the package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and the conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 illustrated in FIG. 11 are solder bumps, but any suitable first-level interconnects 2265 may be used. In some embodiments, no interposer 2257 may be included in the IC package 2200; instead, the dies 2256 may be coupled directly to the conductive contacts 2263 at the face 2272 by first-level interconnects 2265.

[0151] The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the dies 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive pathways (not shown) through the interposer 2257, allowing circuitry within the dies 2256 to electrically couple to various ones of the conductive contacts 2261 (or to other devices included in the interposer 2257, not shown). The first-level interconnects 2258 illustrated in FIG. 11 are solder bumps, but any suitable first-level interconnects 2258 may be used. As used herein, a "conductive contact" may refer to a portion of electrically conductive material (e.g., metal) serving as an interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

[0152] In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnects 2265, and a mold compound 2268 may be disposed around the dies 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold compound 2268. Example materials that may be used for the underfill material 2266 and the mold compound 2268 are epoxy mold materials, as suitable. Second-level interconnects 2270 may be coupled to the conductive contacts 2264. The second-level interconnects 2270 illustrated in FIG. 11 are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects 22770 may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to FIG. 12.

[0153] The dies 2256 may take the form of any of the embodiments of the die 2002 discussed herein (e.g., may include any of the embodiments of the IC devices with angled transistors as described herein). In embodiments in which the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuitry to perform any desired functionality. For example, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), and one or more of the dies 2256 may be memory dies (e.g., high- bandwidth memory), including embedded memory dies as described herein. In some embodiments, any of the dies 2256 may include one or more IC devices with angled transistors, e.g., as discussed above; in some embodiments, at least some of the dies 2256 may not include any IC devices with angled transistors.

[0154] The IC package 2200 illustrated in FIG. 11 may be a flip chip package, although other package architectures may be used. For example, the IC package 2200 may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are illustrated in the IC package 2200 of FIG. 11, an IC package 2200 may include any desired number of the dies 2256. An IC package 2200 may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face 2272 or the second face 2274 of the package substrate 2252, or on either face of the interposer 2257. More generally, an IC package 2200 may include any other active or passive components known in the art.

[0155] FIG. 12 is a cross-sectional side view of an IC device assembly 2300 that may include components having one or more IC devices with angled transistors in accordance with any of the embodiments disclosed herein. The IC device assembly 2300 includes a number of components disposed on a circuit board 2302 (which may be, e.g., a motherboard). The IC device assembly 2300 includes components disposed on a first face 2340 of the circuit board 2302 and an opposing second face 2342 of the circuit board 2302; generally, components may be disposed on one or both faces 2340 and 2342. In particular, any suitable ones of the components of the IC device assembly 2300 may include any of one or more IC devices with angled transistors in accordance with any of the embodiments disclosed herein; e.g., any of the IC packages discussed below with reference to the IC device assembly 2300 may take the form of any of the embodiments of the IC package 2200 discussed above with reference to FIG. 11 (e.g., may include one or more IC devices with angled transistors provided on a die 2256).

[0156] In some embodiments, the circuit board 2302 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 may be a non-PCB substrate.

[0157] The IC device assembly 2300 illustrated in FIG. 12 includes a package-on-interposer structure 2336 coupled to the first face 2340 of the circuit board 2302 by coupling components 2316. The coupling components 2316 may electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302, and may include solder balls (e.g., as shown in FIG. 12), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0158] The package-on-interposer structure 2336 may include an IC package 2320 coupled to an interposer 2304 by coupling components 2318. The coupling components 2318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2316. The IC package 2320 may be or include, for example, a die (the die 2002 of FIG. 10), an IC device, or any other suitable component. In particular, the IC package 2320 may include one or more IC devices with angled transistors as described herein. Although a single IC package 2320 is shown in FIG. 12, multiple IC packages may be coupled to the interposer 2304; indeed, additional interposers may be coupled to the interposer 2304. The interposer 2304 may provide an intervening substrate used to bridge the circuit board 2302 and the IC package 2320. Generally, the interposer 2304 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 2304 may couple the IC package 2320 (e.g., a die) to a BGA of the coupling components 2316 for coupling to the circuit board 2302. In the embodiment illustrated in FIG. 12, the IC package 2320 and the circuit board 2302 are attached to opposing sides of the interposer 2304; in other embodiments, the IC package 2320 and the circuit board 2302 may be attached to a same side of the interposer 2304. In some embodiments, three or more components may be interconnected by way of the interposer 2304.

[0159] The interposer 2304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to through-silicon vias (TSVs) 2306. The interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.

[0160] The IC device assembly 2300 may include an IC package 2324 coupled to the first face 2340 of the circuit board 2302 by coupling components 2322. The coupling components 2322 may take the form of any of the embodiments discussed above with reference to the coupling components 2316, and the IC package 2324 may take the form of any of the embodiments discussed above with reference to the IC package 2320.

[0161] The IC device assembly 2300 illustrated in FIG. 12 includes a package-on-package structure 2334 coupled to the second face 2342 of the circuit board 2302 by coupling components 2328. The package-on-package structure 2334 may include an IC package 2326 and an IC package 2332 coupled together by coupling components 2330 such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may take the form of any of the embodiments of the coupling components 2316 discussed above, and the IC packages 2326 and 2332 may take the form of any of the embodiments of the IC package 2320 discussed above. The package-on-package structure 2334 may be configured in accordance with any of the package-on-package structures known in the art.

[0162] FIG. 13 is a block diagram of an example computing device 2400 that may include one or more components including one or more IC devices with angled transistors in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device 2400 may include a die (e.g., the die 2002 of FIG. 10) having one or more angled transistors as described herein. Any one or more of the components of the computing device 2400 may include, or be included in, an IC package 2200 of FIG. 11 or an IC device 2300 of FIG. 12.

[0163] A number of components are illustrated in FIG. 13 as included in the computing device 2400, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

[0164] Additionally, in various embodiments, the computing device 2400 may not include one or more of the components illustrated in FIG. 13, but the computing device 2400 may include interface circuitry for coupling to the one or more components. For example, the computing device 2400 may not include a display device 2412, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2412 may be coupled. In another set of examples, the computing device 2400 may not include an audio input device 2416 or an audio output device 2414, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2416 or audio output device 2414 may be coupled.

[0165] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 2404 may include memory that shares a die with the processing device 2402. This memory may be used as cache memory and may include embedded DRAM (eDRAM) or spin transfer torque MRAM.

[0166] In some embodiments, the computing device 2400 may include a communication chip 2406 (e.g., one or more communication chips). For example, the communication chip 2406 may be configured for managing wireless communications for the transfer of data to and from the computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0167] The communication chip 2406 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 1402.11 family), IEEE 1402.16 standards (e.g., IEEE 1402.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 1402.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 1402.16 standards. The communication chip 2406 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2406 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2406 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2406 may operate in accordance with other wireless protocols in other embodiments. The computing device 2400 may include an antenna 2408 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[0168] In some embodiments, the communication chip 2406 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2406 may include multiple communication chips. For instance, a first communication chip 2406 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2406 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2406 may be dedicated to wireless communications, and a second communication chip 2406 may be dedicated to wired communications.

[0169] The computing device 2400 may include a battery/power circuitry 2410. The battery/power circuitry 2410 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).

[0170] The computing device 2400 may include a display device 2412 (or corresponding interface circuitry, as discussed above). The display device 2412 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[0171] The computing device 2400 may include an audio output device 2414 (or corresponding interface circuitry, as discussed above). The audio output device 2414 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0172] The computing device 2400 may include an audio input device 2416 (or corresponding interface circuitry, as discussed above). The audio input device 2416 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

[0173] The computing device 2400 may include an other output device 2418 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2418 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. [0174] The computing device 2400 may include an other input device 2420 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0175] The computing device 2400 may include a GPS device 2422 (or corresponding interface circuitry, as discussed above). The GPS device 2422 may be in communication with a satellite-based system and may receive a location of the computing device 2400, as known in the art.

[0176] The computing device 2400 may include a security interface device 2424. The security interface device 2424 may include any device that provides security features for the computing device 2400 or for any individual components therein (e.g., for the processing device 2402 or for the memory 2404). Examples of security features may include authorization, access to digital certificates, access to items in keychains, etc. Examples of the security interface device 2424 may include a software firewall, a hardware firewall, an antivirus, a content filtering device, or an intrusion detection device.

[0177] In some embodiments, the computing device 2400 may include a temperature detection device 2426 and a temperature regulation device 2428.

[0178] The temperature detection device 2426 may include any device capable of determining temperatures of the computing device 2400 or of any individual components therein (e.g., temperatures of the processing device 2402 or of the memory 2404). In various embodiments, the temperature detection device 2426 may be configured to determine temperatures of an object (e.g., the computing device 2400, components of the computing device 2400, devices coupled to the computing device, etc.), temperatures of an environment (e.g., a data center that includes, is controlled by, or otherwise associated with the computing device 2400), and so on. The temperature detection device 2426 may include one or more temperature sensors. Different temperature sensors of the temperature detection device 2426 may have different locations within and around the computing device 2400. A temperature sensor may generate data (e.g., digital data) representing detected temperatures and provide the data to another device, e.g., to the temperature regulation device 2428, the processing device 2402, the memory 2404, etc. In some embodiments, a temperature sensor of the temperature detection device 2426 may be turned on or off, e.g., by the processing device 2402 or an external system. The temperature sensor detects temperatures when it is on and does not detect temperatures when it is off. In other embodiments, a temperature sensor of the temperature detection device 2426 may detect temperatures continuously and automatically or detect temperatures at predefined times or at times triggered by an event associated with the computing device 2400 or any components therein.

[0179] The temperature regulation device 2428 may include any device configured to change (e.g., decrease) temperatures, e.g., based on one or more target temperatures and/or based on temperature measurements performed by the temperature detection device 2426. A target temperature may be a preferred temperature. A target temperature may depend on a setting in which the computing device 2400 operates. In some embodiments, the target temperature may be 200 Kelvin degrees or lower. In some embodiments, the target temperature may be 20 Kelvin degrees or lower, or 5 Kelvin degrees or lower. Target temperatures for different objects and different environments of, or associated with, the computing device 2400 can be different. In some embodiments, cooling provided by the temperature regulation device 2428 may be a multi-stage process with temperatures ranging from room temperature to 4K or lower.

[0180] In some embodiments, the temperature regulation device 2428 may include one or more cooling devices. Different cooling device may have different locations within and around the computing device 2400. A cooling device of the temperature regulation device 2428 may be associated with one or more temperature sensors of the temperature detection device 2426 and may be configured to operate based on temperatures detected the temperature sensors. For instance, a cooling device may be configured to determine whether a detected ambient temperature is above the target temperature or whether the detected ambient temperature is higher than the target temperature by a predetermined value or determine whether any other temperature-related condition associated with the temperature of the computing device 2400 is satisfied. In response to determining that one or more temperature-related condition associated with the temperature of the computing device 2400 are satisfied (e.g., in response to determining that the detected ambient temperature is above the target temperature), a cooling device may trigger its cooling mechanism and start to decrease the ambient temperature. Otherwise, the cooling device does not trigger any cooling. A cooling device of the temperature regulation device 2428 may operate with various cooling mechanisms, such as evaporation cooling, radiation cooling, conduction cooling, convection cooling, other cooling mechanisms, or any combination thereof. A cooling device of the temperature regulation device 2428 may include a cooling agent, such as a water, oil, liquid nitrogen, liquid helium, etc. In some embodiments, the temperature regulation device 2428 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator. In some embodiments, the temperature regulation device 2428 or any portions thereof (e.g., one or more of the individual cooling devices) may be connected to the computing device 2400 in close proximity (e.g., less than about 1 meter) or may be provided in a separate enclosure where a dedicated heat exchanger (e.g., a compressor, a heating, ventilation, and air conditioning (HVAC) system, liquid helium, liquid nitrogen, etc.) may reside.

[0181] By maintaining the target temperatures, the energy consumption of the computing device 2400 (or components thereof) can be reduced, while the computing efficiency may be improved. For example, when the computing device 2400 (or components thereof) operates at lower temperatures, energy dissipation (e.g., heat dissipation) may be reduced. Further, energy consumed by semiconductor components (e.g., energy needed for switching transistors of any of the components of the computing device 2400) can also be reduced. Various semiconductor materials may have lower resistivity and/or higher mobility at lower temperatures. That way, the electrical current per unit supply voltage may be increased by lowering temperatures. Conversely, for the same current that would be needed, the supply voltage may be lowered by lowering temperatures. As energy corelates to the supply voltage, the energy consumption of the semiconductor components may lower too. In some implementations, the energy savings due to reducing heat dissipation and reducing energy consumed by semiconductor components of the computing device or components thereof may outweigh (sometimes significantly outweigh) the costs associated with energy needed for cooling.

[0182] The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

[0183] FIG. 14 is a block diagram of an example processing device 2500 that may include one or more IC devices with angled transistors in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the processing device 2500 may include a die (e.g., the die 2002 of FIG. 10) having one or more angled transistors as described herein. Any one or more of the components of the processing device 2500 may include, or be included in, an IC device 2300 (FIG. 12). Any one or more of the components of the processing device 2500 may include, or be included in, an IC package 2200 of FIG. 11 or an IC device 2300 of FIG. 12. Any one or more of the components of the processing device 2500 may include, or be included in, a computing device 2400 of FIG. 13; for example, the processing device 2500 may be the processing device 2402 of the computing device 2400. [0184] A number of components are illustrated in FIG. 14 as included in the processing device 2500, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the processing device 2500 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single SoC die or coupled to a single support structure, e.g., to a single carrier substrate.

[0185] Additionally, in various embodiments, the processing device 2500 may not include one or more of the components illustrated in FIG. 14, but the processing device 2500 may include interface circuitry for coupling to the one or more components. For example, the processing device 2500 may not include a memory 2504, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a memory 2504 may be coupled.

[0186] The processing device 2500 may include logic circuitry 2502 (e.g., one or more circuits configured to implement logic/compute functionality). Examples of such circuits include ICs implementing one or more of input/output (I/O) functions, arithmetic operations, pipelining of data, etc.

[0187] In some embodiments, the logic circuitry 2502 may include one or more circuits responsible for read/write operations with respect to the data stored in the memory 2504. To that end, the logic circuitry 2502 may include one or more I/O ICs configured to control access to data stored in the memory 2504.

[0188] In some embodiments, the logic circuitry 2502 may include one or more high-performance compute dies, configured to perform various operations with respect to data stored in the memory 2504 (e.g., arithmetic and logic operations, pipelining of data from one or more memory dies of the memory 2504, and possibly also data from external devices/chips). In some embodiments, the logic circuitry 2502 may be configured to only control I/O access to data but not perform any operations on the data. In some embodiments, the logic circuitry 2502 may implement ICs configured to implement I/O control of data stored in the memory 2504, assemble data from the memory 2504 for transport (e.g., transport over a central bus) to devices/chips that are either internal or external to the processing device 2500, etc. In some embodiments, the logic circuitry 2502 may not be configured to perform any operations on the data besides I/O and assembling for transport to the memory 2504.

[0189] The processing device 2500 may include a memory 2504, which may include one or more ICs configure to implement memory circuitry (e.g., ICs implementing one or more of memory devices, memory arrays, control logic configured to control the memory devices and arrays, etc.). In some embodiments, the memory 2504 may be implemented substantially as described above with reference to the memory 2404 (FIG. 13). In some embodiments, the memory 2504 may be a designated device configured to provide storage functionality for the components of the processing device 2500 (i.e., local), while the memory 1604 may be configured to provide system-level storage functionality for the entire computing device 2400 (i.e., global). In some embodiments, the memory 2504 may include memory that shares a die with the logic circuitry 2502.

[0190] In some embodiments, the memory 2504 may include a flat memory (also sometimes referred to as a "flat hierarchy memory" or a "linear memory") and, therefore, may also be referred to as a "basin memory." As known in the art, a flat memory or a linear memory refers to a memory addressing paradigm in which memory may appear to the program as a single contiguous address space, where a processor can directly and linearly address all of the available memory locations without having to resort to memory segmentation or paging schemes. Thus, the memory implemented in the memory 2504 may be a memory that is not divided into hierarchical layer or levels in terms of access of its data.

[0191] In some embodiments, the memory 2504 may include a hierarchical memory. In this context, hierarchical memory refers to the concept of computer architecture where computer storage is separated into a hierarchy based on features of memory such as response time, complexity, capacity, performance, and controlling technology. Designing for high performance may require considering the restrictions of the memory hierarchy, i.e., the size and capabilities of each component. With hierarchical memory, each of the various memory components can be viewed as part of a hierarchy of memories (mi, m2, ..., m _n ) in which each member mi is typically smaller and faster than the next highest member m j+i of the hierarchy. To limit waiting by higher levels, a lower level of a hierarchical memory structure may respond by filling a buffer and then signaling for activating the transfer. For example, in some embodiments, the hierarchical memory implemented in the memory 2504 may be separated into four major storage levels: 1) internal storage (e.g., processor registers and cache), 2) main memory (e.g., the system RAM and controller cards), and 3) on-line mass storage (e.g., secondary storage), and 4) off-line bulk storage (e.g., tertiary, and off-line storage). However, as the number of levels in the memory hierarchy and the performance at each level has increased over time and is likely to continue to increase in the future, this example hierarchical division provides only one non-limiting example of how the memory 2504 may be arranged.

[0192] The processing device 2500 may include a communication device 2506, which may be implemented substantially as described above with reference to the communication chip 2406 (FIG. 13). In some embodiments, the communication device 2506 may be a designated device configured to provide communication functionality for the components of the processing device 2500 (i.e., local), while the communication chip 2406 may be configured to provide system-level communication functionality for the entire computing device 2400 (i.e., global).

[0193] The processing device 2500 may include interconnects 2508, which may include any element or device that includes an electrically conductive material for providing electrical connectivity to one or more components of, or associated with, a processing device 2500 or/and between various such components. Examples of the interconnects 2508 include conductive lines/wires (also sometimes referred to as "lines" or "metal lines" or "trenches") and conductive vias (also sometimes referred to as "vias" or "metal vias"), metallization stacks, redistribution layers, metal-insulator-metal (MIM) structures, etc.

[0194] The processing device 2500 may include a temperature detection device 2510 which may be implemented substantially as described above with reference to the temperature detection device 2426 of FIG. 13 but configured to determine temperatures on a more local scale, i.e., of the processing device 2500 of components thereof. In some embodiments, the temperature detection device 2510 may be a designated device configured to provide temperature detection functionality for the components of the processing device 2500 (i.e., local), while the temperature detection device 2426 may be configured to provide system-level temperature detection functionality for the entire computing device 2400 (i.e., global).

[0195] The processing device 2500 may include a temperature regulation device 2512 which may be implemented substantially as described above with reference to the temperature regulation device 2428 of FIG. 13 but configured to regulate temperatures on a more local scale, i.e., of the processing device 2500 of components thereof. In some embodiments, the temperature regulation device 2512 may be a designated device configured to provide temperature regulation functionality for the components of the processing device 2500 (i.e., local), while the temperature regulation device 2428 may be configured to provide system-level temperature regulation functionality for the entire computing device 2400 (i.e., global).

[0196] The processing device 2500 may include a battery/power circuitry 2514 which may be implemented substantially as described above with reference to the battery/power circuitry 2410 of FIG. 13. In some embodiments, the battery/power circuitry 2514 may be a designated device configured to provide battery/power functionality for the components of the processing device 2500 (i.e., local), while the battery/power circuitry 2410 may be configured to provide system-level battery/power functionality for the entire computing device 2400 (i.e., global).

[0197] The processing device 2500 may include a hardware security device 2516 which may be implemented substantially as described above with reference to the security interface device 2424 of FIG. 13. In some embodiments, the hardware security device 2516 may be a physical computing device configured to safeguard and manage digital keys, perform encryption and decryption functions for digital signatures, authentication, and other cryptographic functions. In some embodiments, the hardware security device 2516 may include one or more secure cryptoprocessors chips.

[0198] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Unless specified otherwise, in various embodiments, features described with respect to one of the drawings may be combined with those described with respect to other drawings.

[0199] The following paragraphs provide various examples of the embodiments disclosed herein.

[0200] Example Al provides an IC device that includes a support structure (e.g., a die, a substrate, a carrier substrate, etc.); a first transistor provided over the support structure; and a second transistor provided over the support structure, where each of the second transistor and the first transistor includes a source region, a drain region, and a channel region spatially between the source region and the drain region, where a shortest line extending between the source region and the drain region of the first transistor is substantially parallel to an edge (e.g., at least one of the edges) of the support structure, and where a shortest line extending between the source region and the drain region of the second transistor is at an angle between 10 degrees and 80 degrees with respect to the edge of the support structure. The edge of the support structure may be, e.g., an edge of one of the opposing front and back faces of the support structure.

[0201] Example A2 provides the IC device according to example Al, where the support structure has a first face and an opposing second face.

[0202] Example A3 provides the IC device according to example A2, where the first transistor is provided over a first region of the first face of the support structure, and the second transistor is provided over a second region, not overlapping with the first region, of the first face of the support structure (i.e., both transistors are provided over the same face, or on the same side, of the support structure). In some embodiments, the support structure may be a substrate of a semiconductor material or may be a substrate having a surface that includes a layer of a semiconductor material, and the non-angled and second transistors may be monolithically formed on the same face of the support structure so that channel regions of these transistors include the semiconductor material. [0203] Example A4 provides the IC device according to example A2, where the first transistor is provided over the first face of the support structure, and the second transistor is provided over the second face of the support structure. In some embodiments, the support structure may be a substrate of a semiconductor material or may be a substrate having a surface of the first face and a surface of the second face that includes a layer of a semiconductor material, and the non-angled and second transistors may be monolithically formed on different faces of the support structure so that channel regions of these transistors include the semiconductor material.

[0204] Example A5 provides the IC device according to example A4, where a projection of the second transistor onto the support structure fully overlaps with or is within a projection of the first transistor onto the support structure or the projection of the first transistor onto the support structure fully overlaps with or is within the projection of the second transistor onto the support structure.

[0205] Example A6 provides the IC device according to example A4, where a projection of the second transistor onto the support structure is offset with respect to (e.g., does not overlap, or overlaps by less than about 75%) a projection of the first transistor onto the support structure. [0206] Example A7 provides the IC device according to example A2, where the second transistor is one of a plurality of second transistors provided over the first face of the support structure, and the first transistor is nestled among the plurality of second transistors.

[0207] Example A8 provides the IC device according to example A2, where the first transistor is one of a plurality of first transistors provided over the first face of the support structure, and the second transistor is nestled among the plurality of first transistors.

[0208] Example A9 provides the IC device according to any one of examples A1-A8, where the support structure is a substrate that includes a semiconductor material, the channel region of the first transistor includes a first portion of the semiconductor material, and the channel region of the second transistor includes a second portion of the semiconductor material.

[0209] Example A10 provides the IC device according to example Al, where the support structure has a first face and an opposing second face, the first transistor is in a first layer over the first face of the support structure, the second transistor is in a second layer over the first face of the support structure (i.e., the first and second layers are over the same face of the support structure and are closer to that, first, face of the support structure than to the other, second, face of the support structure), and the IC device further includes a bonding layer between the first layer and the second layer.

[0210] Example All provides the IC device according to example A10, where the bonding layer includes a bonding material that includes an etch-stop material including silicon, nitrogen, and carbon, where an atomic percentage of each of silicon, nitrogen, and carbon within the etch-stop material is at least about 1%, e.g., at least about 5%, e.g., between about 1% and 50%, indicating that these elements are added deliberately, as opposed to being accidental impurities which are typically in concentration below about 0.1%. [0211] Example A12 provides the IC device according to any one of examples A10-A11, where the second layer is closer to the first face of the support structure than the first layer.

[0212] Example A13 provides the IC device according to example A12, further including a metallization stack, where the metallization stack is between the bonding layer and the first layer, and the bonding layer is between the metallization stack and the second layer (i.e., the metallization stack is a part of a first IC die that includes the first layer and the metallization stack on top of the first layer, where the first IC die is then bonded, face down, to the front of a second IC die that includes the second layer).

[0213] Example A14 provides the IC device according to example A13, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, where the redistribution layer is between the second layer and the bonding layer, and the bonding layer is between the redistribution layer and the metallization stack.

[0214] Example A15 provides the IC device according to example A12, further including a metallization stack, where the first layer is between the bonding layer and the metallization stack (i.e., the metallization stack is a part of a first IC die that includes the first layer and the metallization stack on top of the first layer, where the first IC die is then bonded, backside down, to the front of a second IC die that includes the second layer).

[0215] Example A16 provides the IC device according to example A15, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, where the redistribution layer is between the second layer and the bonding layer, and the bonding layer is between the redistribution layer and the first layer.

[0216] Example A17 provides the IC device according to any one of examples A10-A11, where the first layer is closer to the first face of the support structure than the second layer.

[0217] Example A18 provides the IC device according to example A17, further including a metallization stack, where the metallization stack is between the bonding layer and the second layer, and the bonding layer is between the metallization stack and the first layer (i.e., the metallization stack is a part of a second IC die that includes the second layer and the metallization stack on top of the second layer, where the second IC die is then bonded, face down, to the front of a first IC die that includes the first layer).

[0218] Example A19 provides the IC device according to example A18, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, where the redistribution layer is between the first layer and the bonding layer, and the bonding layer is between the redistribution layer and the metallization stack.

[0219] Example A20 provides the IC device according to example A17, further including a metallization stack, where the second layer is between the bonding layer and the metallization stack (i.e., the metallization stack is a part of a second IC die that includes the second layer and the metallization layer on top of the second layer, where the second IC die is then bonded, backside down, to the front of a first IC die that includes the first layer).

[0220] Example A21 provides the IC device according to example A20, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, where the redistribution layer is between the first layer and the bonding layer, and the bonding layer is between the redistribution layer and the second layer.

[0221] Example Bl provides an IC device that includes a support structure (e.g., a die, a substrate, a carrier substrate, etc.); and a plurality of angled structures (e.g., angled elongated semiconductor structures 306) provided over the support structure, the plurality of angled structures including at least a first angled structure (e.g., 306-1) and a second angled structure (e.g., 306-2), where each of the angled structures includes a first end (e.g., 328-1), a second end (e.g., 328-2) opposite the first end, and a longitudinal axis (e.g., 320) extending between the first end and the second end, where the longitudinal axis of each of the angled structures is at an angle between 10 degrees and 80 degrees with respect to an edge of the support structure (the edge of the support structure may be, e.g., an edge of one of the two opposing faces of the support structure), and where the longitudinal axis of the first angled structure and the longitudinal axis of the second angled structure is a shared longitudinal axis.

[0222] Example B2 provides the IC device according to example Bl, where the first end of the first angled structure is opposite the second end of the second angled structure (i.e., the first end of the first angled structure is closer to the second end of the second angled structure than the second end of the first angled structure, and the second end of the second angled structure is closer to the first end of the first angled structure than the first end of the second angled structure), and each of a projection of the first end of the first angled structure onto a plane parallel to the support structure and a projection of the second end of the second angled structure onto the plane is a straight line. [0223] Example B3 provides the IC device according to example B2, where the straight line of the projection of the first end of the first angled structure onto the plane is parallel to the straight line of the projection of the second end of the second angled structure onto the plane. [0224] Example B4 provides the IC device according to any one of examples B2-B3, where at least one (e.g., all) of the straight line of the projection of the first end of the first angled structure onto the plane and the straight line of the projection of the second end of the second angled structure onto the plane is substantially parallel to the edge of the support structure.

[0225] Example B5 provides the IC device according to any one of examples B2-B3, where at least one of the straight line of the projection of the first end of the first angled structure onto the plane and the straight line of the projection of the second end of the second angled structure onto the plane is at an angle between 10 degrees and 80 degrees with respect to the edge of the support structure.

[0226] Example B6 provides the IC device according to example B5, where at least one of a projection of the second end of the first angled structure onto the plane and a projection of the first end of the second angled structure onto the plane is substantially parallel to the edge of the support structure.

[0227] Example B7 provides the IC device according to any one of examples B1-B6, where the shared longitudinal axis is a first shared longitudinal axis, the plurality of angled structures further includes a third angled structure (e.g., 306-3) and a fourth angled structure (e.g., 306-4), the longitudinal axis of the third angled structure and the longitudinal axis of the fourth angled structure is a second shared longitudinal axis, and the first shared longitudinal axis (e.g., 320-1) and the second shared longitudinal axis (e.g., 320-2) are substantially parallel and at a distance to one another (i.e., they do not overlap or coincide).

[0228] Example B8 provides the IC device according to example B7, where the first end of the first angled structure is opposite the second end of the second angled structure (i.e., the first end of the first angled structure is closer to the second end of the second angled structure than the second end of the first angled structure, and the second end of the second angled structure is closer to the first end of the first angled structure than the first end of the second angled structure), where the first end of the third angled structure is opposite the second end of the fourth angled structure (i.e., the first end of the third angled structure is closer to the second end of the fourth angled structure than the second end of the third angled structure, and the second end of the fourth angled structure is closer to the first end of the third angled structure than the first end of the fourth angled structure), and where each of a projection of the first end of the first angled structure onto a plane parallel to the support structure, a projection of the second end of the second angled structure onto the plane, a projection of the first end of the third angled structure onto the plane, and a projection of the second end of the fourth angled structure onto the plane is a straight line. [0229] Example B9 provides the IC device according to example B8, where the straight line of the projection of the first end of the first angled structure onto the plane is parallel to the straight line of the projection of the second end of the second angled structure onto the plane, and the straight line of the projection of the first end of the third angled structure onto the plane is parallel to the straight line of the projection of the second end of the fourth angled structure onto the plane.

[0230] Example BIO provides the IC device according to any one of examples B8-B9, where at least one (e.g., all) of the straight line of the projection of the first end of the first angled structure onto the plane and the straight line of the projection of the second end of the second angled structure onto the plane is substantially parallel to the edge of the support structure, and at least one (e.g., all) of the straight line of the projection of the first end of the third angled structure onto the plane and the straight line of the projection of the second end of the fourth angled structure onto the plane is substantially parallel to the edge of the support structure.

[0231] Example Bll provides the IC device according to any one of examples B8-B10, where the straight line of the projection of the first end of the first angled structure onto the plane and the straight line of the projection of the first end of the third angled structure onto the plane are in different planes perpendicular to the support structure.

[0232] Example B12 provides the IC device according to example Bll, where the straight line of the projection of the second end of the second angled structure onto the plane and the straight line of the projection of the second end of the fourth angled structure onto the plane are in different planes perpendicular to the support structure.

[0233] Example B13 provides the IC device according to any one of examples B8-B12, where a distance between the straight line of the projection of the first end of the first angled structure onto the plane and the straight line of the projection of the second end of the second angled structure onto the plane is different from a distance between the straight line of the projection of the first end of the third angled structure onto the plane and the straight line of the projection of the second end of the fourth angled structure onto the plane.

[0234] Example B14 provides the IC device according to any one of examples B8-B10, where the straight line of the projection of the first end of the first angled structure onto the plane and the straight line of the projection of the first end of the third angled structure onto the plane are in a single first plane perpendicular to the support structure, and the straight line of the projection of the second end of the second angled structure onto the plane and the straight line of the projection of the second end of the fourth angled structure onto the plane are in a single second plane perpendicular to the support structure. [0235] Example B15 provides the IC device according to any one of examples B8-B10 or B14, where a distance between the straight line of the projection of the first end of the first angled structure onto the plane and the straight line of the projection of the second end of the second angled structure onto the plane is the same as a distance between the straight line of the projection of the first end of the third angled structure onto the plane and the straight line of the projection of the second end of the fourth angled structure onto the plane.

[0236] Example B16 provides the IC device according to example Bl, where the first end of the first angled structure is opposite the second end of the second angled structure (i.e., the first end of the first angled structure is closer to the second end of the second angled structure than the second end of the first angled structure, and the second end of the second angled structure is closer to the first end of the first angled structure than the first end of the second angled structure), and where each of a projection of the first end of the first angled structure onto a plane parallel to the support structure and a projection of the second end of the second angled structure onto the plane is a curved line.

[0237] Example B17 provides the IC device according to example B16, where the curved line of the projection of the first end of the first angled structure onto the plane and the curved line of the projection of the second end of the second angled structure onto the plane are parts of an ellipse or an oval.

[0238] Example B18 provides the IC device according to any one of examples B1-B17, where the angled structures include a semiconductor material.

[0239] Example B19 provides the IC device according to any one of examples B1-B18, where one or more of the angled structures are fins of one or more semiconductor materials, the fins extending away from a base (where the base may be a part of the support structure or may be between the support structure and the fins).

[0240] Example B20 provides the IC device according to any one of examples B1-B19, where one or more of the angled structures are nanoribbons of one or more semiconductor materials.

[0241] Example B21 provides the IC device according to any one of examples B1-B20, further including a transistor provided over the support structure, where the transistor includes a source region, a drain region, and a channel region spatially between the source region and the drain region, where a shortest line extending between the source region and the drain region of the transistor is the shared longitudinal axis, and where the channel region of the transistor includes a semiconductor material of the first angled structure (i.e., the transistor is formed based on the first angled structure). [0242] Example B22 provides the IC device according to example B21, further including a storage element coupled to the transistor.

[0243] Example B23 provides the IC device according to example B22, where the storage element is coupled to the source region or the drain region of the transistor.

[0244] Example B24 provides the IC device according to any one of examples B22-B23, where the storage element is one of a capacitor, a magnetoresistive material, a ferroelectric material, or a resistance-changing material.

[0245] Example B25 provides the IC device according to any one of examples B21-B24, where the transistor is a first transistor, the IC device further includes a second transistor provided over the support structure, and a shortest line extending between a source region of the second transistor and a drain region of the second transistor is substantially parallel to the edge of the support structure.

[0246] Example B26 provides the IC device according to example B25, where the support structure has a first face and an opposing second face.

[0247] Example B27 provides the IC device according to example B26, where the first transistor is provided over a first region of the first face of the support structure, and the second transistor is provided over a second region, not overlapping with the first region, of the first face of the support structure (i.e., both the non-angled and the second transistors are provided over the same face, or on the same side, of the support structure). In some embodiments, the support structure may be a substrate of a semiconductor material or may be a substrate having a surface that includes a layer of a semiconductor material, and the non-angled and second transistors may be monolithically formed on the same face of the support structure so that channel regions of these transistors include the semiconductor material.

[0248] Example B28 provides the IC device according to example B26, where the first transistor is provided over the first face of the support structure, and the second transistor is provided over the second face of the support structure. In some embodiments, the support structure may be a substrate of a semiconductor material or may be a substrate having a surface of the first face and a surface of the second face that includes a layer of a semiconductor material, and the non-angled and second transistors may be monolithically formed on different faces of the support structure so that channel regions of these transistors include the semiconductor material.

[0249] Example B29 provides the IC device according to example B28, where a projection of the second transistor onto the support structure fully overlaps with or is within a projection of the first transistor onto the support structure or the projection of the first transistor onto the support structure fully overlaps with or is within the projection of the second transistor onto the support structure.

[0250] Example B30 provides the IC device according to example B28, where a projection of the second transistor onto the support structure is offset with respect to (e.g., does not overlap, or overlaps by less than about 75%) a projection of the first transistor onto the support structure. [0251] Example B31 provides the IC device according to example B26, where the second transistor is one of a plurality of second transistors provided over the first face of the support structure, and the first transistor is nestled among the plurality of second transistors.

[0252] Example B32 provides the IC device according to example B26, where the first transistor is one of a plurality of first transistors provided over the first face of the support structure, and the second transistor is nestled among the plurality of first transistors.

[0253] Example B33 provides the IC device according to any one of examples B25-B32, where the support structure is a substrate that includes a semiconductor material, the channel region of the first transistor includes a first portion of the semiconductor material, and the channel region of the second transistor includes a second portion of the semiconductor material.

[0254] Example B34 provides the IC device according to example B25, where the support structure has a first face and an opposing second face, the first transistor is in a first layer over the first face of the support structure, the second transistor is in a second layer over the first face of the support structure (i.e., the first and second layers are over the same face of the support structure and are closer to that, first, face of the support structure than to the other, second, face of the support structure), and the IC device further includes a bonding layer between the first layer and the second layer.

[0255] Example B35 provides the IC device according to example B34, where the bonding layer includes a bonding material that includes an etch-stop material including silicon, nitrogen, and carbon, where an atomic percentage of each of silicon, nitrogen, and carbon within the etch-stop material is at least about 1%, e.g., at least about 5%, e.g., between about 1% and 50%, indicating that these elements are added deliberately, as opposed to being accidental impurities which are typically in concentration below about 0.1%.

[0256] Example B36 provides the IC device according to any one of examples B34-B35, where the second layer is closer to the first face of the support structure than the first layer.

[0257] Example B37 provides the IC device according to example B36, further including a metallization stack, where the metallization stack is between the bonding layer and the first layer, and the bonding layer is between the metallization stack and the second layer (i.e., the metallization stack is a part of a first IC die that includes the first layer and the metallization layer on top of the first layer, where the first IC die is then bonded, face down, to the front of a second IC die that includes the second layer).

[0258] Example B38 provides the IC device according to example B37, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, where the redistribution layer is between the second layer and the bonding layer, and the bonding layer is between the redistribution layer and the metallization stack.

[0259] Example B39 provides the IC device according to example B36, further including a metallization stack, where the first layer is between the bonding layer and the metallization stack (i.e., the metallization stack is a part of a first IC die that includes the first layer and the metallization layer on top of the first layer, where the first IC die is then bonded, backside down, to the front of a second IC die that includes the second layer).

[0260] Example B40 provides the IC device according to example B39, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, where the redistribution layer is between the second layer and the bonding layer, and the bonding layer is between the redistribution layer and the first layer.

[0261] Example B41 provides the IC device according to any one of examples B34-B35, where the first layer is closer to the first face of the support structure than the second layer.

[0262] Example B42 provides the IC device according to example B41, further including a metallization stack, where the metallization stack is between the bonding layer and the second layer, and the bonding layer is between the metallization stack and the first layer (i.e., the metallization stack is a part of a second IC die that includes the second layer and the metallization layer on top of the second layer, where the second IC die is then bonded, face down, to the front of a first IC die that includes the first layer).

[0263] Example B43 provides the IC device according to example B42, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, where the redistribution layer is between the first layer and the bonding layer, and the bonding layer is between the redistribution layer and the metallization stack.

[0264] Example B44 provides the IC device according to example B41, further including a metallization stack, where the second layer is between the bonding layer and the metallization stack (i.e., the metallization stack is a part of a second IC die that includes the second layer and the metallization layer on top of the second layer, where the second IC die is then bonded, backside down, to the front of a first IC die that includes the first layer).

[0265] Example B45 provides the IC device according to example B44, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, where the redistribution layer is between the first layer and the bonding layer, and the bonding layer is between the redistribution layer and the second layer.

[0266] Example Cl provides an IC device that includes a support structure (e.g., a die, a substrate, a carrier substrate, etc.); an elongated structure (e.g., a fin or a nanoribbon) of a semiconductor material provided over the support structure; and a further structure of the semiconductor material (i.e., the same material as the elongated structure), proximate to the elongated structure, where a projection of the elongated structure on the support structure is substantially a rectangle, and a projection of the further structure on the support structure is a curve.

[0267] Example C2 provides the IC device according to example Cl, where the projection of the further structure on the support structure has a U-shape.

[0268] Example C3 provides the IC device according to any one of examples C1-C2, where the rectangle has a first dimension in a first direction and a second dimension in a second direction, the first direction is perpendicular to the second direction, the first dimension greater than the second dimension, and the curve has a portion extending along the first direction.

[0269] Example C4 provides the IC device according to example C3, where a line along the first direction in the rectangle overlaps with a line along the first direction in the portion of the curve. [0270] Example C5 provides the IC device according to any one of examples C3-C4, where the first direction is at an angle between 10 degrees and 80 degrees with respect to an edge of the support structure (the edge of the support structure may be, e.g., an edge of one of the two opposing faces of the support structure).

[0271] Example C6 provides the IC device according to any one of examples C3-C5, where a dimension of the portion of the curve extending along the first direction is less than 10% of the first dimension of the rectangle.

[0272] Example C7 provides the IC device according to any one of examples C1-C6, where a distance between the elongated structure and the further structure is between about 3 nanometers and 1000 nanometers, e.g., between about 5 nanometers and 100 nanometers, or between about 10 nanometers and 75 nanometers. [0273] Example C8 provides the IC device according to any one of examples C1-C7, where the elongated structure is a fin extending away from the support structure, and the further structure is a curved structure extending away from the support structure.

[0274] Example C9 provides the IC device according to example C8, where a height of the fin is substantially equal to a height of the curved structure.

[0275] Example CIO provides the IC device according to any one of examples C1-C7, where the elongated structure is a nanoribbon extending parallel to the support structure, and the further structure is a curved structure extending parallel to the support structure.

[0276] Example Cll provides the IC device according to example CIO, further including an insulator material between the nanoribbon and the support structure and between the curved structure and the support structure.

[0277] Example C12 provides the IC device according to any one of examples Cl-Cll, where a distance from the support structure to a surface of the elongated structure that is farthest away from the support structure is substantially equal to a distance from the support structure to a surface of the further structure that is farthest away from the support structure.

[0278] Example C13 provides the IC device according to any one of examples C1-C12, further including an insulator material between the elongated structure and the further structure.

[0279] Example C14 provides the IC device according to any one of examples C1-C13, where the further structure is not electrically connected to any other elements or components of the IC device. [0280] Example C15 provides the IC device according to any one of examples C1-C14, where the further structure is enclosed by an insulator material on all sides (i.e., the further structure is not electrically connected to anything in the IC device).

[0281] Example DI provides an IC device that includes a support structure (e.g., a die, a substrate, a carrier substrate, etc.); a plurality of angled structures (e.g., angled elongated semiconductor structures 306) provided over the support structure, where an individual angled structure of the plurality of angled structures includes a semiconductor material and is an elongated structure having a longitudinal axis that is substantially parallel to the support structure and is at an angle between 10 degrees and 80 degrees with respect to an edge of the support structure (the edge of the support structure may be, e.g., an edge of one of the two opposing faces of the support structure); a plurality of IC components based on the plurality of angled structures, the plurality of IC components having a plurality of terminals; and an array of stacked via pairs, including a first stacked via pair, a second stacked via pair, and a third stacked via pair, each stacked via pair of the array including a first via electrically coupled to a different one of the terminals, and a second via stacked above and electrically coupled to the first via, where an overlap between the first via and the second via for the first stacked via pair is larger than the overlap for the second stacked via pair and the overlap for the third stacked via pair, and where the second stacked via pair and the third stacked via pair are on opposite sides of the first stacked via pair.

[0282] Example D2 provides the IC device according to example DI, where the overlap for the first stacked via pair is largest from all stacked via pairs of the array.

[0283] Example D3 provides the IC device according to any one of examples D1-D2, where the overlap decreases in a radially outward manner starting from the first stacked via pair.

[0284] Example D4 provides the IC device according to any one of examples D1-D3, where the overlap for the first stacked via pair is larger than the overlap of each stacked via pair that is a nearest-neighbor to the first stacked via pair.

[0285] Example D5 provides the IC device according to example D4, where the overlap for at least one stacked via pair that is the nearest-neighbor to the first stacked via pair is larger than the overlap for at least one stacked via pair that is a second-nearest-neighbor to the first stacked via pair.

[0286] Example D6 provides the IC device according to any one of examples D1-D5, where the overlap for at least two stacked via pairs that are nearest-neighbors to the first stacked via pair is larger than the overlap for at least two stacked via pairs that are second-nearest-neighbors to the first stacked via pair.

[0287] Example D7 provides the IC device according to any one of examples D1-D6, where, for the each stacked via pair, the first via is between the one of the terminals and the second via.

[0288] Example D8 provides the IC device according to any one of examples D1-D7, where the second vias of the array of stacked via pairs are arranged in rows and columns, for each of the rows, distances between different pairs of nearest-neighbor second vias of the row are substantially same, and, for each of the columns, distances between different pairs of nearest-neighbor second vias of the column are substantially same.

[0289] Example D9 provides the IC device according to example D8, where, for each of the rows, second vias of the row are aligned along a single line, and, for each of the columns, second vias of the column are aligned along a single line.

[0290] Example D10 provides the IC device according to any one of examples D1-D9, further including a plurality of non-angled structures (e.g., non-angled elongated semiconductor structures 304) provided over the array of stacked via pairs, where an individual non-angled structure of the plurality of non-angled structures includes a semiconductor material and is an elongated structure having a longitudinal axis that is substantially parallel to the support structure and is parallel or perpendicular with respect to the edge of the support structure (the same edge as in example 1); and a plurality of further IC components based on the plurality of non-angled structures, the plurality of further IC components having a plurality of further terminals, where one more of the second vias of the array of stacked via pairs are electrically coupled to one of more of the further terminals.

[0291] Example El provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of a central processing unit.

[0292] Example E2 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of a memory device, e.g., a high-bandwidth memory device.

[0293] Example E3 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device further includes a plurality of memory cells, each of the memory cells including a storage element.

[0294] Example E4 provides the IC device according to example E3, where the storage element is one of a capacitor, a magnetoresistive material, a ferroelectric material, or a resistance-changing material.

[0295] Example E5 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of a logic circuit.

[0296] Example E6 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of input/output circuitry.

[0297] Example E7 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of an FPGA transceiver.

[0298] Example E8 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of an FPGA logic.

[0299] Example E9 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of a power delivery circuitry.

[0300] Example E10 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of a lll-V amplifier.

[0301] Example Ell provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of PCIE circuitry or DDR transfer circuitry.

[0302] Example E12 provides an IC package that includes an IC device according to any one of the preceding examples A, B, C, D, or E; and a further IC component, coupled to the IC die.

[0303] Example E13 provides the IC package according to example E12, where the further IC component includes one of a package substrate, an interposer, or a further IC die. [0304] Example E14 provides a computing device that includes a carrier substrate and an IC device, coupled to the carrier substrate, where the IC device is an IC device according to any one of the preceding examples A, B, C, D, or E, or the IC device is included in the IC package according to any one of examples E12-E13.

[0305] Example E15 provides the computing device according to example E14, where the computing device is a wearable or handheld computing device.

[0306] Example E16 provides the computing device according to examples E14 or E15, where the computing device further includes one or more communication chips and an antenna.

[0307] Example E17 provides the computing device according to any one of examples E14- E16, where the carrier substrate is a motherboard.

[0308] Example E18 provides a method of manufacturing an IC device, the method including providing the IC device according to any one of the preceding examples.