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Title:
INTEGRATED CIRCUIT PACKAGE WITH INTERNAL CIRCUITRY TO DETECT EXTERNAL COMPONENT PARAMETERS AND PARASITICS
Document Type and Number:
WIPO Patent Application WO/2023/250234
Kind Code:
A3
Abstract:
Apparatus and techniques for an integrated circuit (IC) package to automatically detect, through an input/out pin, external component parameters and parasitics. An example IC package generally includes a pin for coupling to a component external to the IC package, and at least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin, and configured to detect at least one of a resistance, an inductance, or a capacitance, respectively, of a lumped parameter model for the component external to the IC package. The resistance detector, inductance detector, or capacitance detector may also be configured to detect parasitics associated with at least one of the component, the pin, or a connection between the component and the pin.

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Inventors:
YU CHENGYUE (US)
GUAN HUA (US)
CHEN YINGJIE (US)
YANG FAN (US)
PAN YUFEI (US)
JIANG JIZE (US)
AHMED SHAMIM (US)
Application Number:
PCT/US2023/067282
Publication Date:
March 07, 2024
Filing Date:
May 22, 2023
Export Citation:
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Assignee:
QUALCOMM INC (US)
International Classes:
H03K17/00; H03K17/16; H03K17/95; H03K17/955
Foreign References:
US9521712B12016-12-13
CN205427011U2016-08-03
EP2464008A12012-06-13
US20190219452A12019-07-18
CN1173233A1998-02-11
US20040059528A12004-03-25
Attorney, Agent or Firm:
ROBERTS, Steven E. et al. (US)
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