Title:
INTEGRATED CIRCUIT WITH AN AMPLIFIER
Document Type and Number:
WIPO Patent Application WO2003049284
Kind Code:
A3
Abstract:
An amplifier circuit comprises an input transistor Q1with a first control electrode coupled to the input In and a first main current channel coupled to the internal node 10. An output transistor Q4 has a second control electrode coupled to the internal node 10 and a second main current channel coupled to the output Out of the amplifier. An internal transistor Q2 has a third main current channel coupled to the internal node 10. The internal transistor Q2 serves to modify the impedance at the internal node 10, but a main low-frequency gain path from the first main channel Q1 to the second control electrode does not pass through the third main current channel Q2. The internal node 10 is coupled to ground via the third main current channel Q2 and a resistive element R1 successively. The resistance value of the resistive element R1 causes poles of a transfer function of the amplifier circuit to develop an imaginary frequency (resonant) component.
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Inventors:
BREUNISSE RAINIER A S (NL)
Application Number:
PCT/IB2002/005035
Publication Date:
February 12, 2004
Filing Date:
November 26, 2002
Export Citation:
Assignee:
KONINKL PHILIPS ELECTRONICS NV (NL)
BREUNISSE RAINIER A S (NL)
BREUNISSE RAINIER A S (NL)
International Classes:
H03F1/22; H03F3/343; H03F3/45; H03G1/00; (IPC1-7): H03F1/22; H03F1/42; H03G1/00
Foreign References:
| US5304946A | 1994-04-19 | |||
| US4879523A | 1989-11-07 |
Other References:
RIEMER D W: "An 10 nV/ square root Hz JFET input precision operational amplifier", IEEE 1990 BIPOLAR CIRCUITS AND TECHNOLOGY MEETING, 17 September 1990 (1990-09-17), pages 223 - 225, XP010007985
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