DESCRIPTION

INTEGRATED CIRCUIT WITH IDDQ TEST FACILITIES AND IC IDDQ TEST

METHOD

The present invention relates to an integrated circuit (IC) comprising a first power rail and a second power rail, a plurality of circuit portions respectively coupled between the first power supply rail and the second power supply rail, the plurality of circuit portions comprising a first circuit portion, the first circuit portion being coupled to the first power supply rail via a first conductive path comprising first enabling switching means.

The present invention further relates to a method of measuring a quiescent current (I _DD Q) of the first circuit portion of such an IC.

In the field of integrated circuit (IC) manufacturing, testing the ICs prior to their release to customers is of importance to reduce the risk of faulty ICs being released. To this end, ICs are typically subjected to a number of different tests in order to increase the fault coverage of the test procedure. The test procedure typically comprises different types of tests, including tests that test the correct functional behaviour of the ICs, e.g. by feeding the IC with test patterns and capturing the response of the IC to those patterns.

However, such functional tests do not capture all possible IC defects. For instance, certain types of structural faults, e.g. certain types of bridges or shorts may not lead to incorrect functional behaviour, although such faults can be equally unacceptable, for instance because the IC draws an excessive amount of current from a power supply, which may be an indication of a limited lifetime expectancy of the IC or may pose overheating risks, amongst others.

A particularly useful test method to detect such structural faults is I _DD Q testing. During such a test an IC is brought into a defined steady (quiescent) state, from which the current flow is measured. The amount of current flowing through the IC in this steady state is a measure of its quality, with an unusually

high flow indicating the presence of structural faults. Unfortunately, with the increasing complexity of ICs, I _DD Q testing has lost some popularity because the increase in current flow caused by a structural fault has become more difficult to detect due to the fact that IC technology scaling has increased the variation and magnitude of the I _DD Q of properly functioning ICs, thus making it more difficult to dinstinguish between correct and faulty IC behaviour.

In US patent US 6,043,672, a solution is disclosed for measuring the I _DD Q of only a part of an IC. To this end, the IC is divided into sections, with each section being coupled to a unitary power supply via a selectable power supply switch. These switches have been added to the power supply to facilitate the disconnecting of selected sections of the IC from the power supply during test. To facilitate I _DD Q testing at a section level, each section additionally has its own dedicated power supply. In the I _DD Q test mode, a section is disconnected from the unitary power supply by disabling the appropriate selectable power supply switch and connected to its dedicated I _DD Q power supply. The supply current drawn from the I _DD Q power supply is measured to determine the I _DD Q current for that section rather than for the whole IC. This reduces the background current of the measurement and makes a structural error easier to detect. This solution not only has the disadvantage that test specific switches have to be placed in the functional mode unitary power supply, but in addition a large number of additional external terminals are required for invoking an I _DD Q test on an IC section basis. This makes implementation of this solution expensive, because additional external terminals such as additional pins or bond pads significantly increase the cost of an IC.

The present invention seeks to provide an IC that facilitates separate I _DD Q measurements of multiple portions of the IC without requiring additional power supplies to each portion. The present invention further seeks to provide a method for measuring the I _DD Q of a portion of such an IC.

According to a first aspect of the present invention, there is provided an IC according to the opening paragraph, the first circuit portion further being coupled to a power supply rail via a second conductive path for enabling a quiescent current measurement of the first circuit portion in a test mode of the integrated circuit, the second conductive path comprising further switching means for coupling the first portion to the test mode power supply rail in the test mode.

The present invention takes advantage of the fact that most circuit portions, e.g. cores, of an IC have switching means, e.g. one or more enable transistors, coupled between the first power supply rail and the circuit portion to facilitate switching the circuit portion to a standby mode in the functional mode of the IC. In a test mode of the IC, the conductive path between the first portion and the first power supply rail is switched from the first conductive path to the second conductive path by disabling the first switching means and enabling the additional further switching means. The use of the further switching means, which for instance may comprise one or more sensing switches, makes it possible to use only a single pad coupled to the test mode power supply rail for providing each of the circuit portions of the IC with a current source for the I _DD Q measurement. The selection of the appropriate sensing switches ensures that only selected parts of the IC under test are subjected to an I _D DQ test.

Moreover, if the IC further comprises current sensing means coupled between the sensing means and the test mode power supply rail, the first power supply rail may be used as the test mode power supply rail because the I _DD Q measurement is performed on-chip. This obviates the need for an additional power supply rail and additional pad for coupling the additional rail to a power supply; only an output for making the I _DD Q measurement result of the current sensing means externally available is required.

In an embodiment, the first circuit portion comprises a plurality of voltage islands; the first switching means comprise a plurality of enable switches, each enable switch being coupled between the first power supply rail and a respective voltage island; and the further switching means comprise a

plurality of sensing switches, each sensing switch being coupled between the test mode power supply rail and a respective voltage island. This facilitates a more fine-grained I _DD Q measurement; a voltage island, e.g. a part of an IC core that has its own internal voltage rails connected to a global supply rail via its own enable switch, may be switched off and its sensing switch may be enabled to facilitate an I _DD Q measurement of that particular part of the circuit portion of the IC of the present invention.

The further switching means, e.g. the one or more sensing switches typically are responsive to a test enable signal, which in case of multiple sensing switches may be combined with a selection signal to activate selected sensing switches. Such selection signals may be provided in a number of ways. A preferred way of providing such selection signals is by means of a shift register, because this only requires a single date shift input on the IC.

According to a further aspect of the present invention, there is provided a method for I _DD Q testing the IC of the present invention, the method comprising bringing the integrated circuit in the test mode; providing the first circuit portion with a test stimulus;disabling at least a part of the first switching means; enabling at least a part of the further switching means; and measuring a quiescent current via the enabled part of the further switching means. This method facilitates I _DD Q measurements of various parts of an IC without requiring dedicated supply pads for each of these parts.

The present invention is described in more detail and by way of examples only and with reference to the accompanying drawings, in which:

Fig. 1 schematically depicts an integrated circuit having a plurality of circuit portions;

Fig. 2 shows a circuit portion according to an embodiment of the present invention; Fig. 3 shows a circuit portion according to another embodiment of the present invention;

Fig. 4 shows a circuit portion according to yet another embodiment of the present invention;

Fig. 5 shows a circuit portion according to yet another embodiment of the present invention; Fig. 6 shows a detail of an integrated circuit of the present invention; and

Fig. 7 shows a circuit portion according to yet another embodiment of the present invention.

It should be understood that the Figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the Figures to indicate the same or similar parts.

Fig. 1 shows an IC 10 having a plurality of circuit portions 100. Each circuit portion 100 is coupled between a first power supply rail 110, e.g. a V _DD rail, and a second power supply rail 130, e.g. ground (GND) via respective enable switches 120 and further enable switches 140. These switches may be controlled and implemented in any known way. A possible implementation is by means of nMOS and pMOS transistors in a CMOS technology, although it will be obvious to the skilled person that other implementations, e.g. in other technologies are equally feasible. The enable switches 120 and the further enable switches 140 facilitate the power-down of a circuit portion 100 in the functional mode of the IC 10 when the functionality of the circuit portion 100 is not required. This is a well-known arrangement to reduce the power consumption of the IC 10 during its operation.

In Fig. 1 , both power supply rails 110 and 130 are coupled to the circuit portions 100 via enable switches. This is by way of example only. Alternative arrangements are equally feasible, e.g. an arrangement in which only one of the two supply rails is coupled to the circuit portion 100 via an enable switch, with the other supply rail being directly coupled to the circuit portion 100. Similarly, Fig.1 shows a single enable switch between a power supply rail and circuit portion 100 by way of example only; it is equally feasible that the IC 10

comprises multiple switches arranged in parallel between a power supply rail and a circuit portion 100.

Fig. 2 shows a first embodiment of a detail of an IC 10 according to the present invention. A circuit portion 100 is coupled to the first power supply rail 110 via enable switch 120. In addition, the first power supply rail 110 is coupled to the circuit portion 100 via sensing switch 220. The sensing switch 220 may be implemented in the same manner as the enable switch 120, although the dimensions of the sensing switch 220 may differ from the enable switch 120. The sensing switch 220 is coupled to an output 240 of the IC 10 via current sensor 230. This facilitates on-chip determination of the I _DD Q, with the first power supply rail 110 providing the current in the test mode of IC 10. In other words, the first power supply rail 110 acts as the test mode power supply rail during the _IDD Q test.

The output of the current sensor 230 may be coupled to the output 240 via a shift register (not shown) for shifting out the test result. The latter is particularly advantageous if all the circuit portions 100 of the IC 10 have an I _DD Q test arrangement as shown in Fig. 2, in which case the shift register may collect the test results of all the circuit portions 100. Alternatively, the current sensor 230 may be omitted to facilitate off-chip determination of the I _DD Q- This will be discussed in more detail later.

In a test mode, the circuit portion 100 is brought into a test prepared state by providing the circuit 100 with an appropriate test stimulus. Next, the enable switch 120 is disabled and the sensing switch 220 is enabled to allow the circuit portion 100 to draw an I _DD Q from the IC power supply via power supply rail 110 via sensing switch 220. The I _DD Q can be observed using current sensor 230 in the path from the sensing switch 220 to the output 240. The test result is presented on output 240.

In Fig. 2, the further enable switch 140 between the circuit portion 100 and second power supply rail 130 has been omitted by way of example only. In fact, the IC 10 may comprise a further sensing switch (not shown) arranged between the circuit portion 100 and the second power supply rail 130, which may be in addition to or instead of the sensing switch 220.

In Fig. 3, the sensing switch 220 is coupled to a separate supply rail 310, which acts as the test mode supply rail during the I _DD Q test and is coupled to an external connection 340, e.g. a pin or pad of IC 10. This arrangement facilitates off-chip measurement of the I _DD Q of circuit portion 100 by providing the current source to the circuit portion through the further power supply rail 310 and the sensing switch 220.

Fig. 4 shows a circuit portion 400 comprising multiple voltage islands. In the context of the present invention, a voltage island is a part of a circuit portion that can be individually coupled to the power supply rails of the IC 10, and typically has its own internal power supply rail, although a voltage island may also be a discrete subblock of a larger IC portion.

In Fig. 4, each voltage island has its own internal supply rail 410, which is coupled to the first power supply rail 110 via respective enable switches 120. The circuit portion 400 has three voltage islands, having respective internal supply rails 410a-c. Each voltage island further has a further internal supply rail 420, which is coupled to the second power supply rail 130. The further internal supply rails 420a-c may be coupled to the further power supply rail 130 via respective further enable switches (not shown), which may be used in addition to or instead of the enable switches 120. The circuit portion 400 comprises circuitry 430 distributed over its voltage islands. In Fig. 4, the circuitry 430 is depicted as logic circuitry by way of example only. Other types of circuitry, e.g. sequential circuitry or data retention circuitry are equally feasible.

The IC 10 further comprises a plurality of sensing switches 220, with each switch 220 coupled between an internal supply rail 410 of a voltage island and the first power supply rail 110 via current sensor 230. The current sensor 230 is coupled to an output 240 of the IC 10.

The method of the present invention can be used to subject the circuit portion 100 to an I _DD Q test in the following manner. In a first step, the IC 10 is brought in a test mode. This is typically done by providing the IC 10 with a test enable signal. The circuit portion 400 is then provided with a test stimulus to bring the circuit portion 400 in a predefined, i.e. test prepared state. Next, at

least one of the enable switches 120 is switched off such that its corresponding voltage island is disconnected from the first power supply rail 110. The other switches 120 remain enables to ensure that the circuitry fed by the other voltage islands remain in a well defined rather than a floating state. The sensing switches coupled to the disconnected voltage island (or voltage islands) are enabled such that the voltage island becomes connected to the first power supply rail 110 via the sensing switch 220, and the I _DD Q of this voltage island is subsequently measured.

The method of the present invention facilitates I _DD Q testing at different hierarchical levels. The I _DD Q test may be executed at the circuit portion, e.g. core, level. In addition, a spatial I _DD Q test of a part of a circuit portion may be performed, i.e. an I _DD Q test in which only a subset of the plurality of internal supply rails of the circuit portion is included. This provides a superior fault localization resolution over known methods. In the embodiment shown in Fig. 4, the IDDQ measurement is performed on-chip using the built-in current sensor 230. The current sensor 230 provides the output 240 with the test result for evaluation external to the IC 10.

Alternatively, the I _DD Q current measurement may be performed off-chip. Fig. 5 shows a part of IC 10 that facilitates an off-chip I _DD Q measurement. In Fig. 5, the sensing switches 220 are coupled between the respective voltage islands of the circuit portion 400 and a further power supply rail 310, which is coupled to a pin or pad 340 of the IC 10. In Fig. 5, all sensing switches 220 have individual conductive paths to the further power supply rail 310 by way of example only; alternatively, the sensing switches 220 may share a single conductive path to the further power supply rail 310, in which case all sensing switches 220 may be conductively coupled to node 502.

During test, the enable switch 120 of a voltage island under test is disabled and the corresponding sensing switch 220 is enabled. The voltage island under test draws its I _DD Q from the further supply rail 310, which provides a current via pin or pad 340. The current drawn via this pin or pad facilitates an off-chip I _DD Q measurement, e.g. with an external automated test device.

The size of a voltage island may be designed such that a minimum required resolution in the I _DD Q measurement is guaranteed. The leakage current of a given island can be expressed by Equation (1 ): island island ± δi (1) where i _ιsland and Ai represent the average leakage current per island and the variability of the leakage current respectively. δ/ can be decomposed as it is shown in Equation (2) into leakage current variations due to process variations (i _process ) and environmental conditions (i _ec ).

^A i = ϊ process + iec (2)

The minimum defective current that can be detected will determine the maximum leakage current per island and therefore the sizing of the islands as it is shown in Equation (3): ^ Range ^ι ιsland ~ . ¹ DEFECT \^} max ACCUraCy mm

Range and Accuracy are the specifications given by the measurement equipment used to perform the I _DD Q testing. For instance, when using the Agilent 93000 SoC tester from Agilent, the ratio between Range and Accuracy is in the order of 500 for all the possible ranges. As previously mentioned, the sensing switches 220 may be sized differently than the enable switches 120. The sizing for the sensing switches 220 is based in the leakage current per island. Typically, the size of the enable switches 120 is determined by the active current (dynamic + leakage) of the circuit portion 100 or 400, e.g. a core. In the present invention, the enable switch 120 dimensions may need to be adjusted to match the active current requirements (dynamic + leakage) of the island they control, as will be discussed below.

The size of the sensing switches 220 may be determined as follows. The equivalent island resistance of its corresponding voltage island is given by the following expression:

_ (V _DD - AV)

^K ,sland ^{~ ~} (4)

* leak where V _DD , are the supply voltage, the voltage drop across the enable switch 120 and the leakage current of the island respectively. In other words, AV is defined as the difference in voltage between the power supply rail 110 and the internal power supply rail 410. I _leαk defines the defect- free leakage current of the voltage island.

The channel resistance of the sensing switch 220 can be expressed as:

^{Sene ~} UV _os -V _th ) W - ^{Kτ '} w & where K ₁ is a constant for a given process technology for the sensing switch 220, e.g. a MOS transistor operating in linear region with low drain- source (V _DS ) voltages, W and L are the transistor channel width and length of the sensing transistor respectively.

By using Equations (4) and (5), the voltage drop δF across the sensing switch 220 must be no more than AV , and can therefore be expressed as:

AV'≤ I _leαk K _τ ^ (6)

Rearranging Equation (6), the lower bound for the sensing switch 220 geometry can be obtained:

where n = AV/V _DD represents the allowed relative voltage drop across the sensing switch 220.

The same procedure can be applied to the sizing of the enable switches 120. As dynamic current has also to be taken into account for the sizing of the enable switches 120, the dynamic current term has to be included in the denominator of Equation (4).

Fig. 6 shows an embodiment of a control circuit for controlling the enable switches 120 and the sensing switches 220 in the test mode of the IC 10. In Fig. 6, a control circuit for these switches being pMOS switches is

shown. Modifications of this circuit for other types of switches are routine skill exercises for the skilled person, and will not be discussed here for this reason.

The enable switch 120 is responsive to an enable signal SB. The enable signal SB is also provided to logic gate 600, which is a NAND gate in case of the enable switch 120 and the sensing switch 220 being pMOS transistors. Hence, apart from being used to control the various circuit portions

100 or 400 in the functional mode of the IC 10, the control signal SB is also used in the test mode of the IC 10 as a test configuration signal to configure which parts of the IC 10 will be subjected to an I _DD Q test. The logic gate 600 further receives a test enable signal TE. When both TE and SB are a logic high, the logic gate 600 will produce a logic low, thus enabling the sensing switch 220. This triggers the flow of the I _DD Q 610 through the circuit portion or voltage island under test, which is measured by current sensor 230. Each pair of enable switches 120 and sensing switches 220 may have its own control circuit as shown in Fig. 6.

In a preferred embodiment, the control signals SB for the various control circuits of the IC 10 are provided by means of a shift register (not shown), which may be a dedicated test shift register, such as a shift register compliant with the boundary scan standard IEEE 1149.1 or the system-on-chip test standard IEEE 1500. This shift register is typically fed with a switch configuration data pattern, i.e. a plurality of signals SB via a further input (not shown) of the IC 10, such as the IEEE 1149.1 compliant TDI pin. However, alternative ways of providing the control signals SB, e.g. by making the controller of the enable switches 120 in the functional mode of the IC 10 responsive to a test instruction, are also feasible.

In Figures 4 and 5, the voltage island partitioning of the circuit portion 400 has been based on utilizing the row structure of the internal supply rails 410a-c. Fig. 7 shows an alternative way of partitioning a circuit portion of the IC 10. The circuit portion 700 has four voltage islands, with each voltage islands having an internal supply rail 710, 720, 730 and 740 respectively. Each internal supply rail is coupled to the first supply rail 110 via respective enable switches 120, and via respective sensing switches 220 to facilitate on-chip I _DD Q

measurements using current sensor 230. Each sensing switch 220 is controlled by a logic circuit 600, with each logic circuit 600 receiving the test enable signal TE and one of the control signals S1 , S2, S3, S4 for controlling the enable switch 120 of the corresponding voltage island. The control signals S1 , S2, S3, S4 may be provided by a shift register (not shown) as previously explained.

Many other ways of partitioning a circuit portion, such as a core, of the IC 10 of the present invention will be apparent to the skilled person.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.