Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
INTEGRATED CIRCUIT WITH SCAN CHAIN AND CHIP TESTING METHOD
Document Type and Number:
WIPO Patent Application WO/2011/044796
Kind Code:
A1
Abstract:
An integrated circuit with a scan chain and a chip testing method are disclosed. The integrated circuit (20) includes a first interface group (11), a second interface group (14) and a scan data selector (12). The first interface group (11) and the second interface group (14) each respectively include at least two I/O ports which can be packaged as external pins of the integrated circuit. Each I/O port of the first interface group (11) corresponds to the input end of the scan data selector (12). The output end of the scan data selector (12) is connected with the scan data input end of the scan chain (13). The scan data output end of the scan chain (13) is connected with each I/O port of the second interface group (14).

Inventors:
XIE WUHONG (CN)
Application Number:
PCT/CN2010/076448
Publication Date:
April 21, 2011
Filing Date:
August 30, 2010
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
ACTIONS SEMICONDUCTOR CO LTD (CN)
XIE WUHONG (CN)
International Classes:
G01R31/3185
Foreign References:
CN1996035A2007-07-11
US20070150781A12007-06-28
CN1516015A2004-07-28
US20080195346A12008-08-14
CN101387685A2009-03-18
CN1748154A2006-03-15
US6848067B22005-01-25
Other References:
See also references of EP 2428808A4
None
Attorney, Agent or Firm:
SHENZHEN ZHONGYI PATENT AND TRADEMARK OFFICE (CN)
深圳中一专利商标事务所 (CN)
Download PDF: