Title:
INTEGRATED CMOS CIRCUIT CONFIGURATION, AND PRODUCTION OF SAME
Document Type and Number:
WIPO Patent Application WO1998052211
Kind Code:
A3
Abstract:
An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surface of a semiconductor substrate. The MOS transistors are arranged relative to one another such that a current flow through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the MOS transistors.
Inventors:
KRAUTSCHNEIDER WOLFGANG (DE)
HOFMANN FRANZ (DE)
RISCH LOTHAR (DE)
HOFMANN FRANZ (DE)
RISCH LOTHAR (DE)
Application Number:
PCT/DE1998/001154
Publication Date:
February 18, 1999
Filing Date:
April 24, 1998
Export Citation:
Assignee:
SIEMENS AG (DE)
KRAUTSCHNEIDER WOLFGANG (DE)
HOFMANN FRANZ (DE)
RISCH LOTHAR (DE)
KRAUTSCHNEIDER WOLFGANG (DE)
HOFMANN FRANZ (DE)
RISCH LOTHAR (DE)
International Classes:
H01L27/092; H01L21/8238; (IPC1-7): H01L/
Foreign References:
| US4799097A | 1989-01-17 |
Other References:
"CMOS Inverter", IBM TECHNICAL DISCLOSURE BULLETIN., vol. 27, no. 12, May 1985 (1985-05-01), NEW YORK US, pages 7046 - 7048, XP002082101
M. J. DECLERCQ: "Application of the Anisotropic etching of silicon to the Development of Complementary Structures", 1974 INTERNATIONAL ELECTRON DEVICES MEETING, 9 December 1974 (1974-12-09), pages 519 - 522, XP002082102
M. J. DECLERCQ: "Application of the Anisotropic etching of silicon to the Development of Complementary Structures", 1974 INTERNATIONAL ELECTRON DEVICES MEETING, 9 December 1974 (1974-12-09), pages 519 - 522, XP002082102
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