RELATED APPLICATIONS

[001] The application claims priority to U.S. Non-provisional Patent Application No. 16/145,819 filed on September 28, 2018, and entitled“Integrated Self-Driven Active Clamp”, which claims priority to U.S. Provisional Patent

Application No. 62/625,691 filed on February 2, 2018, and entitled“Integrated Adaptive Active Clamp,” all of which is hereby incorporated by reference for all purposes.

BACKGROUND

[002] Switch-mode power supplies (SMPS) are power management components in modern electronic devices. They provide, among other things, power efficient and galvanically isolated power to multiple loads. To achieve high power processing efficiency and/or galvanic isolation, conventionally one or more magnetically coupled elements, semiconductor switches and associated gate driver circuits are required.

[003] The magnetically coupled elements often suffer from non-trivial leakage inductance phenomena, which necessitate the need for affordable voltage snubber circuits to control the semiconductor switch peak drain-to- source voltages. Because of the price- sensitive nature of SMPS, the snubber circuits are conventionally limited to the cost-effective passive and power lossy resistor-capacitor-diode (RCD) configurations.

[004] In systems sensitive to power losses and heat generation, the dissipation in lossy components in the form of heat is unsuitable. Thus, recycling of energy using an active clamping configuration within the system provides an opportunity for system form-factor reduction and power efficiency improvement.

[005] Additionally, clamping the maximum drain- source voltages of switching power transistors allows for increased device reliability and use of power transistors with improved figure-of-merit (FOM). The improved FOM enables the SMPS to operate at higher switching frequency while maintaining high power processing efficiency. Furthermore, it allows for a reduction of the SMPS reactive component size and cost. SUMMARY

[006] In some embodiments, an active clamp circuit includes an active clamp capacitor coupled in series with an active clamp switch and an active clamp controller circuit. The active clamp controller circuit receives an active clamp switch current that passes through the active clamp switch and controls the active clamp switch based on the received active clamp switch current. The active clamp controller circuit is configured to enable the active clamp switch based on a first amplitude comparison, the first amplitude comparison being based on the active clamp switch current. The active clamp controller circuit is configured to disable the active clamp switch based on a second amplitude comparison and a third amplitude comparison, the second amplitude comparison and the third amplitude comparison being based on the active clamp switch current.

[007] In some embodiments, an apparatus includes a power converter circuit to convert an input voltage from a voltage source to an output voltage. The power converter circuit includes a transformer which has a primary winding and a secondary winding, a first winding node of the primary winding being coupled to the voltage source to receive the input voltage. The apparatus includes a main switch that is coupled to a second winding node of the primary winding to control a current through the primary winding, and an active clamp circuit to clamp a voltage at the second winding node of the primary winding. The active clamp circuit includes: i) a series circuit combination of an active clamp capacitor coupled in series to an active clamp switch, the series circuit combination being coupled in parallel with the primary winding, and ii) an active clamp controller circuit to receive an active clamp switch current that passes through the active clamp switch and to control the active clamp switch based on the active clamp switch current. The active clamp controller circuit is configured to enable the active clamp switch based on a first amplitude comparison, the first amplitude comparison being based on the active clamp switch current. The active clamp controller circuit is configured to disable the active clamp switch based on a second amplitude comparison and a third amplitude comparison, the second amplitude comparison and the third amplitude comparison being based on the active clamp switch current.

BRIEF DESCRIPTION OF THE DRAWINGS [008] FIG. 1 is a simplified circuit schematic of a conventional power converter.

[009] FIG. 2 is a simplified circuit schematic of a power converter with a self-driven active clamp circuit, in accordance with some embodiments.

[0010] FIG. 3 is a simplified circuit schematic of a self-driven active clamp circuit, in accordance with some embodiments.

[0011] FIG. 4 is a simplified plot of signals related to a self-driven active clamp circuit, in accordance with some embodiments.

[0012] FIG. 5A is a simplified plot of signals related to a power converter with a self-driven active clamp circuit, in accordance with some embodiments.

[0013] FIG. 5B is a simplified plot of signals related to a power converter with a conventional clamp circuit.

[0014] FIG. 6 is a simplified circuit schematic of a portion of a power converter with a self-driven active clamp circuit, in accordance with some

embodiments.

[0015] FIG. 7 is a simplified circuit schematic of a portion of a power converter with a self-driven active clamp circuit, in accordance with some

embodiments.

[0016] FIG. 8 is a simplified circuit schematic of a portion of a power converter with a self-driven active clamp circuit, in accordance with some

embodiments.

[0017] FIG. 9A is a simplified plot of signals related to a power converter with a self-driven active clamp circuit, in accordance with some embodiments.

[0018] FIG. 9B is a simplified plot of signals related to a power converter with a conventional clamp circuit.

[0019] FIG. 10 is a screenshot showing experimental results of a power converter with a self-driven active clamp circuit, in accordance with some

embodiments.

[0020] FIG. 11 is a portion of a process for clamping a voltage of a main switch of a power converter using a self-driven active clamp circuit, in accordance with some embodiments.

[0021] FIG. 12 is a portion of a process for clamping a voltage of a main switch of a power converter using a self-driven active clamp circuit, in accordance with some embodiments. DETAILED DESCRIPTION

[0022] Some embodiments described herein provide a self-driven active clamp circuit and self-driven active clamping methods for use in a power converter that converts an input voltage to an output voltage using a transformer. In some embodiments, the self-driven active clamp described herein replaces a diode of a resistor-capacitor-diode (RCD) snubber circuit of a conventional power converter, advantageously converting the conventional power converter into a power converter having self-driven active clamping without needing to change additional control circuits of the power converter (such as a primary- side power management integrated circuit, or a secondary side synchronous switch controller integrated circuit). In other embodiments, the self-driven active clamp circuit is integrated into an initial design of a power converter.

[0023] The self-driven active clamp circuit advantageously increases power processing efficiency of a power converter by recycling energy stored in a leakage inductance of the transformer. To further improve light-to-medium power processing efficiency, in some embodiments, the active clamp circuit is advantageously disabled during light- load and low-line operation of the power converter (e.g., when a drain- source voltage of a primary side switch is below a voltage threshold, such as 500V).

[0024] In accordance with some embodiments, the self-driven active clamp circuit clamps a primary side peak voltage of a main switch, which enables the power converter to utilize primary side and/or secondary side switches having a lower voltage rating, leading to reduced power losses during switch conduction and/or switching. In some embodiments, the self-driven active clamp circuit turns on when a body-diode of an active clamp field effect transistor (FET) switch of the self-driven active clamp circuit begins conducting (e.g., a source-drain current of the switch is flowing through the switch) and turns off when near a second zero crossing of the source-drain current through the switch. Thus, an on-time of the self-driven active clamp circuit can be advantageously reduced as compared to conventional active clamp solutions because the active clamp switching does not need to coincide with a main switch turn-on time. As a result, a smaller active clamp capacitor can be utilized as compared to conventional clamping circuits because the active clamp circuit resonant period is shorter. Because the active clamp capacitor is a high voltage component, using a smaller capacitance can result in significant cost reduction benefits.

[0025] At light loads, zero- voltage- switching is conventionally difficult to achieve using conventional active clamp circuits because the period between main switch tum-on times is significantly longer. Embodiments of the self-driven active clamp circuit described herein allow for near zero- voltage- switching of the main switch on the primary side of the power converter across a wide range of output load currents, without the need for accurate modulation of the transformer magnetizing inductance current value. Such embodiments induce a low-amplitude resonant magnetizing inductance current, via discharging of the active clamp capacitor, which amplifies the quasi-resonant voltage amplitude. This advantageously results in near zero-voltage switching of the main- switch during quasi-resonant operation at the first valley, and significantly reduced main switch turn-on voltage at second and higher valleys.

[0026] A further advantage of the self-driven active clamp circuit described herein is a significantly lower active clamp RMS current (e.g., reduction of up to lOx), as compared to conventional active clamp zero-voltage-switching methods.

This enables the self-driven active clamp circuit to utilize an active clamp switch having a higher RDSON (drain-source on-resistance) as compared to conventional active clamp circuits, resulting in an active clamp circuit which is lower cost, easier to integrate, and having a smaller physical size than conventional active clamp circuits.

[0027] FIG. 1 is a simplified circuit schematic of a conventional power converter (“converter”) 100. Some elements of the power converter 100 have been omitted from FIG. 1 to simplify the description of power converter 100 but are understood to be present. A voltage source V _m ’ is received at the converter 100. V _m ’ can be provided either as an alternating current (AC) or direct current (DC). An input side of the converter 100 generally includes an input voltage filter block 122, a rectifier block 116 (in the case of AC input), an input voltage buffer capacitor Cl, an RCD snubber circuit block 114 (which includes a capacitor C2, a resistor Rl and a diode Dl), a main switch Ml, and a main switch controller circuit (“controller”) 118. The input voltage filter block 122, rectifier block 116 and the input buffer capacitor Cl provide a filtered, buffered, rectified, or otherwise conditioned input voltage V _m to a transformer 102. [0028] The transformer 102 transfers power from the input side of the converter 100 to an output side of the converter 100 and generally includes a primary winding 104 with a first node 108 and a second node 110, and a secondary winding 106. The output side of the converter 100 generally includes an output buffer circuit 112, a synchronous rectifier switch M2, a synchronous rectifier switch controller circuit (“controller”) 120, and a load (not shown).

[0029] The first node 108 receives V _m , and the second node 110 is coupled to a terminal of the main switch Ml at the second node 110. The main switch Ml controls a current through the primary winding 104 to charge a magnetizing inductance L _M of the transformer 102 during a first portion of a switching cycle of the converter 100. The synchronous rectifier switch M2 controls a current flow through the secondary winding 106 to discharge the transformer 102 into output buffer circuit 112 and/or a load during a subsequent portion of the switching cycle. In some embodiments, one or both of the main switch Ml and/or the synchronous rectifier switch M2 are field-effect transistors (FETs), each having a drain node, a source node, and a gate node to control a conduction of current between the drain node and the source node. In other embodiments, the synchronous rectifier switch M2 is replaced with a diode.

[0030] When the main switch Ml is enabled by the controller 118 during the first portion of a switching cycle, current flows through the primary winding 104 to a voltage bias node such as ground. The current flow through the primary winding 104 causes energy to be stored in the magnetization inductance L _M and a leakage inductance L _L of the transformer 102. When the main switch Ml is disabled in a subsequent portion of the switching cycle, output voltage V _out is generated at the output buffer circuit 112 and is provided to a load (not shown). When the main switch Ml is turned off, a reflected voltage (nV _out ) is developed at a drain node of the main switch Ml at node 110. The contribution of the reflected voltage nV _out to a drain- source voltage V _ds of the main switch Ml at the node 110 is expressed as:

Vds = Vin ₊ nVout (Equation 1)

where n is a turns ratio of the transformer 102. Energy stored in the leakage inductance L _L of the transformer 102 also contributes to the voltage V _ds developed at the node 110.

[0031] The RCD snubber circuit 114 prevents the voltage V _ds from increasing to a level that damages the main switch ML As V _ds rises, the diode D1 becomes forward biased and current flows into the capacitor C2 and into the resistor Rl to dissipate energy, thereby clamping V _ds to a level that is within a safe operating range of the main switch Ml. To further increase the efficiency of the converter 100, the diode Dl can be replaced with an actively driven clamp switch driven by an active clamp drive signal. However, conventional active clamping circuits require a control signal or other means of synchronization from the controller 118. Thus, a converter 100 that uses a controller 118 that is not already configured to support conventional active clamping cannot easily be modified to implement active clamping.

[0032] FIG. 2 is a simplified circuit schematic of a power converter

(“converter”) 200 with a self-driven active clamp circuit 214, in accordance with some embodiments. Some elements of the power converter 200 have been omitted from FIG. 2 to simplify the description of the power converter 200 but are understood to be present. The converter 200 generally includes the circuit elements discussed with reference to FIG. 1. However, all, or a portion (e.g., the diode Dl), of the snubber circuit 114 of the converter 100 has been replaced with the self-driven active clamp circuit (“active clamp circuit”) 214. Advantageously, the active clamp circuit 214 can replace the snubber circuit 114 of the converter 100 without making significant modifications to the converter 100 (e.g., it does not require a control signal or other synchronization signal from the controllers 118, 120). Thus, a converter 100 that was manufactured with a snubber circuit similar to the snubber circuit 114 can be modified with the self-driven active clamp circuit 214 to perform active clamping.

For example, in some embodiments, the diode Dl of the conventional snubber circuit 114 can be replaced with the self-driven active clamp circuit 214. A magnetizing inductance current I _LM flowing out of the primary winding 104 is described later with reference to FIG. 5 A.

[0033] FIG. 3 is a simplified circuit schematic of the self-driven active clamp circuit 214 of the converter 200 introduced with reference to FIG. 2, in accordance with some embodiments. Some elements of the self-driven active clamp circuit 214 have been omitted from FIG. 3 to simplify the description of the self-driven active clamp circuit 214 but are understood to be present. The active clamp circuit 214 generally includes an active clamp switch controller circuit 302 which provides an active clamp switch control signal to the active clamp switch M3 via a gate driver circuit 314. The active clamp circuit 214 additionally includes a first current amplitude comparison circuit 304, a second current amplitude comparison circuit 306, a voltage peak detection and enable circuit 308, a voltage source circuit 316 (e.g., an LDO), an active clamp switch M3 having a body-diode D2, and an active clamp capacitor C3. The active clamp capacitor C3 is coupled in a series with the active clamp switch M3, and the series combination of the active clamp capacitor C3 and the active clamp switch M3 are coupled in parallel with the primary winding 104. The first current amplitude comparison circuit 304, the second current amplitude comparison circuit 306, the voltage peak detection and enable circuit 308, and the active clamp switch controller circuit 302 are referred to herein as being of an active clamp controller circuit. The active clamp capacitor C3 can advantageously be of a lower voltage rating as compared to the voltage rating of capacitor C2 of a conventional RCD circuit 114, thus providing cost savings. For example, in an example embodiment, the active clamp capacitor C3 can have a 250V rating as compared to a 630V rating of the capacitor C2. In some embodiments, the resistor Rl of the conventional RCD 114 can advantageously be omitted from the active clamp circuit 214, providing further cost savings.

[0034] The voltage source circuit 316 receives a voltage 318 and increases, decreases, or otherwise conditions the voltage 318 to power the gate driver circuit 314 in order to drive (i.e., enable and disable) the active clamp switch M3. In some embodiments, the active clamp switch M3 is a current-bidirectional two-quadrant switch. In some embodiments, the active clamp switch M3 is a field-effect transistor (FET) having a drain node (i.e., a first switch node), a source node (i.e., a second switch node), and a gate node (i.e., a switch control node) to control a conduction of current between the drain node and the source node. The drain node and the source node of the active clamp switch M3 are in a series circuit combination with the active clamp capacitor C3. The gate node of the active clamp switch M3 controls a current between the drain node and the source node of the active clamp switch M3. In some embodiments, the active clamp switch M3 includes a diode, other than a body-diode, which is configured to pass a current between the source node and the drain node (in a first current direction) when the diode is forward biased (e.g., when sufficient voltage is developed across the source and drain of the active clamp switch M3). When the gate node of the active clamp switch M3 is driven by the switch control signal, the active clamp switch M3 passes current bidirectionally (e.g., in the first current direction, and/or a second current direction). In the first current direction, current flows from the primary winding 104, through the active clamp switch M3, and into the active clamp capacitor C3. In the second current direction, current flows from the active clamp capacitor C3, through the active clamp switch M3, and into the primary winding 104.

[0035] The voltage peak detection and enable circuit 308 generally includes a voltage comparison circuit 310, a diode D3 and a capacitor C4. The capacitor C4 couples a first input of the voltage comparison circuit 310 to the node 110 to receive the drain-source voltage Vds of the main switch M3. The voltage comparison circuit 310 receives a voltage threshold 312 (e.g., from a voltage source circuit, not shown) at a second input. In some embodiments, the voltage threshold 312 is a voltage level above which the main switch M3 could be damaged. In other embodiments, the voltage threshold 312 is a voltage level that corresponds to a heavy load operation of the converter 200. In still other embodiments, the voltage threshold is a voltage level that corresponds to medium or heavy load operation of the converter 200. The voltage peak detection and enable circuit 308 transmits an enable signal to the active clamp switch controller circuit 302 when a voltage across the main switch M3 is equal to or surpasses the voltage threshold 312. The voltage peak detection and enable circuit 308 transmits a disable signal to the active clamp switch controller circuit 302 when a voltage across the switch M3 does not equal or surpass the voltage threshold 312. Thus, the active clamp switch controller circuit is configured to disable the active clamp switch M3 in response to a voltage amplitude of a voltage developed across the main switch Ml being less than the voltage threshold 312 (e.g., 500 V), irrespective of a current surpassing the first current threshold 320. That is, for as long as the active clamp switch controller circuit 302 receives a de-asserted signal at the ENABLE input, the active clamp switch M3 is disabled and the output PWM signal is not transitioned based on signals received by the active clamp switch controller circuit 302 at the SET and RESET inputs from the current amplitude comparison circuits 304, 306. In contrast, when the voltage comparison signal indicates that the received voltage surpasses the voltage threshold 312 (ENABLE is asserted), the output PWM signal is based on the SET and RESET signals received, by the active clamp switch controller circuit 302, from the current amplitude comparison circuits 304, 306. Thus, in some embodiments, the self-driven active clamp circuit 214 is advantageously disabled during light load operation of the converter 200, further increasing power efficiency. [0036] During a portion of the switching cycle when the main switch Ml and active clamp switch M3 are both off, an active clamp switch current i _Sd flows from the primary winding 104, through the body-diode D2, to the active clamp capacitor C3. During a subsequent portion of the switching cycle when the main switch Ml is off and the active clamp switch M3 is on, the current i _Sd oscillates between the active clamp capacitor C3, the magnetizing inductance LM, and other intended or parasitic reactive elements of the converter 200.

[0037] At a high level, the active clamp switch M3 is enabled if the current ISD surpasses a first current threshold 320 due to the current ISD flowing from the primary winding 104 to the active clamp capacitor C3 through the body diode D2 of the active clamp switch M3 (e.g., body diode conduction of the D2 is detected). The active clamp switch M3 is disabled if a second zero crossing of the current ISD is detected. A first zero-crossing of the current ISD is determined to have occurred if the current ISD is less than a second current threshold 322, due to the current ISD flowing from the active clamp capacitor C3 into the primary winding 104 through the enabled active clamp switch M3. The second zero-crossing of the current ISD is determined to have occurred if the current ISD is greater than the second current threshold 322 at a later time, due to current flowing from the primary winding 104 to the active clamp capacitor C3 through the enabled active clamp switch M3. Upon determining that the second zero-crossing of the current ISD has occurred, the active clamp switch M3 is disabled.

[0038] To elaborate, the first current amplitude comparison circuit 304 receives the current i _Sd at a first input, receives or generates the first current threshold 320 at a second input (e.g., from a first current source circuit, not shown), compares the received current i _Sd to the first current threshold 320, and transmits a first comparison signal to a SET input of the active clamp switch controller circuit 302. In some embodiments, the first current threshold 320 is a current amplitude that identifies body-diode conduction of the active clamp switch M3. In some

embodiments, the first current threshold 320 is about 50mA to 250mA, such as lOOmA. The second current amplitude comparison circuit 306 receives the current i _Sd at a first input, receives or generates the second current threshold 322 at a second input (e.g., from a second current source circuit, not shown), compares the received current i _Sd to the second current threshold 322, and transmits second and third comparison signals to a RESET input of the active clamp switch controller circuit 302. In some embodiments, the second current threshold 322 is a current amplitude that identifies a first and second zero-crossing of the current i _Sd , the RESET input of the active clamp switch controller circuit 302 receiving an asserted second comparison signal in response to the second current amplitude circuit 306 detecting the first zero crossing of the current i _Sd , and receiving a de-asserted third comparison signal in response to the second current amplitude circuit 306 detecting the second zero crossing of the current i _Sd . In some embodiments, the second current threshold 322 is about -300mA to 0mA, such as -50mA. In some embodiments, the first zero-crossing of the current i _Sd is determined by the current i _Sd transitioning across the second current threshold 322 with a negative going slope, and the second zero-crossing of the current i _Sd is determined by the current i _Sd transitioning across the second current threshold 322 with a positive going slope.

[0039] Thus, a PWM signal to drive the active clamp switch M3 via the gate driver circuit 314 is generated by the active clamp switch controller circuit 302 based on the comparison result signals received at SET and RESET inputs from the comparison circuits 304, 306. The PWM signal is transmitted to the gate driver circuit 314 to control the active clamp switch M3. FIG. 4 provides an example plot 400 illustrating a relationship between the SET and RESET comparison signals 402, 406 and a resultant PWM signal output 404 of the active clamp switch controller circuit 302, in accordance with some embodiments.

[0040] As shown, a rising edge of the SET comparison signal 402 received from the first current amplitude comparison circuit 304 (due to detecting body-diode conduction of M3) triggers a first edge 404a of the PWM signal 404. A falling edge of the SET comparison signal 402 does not cause the PWM signal 404 to change state. Likewise, a rising edge of the RESET comparison signal 406 received from the second current amplitude comparison circuit 306 (due to detecting a first zero crossing of the current ISD) does not cause the PWM signal 404 to change state.

However, a falling edge of the RESET comparison signal 406 (due to detecting a second zero-crossing of the current ISD) triggers a second edge 404b of the PWM signal 404. Thus, in the embodiment shown, the active clamp switch M3 is enabled when the current i _Sd surpasses the first current threshold 320 (e.g., when the current i _Sd is flowing through the body diode D2 to the active clamp capacitor C3). The active clamp switch M3 is disabled when a second zero-crossing of the current ISD is detected (e.g., when the current i _Sd is resonating due to the magnetizing inductance LM, the active clamp capacitor C3, and other reactive components).

[0041] In some embodiments, the converter 200 relies on an indirect resonant mechanism to achieve near zero-voltage tum-switching of the main switch Ml. FIG. 5A shows a simplified graph 502 which provides operation details of the converter 200, in accordance with some embodiments. In comparison, FIG. 5B shows a simplified graph 550, which provides operation details of a converter having a conventional active clamp circuit. In both graph 502 and graph 550, the voltage V _ds at the node 1 10 and a current flow ILM of the transformer 102 over time t is shown.

The current I _LM is shown in graph 502 as having an opposite polarity to that of the current i _Sd introduced with reference to FIG. 3 _. As was described with reference to FIG. 3, the active clamp switch M3 enable signal (PWM) 506 is generated in response to an amplitude of the current flow ISD (negative ILM). The simplified graph 502 corresponding to the converter 200 illustrates advantageous zero-voltage switching of the active clamp switch M3 at region 504 when the body-diode D2 is conducting, zero-current switching of the active clamp switch M3 at region 508, and near-zero voltage switching of the main switch Ml at region 514. The near-zero voltage switching of the main switch Ml in region 514 is achieved via a second-order effect arising from the operation of the active clamp circuit 214 as described herein.

Specifically, when the active clamp circuit 214 is operational, the active clamp capacitor C3 voltage is maintained at a voltage value approximately equal to the reflected output voltage. As a result, at the instant when the converter 200 enters region 514 (quasi-resonant mode) the voltage across the active clamp switch M3 is approximately zero and the equivalent circuit becomes an LC circuit as shown in the simplified circuit schematic 700 of FIG. 7 (L is due to the transformer 102

magnetizing inductance and C is the equivalent capacitance Ceq seen at node 110).

Of note is that the equivalent capacitance Ceq as seen at node 110 is dominated by the respective capacitance of the active clamp switch CossM3 and the active clamp capacitor C3 capacitance (as shown in the simplified schematic 700 of FIG. 7), which are in the nF range (several orders of magnitude greater than that of a conventional converter 100 with the RCD snubber circuit block 114). Due to the relatively large equivalent capacitance Ceq, the resonant magnetizing inductance current amplitude, ILM ¹ (as shown in FIG. 7), is forced to a larger value (as shown in FIG. 9A) as compared to the case where a conventional RCD snubber is utilized and the voltage at the clamp capacitor is significantly larger than the reflected output voltage (as shown in Fig. 9B). The peak magnetizing inductance current can be approximated according to the well-known LC resonant conservation of energy equation,

(Equation 2),

where Ceq is the equivalent capacitance at node 110 and i i is a magnetizing inductance current (shown in FIG. 7 as i ¹ ). Because the amplitude of the magnetizing inductance current is forced to a higher value initially, and because the equivalent capacitance Ceq as seen at node 110 falls to pF range once the main switch Ml drain- source voltage begins to fall (a simplified schematic 800 of an equivalent circuit at this point is shown in FIG. 8), the voltage value at the valleys is forced to a lower voltage value (e.g., 2-3x time less as compared to a conventional RCD circuit).

[0042] Furthermore, a width of the PWM pulse 506 is significantly and advantageously shorter than a PWM pulse 556 corresponding to a conventional active clamp with zero-voltage switching of the main switch Ml at region 564. An RMS current i _rm s of the graph 502 is significantly less than an RMS current i _rm s of the graph 550, due to the peak currents being of the same amplitude i _P k but the resonant period (and duty-ratio D, of the on-time/switching period) of the graph 502 being an order of magnitude less than graph 550, as given by the equation,

i _rms = ipk ' f (Equation 3),

thus, a smaller active clamp capacitor C3 (on the order of nanofarads) can be used, as compared to a conventional active clamp circuit which may require an active clamp capacitor being on the order of hundreds of nanofarads. Based on the near zero voltage crossing at region 514, the main switch Ml is switched on (e.g., resulting in pulse MIEN 516) when voltage V _ds at node 110 is equal to Vi _n - knV _out , where k is an integer value.

[0043] FIGS. 6-8 highlight parasitic capacitive and inductive elements of the converter 200 which resonate during quasi-resonant operation of the converter 200, a portion of the switching cycle when the main switch Ml and the synchronous rectifier switch M2 are both off. A simplified circuit schematic 600 of FIG. 6 includes elements of the converter 200 introduced in FIG. 2, as well as a representation of magnetizing inductance LM 130, parasitic capacitance CossM3 of the active clamp switch M3, parasitic capacitance CossMl of the main switch Ml, and parasitic capacitance CossM2 of the synchronous rectifier switch M2. Also shown is an active clamp switch voltage VA _C which is a drain- source voltage of the active clamp switch M3. The dominant capacitive elements along with the range of their capacitance values for two different active clamp switch voltages are illustrated in the simplified circuit schematics 700, 800 of FIGS. 7-8, respectively.

[0044] The simplified circuit schematic 700 of FIG. 7 illustrates particular capacitive and inductive elements of the converter 200 during a portion of the switching cycle when the voltage across the capacitance CossM3 is approximately equal to zero volts, the voltage across the active clamp capacitor C3 is approximately equal to nV _out , and the voltage V _ds at node 110 is equal to Vi _n + nV _out . At this time, the combined capacitance of the active clamp capacitor C3 and the parasitic capacitance CossM3 of the active clamp switch M3 is on the order of nanofarads.

The parasitic capacitance CossMl of the main switch Ml is on the order of picofarads, and the parasitic capacitance CossM2 of the synchronous rectifier switch M2 is on the order of picofarads.

[0045] The simplified schematic 800 of FIG. 8 illustrates particular capacitive and inductive elements of the converter 200 during a portion of the switching cycle when the voltage across the capacitance CossM3 is approximately equal to negative nV _out , and the voltage across the active clamp capacitor C3 is approximately equal to nV _out , resulting in the voltage V _ds at node 110 being less than the input voltage Vi _n . During this portion of the switching cycle, the active clamp capacitor C3 voltage is significantly larger than the reflected output voltage nVout. The combined capacitance of the active clamp capacitor C3 and the parasitic capacitance CossM3 of the active clamp switch M3 is on the order of picofarads. The parasitic capacitance CossMl of the main switch Ml is on the order of picofarads, and the parasitic capacitance CossM2 of the synchronous rectifier switch M2 is on the order of picofarads. A current ILM ² of the magnetizing inductance 130 is also shown.

[0046] The large difference in the capacitive values is important because the initial large effective capacitance leads to higher magnetizing inductance current (during LC resonance):

(Equation 4)

where Vp _eak is equal to the reflected voltage nV _out on the primary side of the transformer 102, L _M is the magnetizing inductance 130, and Ceq is the equivalent capacitance of the intended and parasitic capacitances as seen at node 110 shown in FIGS. 6-8. The large difference in the capacitive values occurs due to a large active clamp FET output capacitance CossM3 of the active clamp switch M3 when its drain- source voltage is zero, which is only the case when the active clamp circuit 214 is enabled (e.g., when energy stored in the active clamp capacitor C3 is recycled during each switching cycle).

[0047] A simplified graph 900 of FIG. 9A illustrates voltage V _ds at node 110 and a magnetizing inductance current im (im ^1-2 ) of the magnetizing inductance 130 over time t during a quasi-resonant operation of the converter 200, in accordance with some embodiments. A simplified graph 950 of FIG. 9B is a plot of voltage V _ds and current i over time t during a quasi-resonant portion of the switching cycle for a conventional lossy RCD snubber circuit. The simplified graph 900 illustrates the non linear effect of Equation 4 when the active clamp capacitor C3 voltage VAC is approximately equal to the reflected output voltage (e.g., VAC ~ nV _out ), as compared to the simplified graph 950 which illustrates a conventional lossy snubber operation where the snubber capacitor voltage is significantly greater than the reflected output voltage (e.g., VAC > 1.5 X nV _out ).

[0048] As shown in the simplified graph 900, the active clamp circuit 214 allows for a higher magnetizing current im as compared to the conventional lossy snubber circuit shown in the simplified graph 950. The higher magnetizing current im, in turn, enables more charge to be removed from the main switch Ml, thus leading to lower drain-source voltages Vds during quasi-resonant operation of the converter 200.

[0049] FIG. 10 is a screenshot 1000 of experimental results of Vds over time for a converter 200 having an active clamp circuit 214, in accordance with some embodiments. A first portion 1002 of the screenshot 1000 shows voltage Vds at node 110 during operation of the converter 200 when the active clamp circuit 214 is disabled. A second portion 1052 of the screenshot 1000 shows voltage Vds at node 110 during operation of the converter 200 when the active clamp circuit 214 is enabled and the active clamp capacitor voltage VAC is approximately equal to the reflected output voltage nVout. As shown, when the active clamp 214 is enabled, the main switch Ml drain-source voltage at the valleys is significantly smaller (e.g., lOOVdc vs. 225Vdc at the first valley; l25Vdc vs. 240Vdc at the second valley and etc.). The benefit of the reduced valley voltage is due to the reduced main switch CossMl energy dissipated, which is a function of the voltage squared, when the main switch Ml is turned on.

[0050] FIG. 11 is a portion of an example process for clamping a voltage of a main switch of a power converter (e.g., the power converter 200), in accordance with some embodiments. The particular steps, order of steps, and combination of steps are shown for illustrative and explanatory purposes only. Other embodiments can implement different particular steps, orders of steps, and combinations of steps to achieve similar functions or results. At step 1102, an input voltage is received at a primary winding (104) of a transformer (102) of the power converter (200). At step 1104, a current through the primary winding (104) is controlled using a main switch (Ml) of the power converter (200). At step 1106, a voltage of the main switch (e.g., at node 110) is clamped to a maximum voltage using an active clamp circuit (214). The voltage of the main switch (Ml) is clamped based on an active clamp switch current (ISD) that passes through an active clamp switch (M3) of the active clamp circuit (214). Details of step 1106 are presented in FIG. 12, in accordance with some embodiments. The particular steps, order of steps, and combination of steps are shown for illustrative and explanatory purposes only. Other embodiments can implement different particular steps, orders of steps, and combinations of steps to achieve similar functions or results.

[0051] At step 1202, the active clamp switch current (ISD) is received at a first current amplitude comparison circuit (304) at a first time. At step 1204, it is determined, using the first current amplitude comparison circuit, if the active clamp switch current is greater than a first current threshold (320) (e.g., lOOmA). If it is determined at step 1204 that the active clamp switch current is not greater than the first current threshold, flow returns to step 1202. If it is determined at step 1204 that the active clamp switch current is greater than the first current threshold (e.g., a body- diode of the active clamp switch M3 is conducting), flow continues to step 1206. At step 1206, the active clamp switch (M3) is enabled (e.g., turned on), thereby clamping a voltage at the main switch (Ml). At step 1208, the active clamp switch current is received at a second current amplitude comparison circuit (306) at a second time. At step 1210, it is determined, using the second current amplitude comparison circuit, if the active clamp switch current is less than a second current threshold (322) (e.g., - 50mA). If it is determined at step 1210 that the active clamp switch current is not less than the second current threshold, flow returns to step 1208. If it is determined at step 1210 that the active clamp switch current is less than the second current threshold (e.g., a first zero crossing of the active clamp switch current), flow continues to step 1212. At step 1212, the active clamp switch current is received at the second current amplitude comparison circuit at a third time. At step 1214, it is determined, using the second current amplitude comparison circuit, if the active clamp switch current is greater than the second current amplitude comparison circuit. If it is determined at step 1214 that the active clamp switch current is not greater than the second current threshold, flow returns to step 1212. If it is determined at step 1214 that the active clamp switch current is greater than the second current threshold (e.g., a second zero crossing of the active clamp switch current), flow continues to step 1216. At step 1216, the active clamp switch (M3) is disabled (e.g., it is turned off). When the active clamp switch is turned off, the active clamp circuit (214) is no longer clamping a voltage of a main switch (Ml) of the power converter (200).

[0052] Reference has been made in detail to embodiments of the disclosed invention, one or more examples of which have been illustrated in the accompanying figures. Each example has been provided by way of explanation of the present technology, not as a limitation of the present technology. In fact, while the specification has been described in detail with respect to specific embodiments of the invention, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to these embodiments. For instance, features illustrated or described as part of one embodiment may be used with another embodiment to yield a still further embodiment. Thus, it is intended that the present subject matter covers all such modifications and variations within the scope of the appended claims and their equivalents. These and other modifications and variations to the present invention may be practiced by those of ordinary skill in the art, without departing from the scope of the present invention, which is more particularly set forth in the appended claims. Furthermore, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only and is not intended to limit the invention.