YIN, Youyun (No. 3009, BYD Road Pingsha, Shenzhen Guangdong 8, 518118, CN)
DONG, Chao (No. 3009, BYD Road Pingsha, Shenzhen Guangdong 8, 518118, CN)
LI, Bing (No. 3009, BYD Road Pingsha, Shenzhen Guangdong 8, 518118, CN)
XU, Wenhui (No. 3009, BYD Road Pingsha, Shenzhen Guangdong 8, 518118, CN)
YIN, Youyun (No. 3009, BYD Road Pingsha, Shenzhen Guangdong 8, 518118, CN)
DONG, Chao (No. 3009, BYD Road Pingsha, Shenzhen Guangdong 8, 518118, CN)
LI, Bing (No. 3009, BYD Road Pingsha, Shenzhen Guangdong 8, 518118, CN)
| WHAT IS CLAIMED IS: 1 . An intelligent power circuit, comprising: a pulse modulating unit configured to receive a controlling signal, to convert an ascending edge of the controlling signal into a first narrow pulse signal, and to convert a descending edge of the controlling signal into a second narrow pulse signal; a low voltage transceiver connected with the pulse modulating unit and configured to receive and transmit the first narrow pulse signal and the second narrow pulse signal; a signal transformer connected with the low voltage transceiver and configured to transform a voltage of the first narrow pulse signal and a voltage of the second narrow pulse signal from a low voltage to a high voltage respectively; a high voltage transceiver connected with the signal transformer and configured to receive and transmit the first narrow pulse signal and the second narrow pulse signal; a rectifying unit connected with the high voltage transceiver and configured to rectify the first narrow pulse signal and the second narrow pulse signal received from the high voltage transceiver to obtain the controlling signal; a driving unit connected with the rectifying unit and configured to control a connected power module according to the controlling signal; an insertion unit connected with the high voltage transceiver and configured to obtain a representation of a serial digital signal by using the first narrow pulse signal and the second narrow pulse signal to generate a signal with a first feature representing bit 0 of the serial signal and a second feature representing bit 1 of the serial signal and to transmit the signal with the first feature and the second feature to the high voltage transceiver; wherein the high voltage transceiver is further configured to receive and transmit the signal with the first feature and the second feature; the signal transformer is further configured to transform the signal with the first feature and the second feature from the high voltage to the low voltage and to transmit the signal with the first feature and the second feature to the low voltage transceiver; and the low voltage transceiver is further configured to receive and transmit the signal with the first feature and the second feature, and a de-insertion unit connected with the low voltage transceiver and the pulse modulating unit and configured to de-insert and obtain the serial digital signal from the first narrow pulse signal and the second narrow pulse signal according to the first feature and the second feature of the signal received from the low voltage transceiver. 2. The intelligent power circuit of claim 1 , wherein the de-insertion unit de-inserts and obtains the serial digital signal from the first narrow pulse signal and the second narrow pulse signal by determining the signal sending from the low voltage transceiver is with the first feature or with the second feature. 3. The intelligent power circuit of claim 1 , wherein the insertion unit obtains the first feature by inserting a third narrow pulse signal at a first time period after sending the first narrow pulse signal; and the insertion unit obtains the second feature by inserting a third narrow pulse signal at a second time period after sending the first narrow pulse signal. 4. The intelligent power circuit of claim 3, wherein a pulse width of the controlling signal is greater than or equal to a sum of a pulse width of the first narrow pulse signal, a longer one of the first time period and the second time period and a pulse width of the third narrow pulse signal. 5. The intelligent power circuit of claim 2, wherein: the de-insertion unit obtains a bit 0 of the serial digital signal if the signal with the first feature is received from low voltage transceiver; the de-insertion unit obtains a bit 1 of the serial digital signal if the signal with the second feature is received from low voltage transceiver; and the de-insertion unit obtains the serial digital signal as a result of getting all the bit 0 and bit 1 . 6. The intelligent power circuit of any one of claims 1 -5, wherein the high voltage transceiver comprises: a first input, a second input, a first output, a second output, a first inverter, a second inverter, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first Schmitt trigger and a second Schmitt trigger, wherein the first input is connected with an input of the first inverter and a gate of the first NMOS transistor, an output of the first inverter is connected with a gate of the second PMOS transistor, a source of the second PMOS transistor is connected with a power supply, a drain of the second PMOS is connected with a drain of the second NMOS transistor, a source of the second NMOS transistor is grounded, a drain of the second PMOS and a drain of the second NMOS transistor are connected with an input of the second Schmitt trigger respectively and an output of the second Schmitt trigger is made as the first output; and wherein the second input is connected with an input of the second inverter and a gate of the second NMOS transistor, an output of the second inverter is connected with a gate of the first PMOS transistor, a source of the first PMOS transistor is connected with a power supply, a drain of the first PMOS transistor is connected with a drain of the first NMOS transistor, a source of the first NMOS transistor is grounded, a drain of the first PMOS transistor and a drain of the first NMOS transistor are connected with an input of the first Schmitt trigger respectively and an output of the first Schmitt trigger is made as the second output. 7. The intelligent power circuit of any one of claims 1 -6, wherein the low voltage transceiver comprising: a third input, a fourth input, a third output, a fourth output, a third inverter, a fourth inverter, a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a third Schmitt trigger and a fourth Schmitt trigger, wherein the third input is connected with an input of the third inverter and agate of the third NMOS transistor, an output of the third inverter is connected with a gate of the fourth PMOS transistor, a source of the fourth PMOS transistor is connected with a power supply, a drain of the fourth PMOS transistor is connected with a drain of the fourth NMOS transistor, a source of the fourth NMOS transistor is grounded, a drain of the fourth PMOS transistor and a drain of the fourth NMOS transistor are connected with an input of the fourth Schmitt trigger respectively and an output of the fourth Schmitt trigger is made as the third output; and wherein the fourth input is connected with an input of the fourth inverter and a gate of the fourth NMOS transistor, an output of the fourth inverter is connected with a gate of the third PMOS transistor, a source of the third PMOS transistor is connected with a power supply, a drain of the third PMOS is connected with a drain of the third NMOS transistor, a source of the third NMOS transistor is grounded, a drain of the third PMOS transistor and a drain of the third NMOS are connected with an input of the third Schmitt trigger respectively and an output of the third Schmitt trigger is made as the fourth output. 8. The intelligent power circuit of any one of claims 1 -7, further comprising: a multi-path sampling unit configured to sample and obtain an analog signal; a dual-integral A/D unit connected with the multi-path sampling unit and configured to convert the analog signal into a digital signal; and a serial processing unit connected with the dual-integral A/D unit and configured to convert the digital signal into the serial digital signal. 9. The intelligent power circuit of any one of claims 1 -8, further comprising: an asynchronous processing unit connected with the de-insertion unit and configured to perform an asynchronous processing on the serial digital signal received from the de-insertion unit. 10. A method for controlling an intelligent power circuit, comprising the steps of: receiving a controlling signal, converting an ascending edge of the controlling signal into a first narrow pulse signal, and converting a descending edge of the controlling signal into a second narrow pulse signal; transforming the first narrow pulse signal and the second narrow pulse signal from a low voltage to a high voltage respectively; rectifying the first narrow pulse signal and the second narrow pulse signal to get the controlling signal; controlling a power according to the controlling signal; obtaining a serial digital signal; generating a signal with a first feature representing bit 0 of the serial signal and a second feature representing bit 1 of the serial signal and transmitting the signal with the first feature and the second feature from the high voltage to the low voltage; and de-inserting and obtaining the serial digital signal from the signals with features according to the first feature and the second feature of the signal with the low voltage. 1 1 . The method of claim 10, wherein the step of de-inserting and obtaining the serial digital signal from the signals with features according to the first feature and the second feature of the signal with the low voltage comprises a step of determining the signal sending from the low voltage transceiver is with the first feature or with the second feature I. 12. The method of claim 10, wherein the step of generating a signal with a first feature representing bit 0 of the serial signal and a second feature representing bit 1 of the serial signal further comprises: inserting a third narrow pulse signal at a first time period after sending the first narrow pulse signal to obtain a first feature; and inserting a third narrow pulse signal at a second time period after sending the first narrow pulse signal to obtain a second feature. 13. The method of claim 1 1 , wherein a pulse width of the controlling signal is greater than or equal to a sum of a pulse width of the first narrow pulse signal, a longer one of the first time period and the second time period and a pulse width of the third narrow pulse signal. 14. The method of claim 1 1 , wherein the step of the step of de-inserting and obtaining the serial digital signal from the signals with features according to the first feature and the second feature of the signal with the low voltage further comprises: de-inserting and obtaining a bit 0 of the serial digital signal if the signal with the first feature is received ; and de-inserting and obtaining a bit 1 of the serial digital signal if the signal with the second feature is received. 15. The method of any one of claims 10-13, wherein the step of obtaining a serial digital signal further comprises: sampling and getting an analog signal; converting the analog signal into a digital signal; and performing a serial process on the digital signal. 16. The method of any one of claims 10-14, further comprising: performing an asynchronous processing on the serial digital signal obtained from the step of de-inserting. |
CONTROLLING METHOD THEREOF
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority and benefits of Chinese Patent Application Serial No.
201010244464.9, filed with the State Intellectual Property Office of P. R. China on July 29, 2010, the entire content of which is incorporated herein by reference.
FIELD
The present disclosure relates to a field of intelligent power circuit, and more particularly, to an intelligent power circuit of high-voltage insulation and a method for controlling the same.
BACKGROUND
A power unit of the intelligent power circuit such as IGBT ( Insulated Gate Bipolar
Transistor), MOSFETC Metal-Oxide-Semiconductor Field-Effect Transistor), MOSFET and IGCT ( Intergrated Gate Commutated Thyristors) has a widespread application in a high power converter because of their low consumption of energy, high switch-on and off frequency and high current capacity. At the same time, requirements for a driving circuit for the power unit are also strict. The driving circuit for the power unit of the intelligent power circuit works in a high voltage environment, driving pulse signals must be insulated before being transmitted to the driving unit of the intelligent power circuit.
Conventional insulating methods include light insulation and magnetic insulation. The light insulation may have such problems as time delay of transportation, easily to be aging and low reliability due to a low insulation voltage, and normally this method is not used when an insulation voltage is higher than 2000V. The magnetic insulation (pulse transformer insulation) may easily realize an insulation of a relatively high voltage and a transformer have no such problems as time delay of transportation, easily to be aging and low reliability and may realize a high switch-on and off frequency. Therefore, the pulse transformer is mainly used as an insulating component in the power unit of the intelligent power circuit to realize an insulation and transportation of driving signals when the insulation voltage is lower than 5000V.
In a conventional power circuit, the pulse transformer drives the IGBT or MOS Transistor by directly using an insulated amplified pulse signal.
The disadvantages of the conventional power circuit may include that the pulse transformer only transports a narrow pulse signal with a fixed pulse width and therefore signals sampled at a high voltage end need to be transported from the high voltage end to a low voltage end via another group of high voltage transceiver, pulse transformer and low voltage transceiver; more components may be needed and the power circuit may occupy a larger area.
SUMMARY
The present disclosure is directed to solve at least one of the above mentioned problems, and more particularly a problem of needing more components to transmit a driving signal and a sampled signal respectively.
According to an aspect of the present disclosure, an intelligent power circuit is provided. The intelligent power circuit comprises: a pulse modulating unit configured to receive a controlling signal, to convert an ascending edge of the controlling signal into a first narrow pulse signal, and to convert a descending edge of the controlling signal into a second narrow pulse signal; a low voltage transceiver connected with the pulse modulating unit and configured to receive and transmit the first narrow pulse signal and the second narrow pulse signal; a signal transformer connected with the low voltage transceiver and configured to transform a voltage of the first narrow pulse signal and a voltage of the second narrow pulse signal from a low voltage to a high voltage respectively; a high voltage transceiver connected with the signal transformer and configured to receive and transmit the first narrow pulse signal and the second narrow pulse signal; a rectifying unit connected with the high voltage transceiver and configured to rectify the first narrow pulse signal and the second narrow pulse signal received from the high voltage transceiver to obtain the controlling signal; a driving unit connected with the rectifying unit and configured to control a connected power module according to the controlling signal; an insertion unit connected with the high voltage transceiver and configured to obtain a representation of a serial digital signal by using the first narrow pulse signal and the second narrow pulse signal to generate a signal with a first feature representing bit 0 of the serial signal and a second feature representing bit 1 of the serial signal and to transmit the signal with the first feature and the second feature to the high voltage transceiver; wherein the high voltage transceiver is further configured to receive and transmit the signal with the first feature and the second feature; the signal transformer is further configured to transform the signal with the first feature and the second feature from the high voltage to the low voltage and to transmit the signal with the first feature and the second feature to the low voltage transceiver; and the low voltage transceiver is further configured to receive and transmit the signal with the first feature and the second feature, and a de-insertion unit connected with the low voltage transceiver and the pulse modulating unit and configured to de-insert and obtain the serial digital signal from the first narrow pulse signal and the second narrow pulse signal according to the first feature and the second feature of the signal received from the low voltage transceiver.
According to another aspect of the present disclosure, A method for controlling an intelligent power circuit, comprising the steps of: receiving a controlling signal, converting an ascending edge of the controlling signal into a first narrow pulse signal, and converting a descending edge of the controlling signal into a second narrow pulse signal; transforming the first narrow pulse signal and the second narrow pulse signal from a low voltage to a high voltage respectively; rectifying the first narrow pulse signal and the second narrow pulse signal to get the controlling signal; controlling a power according to the controlling signal; obtaining a serial digital signal; generating a signal with a first feature representing bit 0 of the serial signal and a second feature representing bit 1 of the serial signal; transmitting the signal with the first feature and the second feature from the high voltage to the low voltage; and de-inserting and obtaining the serial digital signal from the signals with features according to the first feature and the second feature of the signal with the low voltage.
According to the embodiments of the present disclosure, in the intelligent power circuit of high-voltage insulation, the insertion processing unit obtains a representation of the serial digital signal by using the first narrow pulse signal and the second narrow pulse signal and to generate a signal with a first feature representing bit 0 of the serial signal and a second feature representing bit 1 of the serial signal and to transmit the signal with the first feature and the second feature to the high voltage transceiver; the de-insertion unit de-inserts and obtains the serial digital signal from the first narrow pulse signal and the second narrow pulse signal according to the first feature and the second feature of the signal received from low voltage transceiver. The digital signals from the high voltage end and the controlling signals from the low voltage end may share a same high voltage transceiver, signal transformer and low voltage transceiver, thus reducing a number of components. BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other features and advantages of the disclosure will become apparent and more readily appreciated from the following descriptions taken in conjunction with the drawings in which:
Fig. 1 is a block diagram showing an intelligent power circuit of high-voltage insulation according to an embodiment of the present disclosure;
Fig. 2 is a schematic diagram showing a structure of a high voltage transceiver, a signal transformer and a low voltage transceiver according to an embodiment of the present disclosure;
Fig. 3 is a schematic diagram showing obtaining a representation of a serial digital signal with a first narrow pulse and a second narrow pulse by an insertion unit according to an embodiment of the present disclosure;
Fig. 4 is a schematic diagram showing obtaining a serial digital signal from a first narrow pulse and a second narrow pulse by a de-insertion unit according to an embodiment of the present disclosure;
Fig. 5 is a schematic diagram showing modulating a controlling signal by a pulse modulating unit according to an embodiment of the present disclosure;
Fig.6 is a schematic diagram showing converting a controlling signal from the first narrow pulse signal and the second narrow pulse signal by a rectifying unit according to an embodiment of the present disclosure; Fig.7 is a schematic diagram showing asynchronously processing the serial digital signal after a de-insertion process by an asynchronous processing unit according to an embodiment of the present disclosure; and
Fig. 8 is a flow chart showing a method for controlling an intelligent power circuit according to an embodiment of the present disclosure.
DETAILED DESCRIPTION
Reference will be made in detail to embodiments of the present disclosure. The embodiments described herein with reference to drawings are explanatory, illustrative, and used to generally understand the present disclosure. The embodiments shall not be construed to limit the present disclosure. The same or similar elements and the elements having same or similar functions are denoted by like reference numerals throughout the descriptions.
Fig. 1 is a block diagram showing an intelligent power circuit of high-voltage insulation according to an embodiment of the present disclosure. As shown in Fig.1 , the intelligent power circuit 100 comprises: a pulse modulating unit 101 , a low voltage transceiver 102, a signal transformer 103, a high voltage transceiver 104, a rectifying unit 105, a driving unit 106, a power unit 107, an insertion unit 1 1 1 and a de-insertion unit 1 12.
The pulse modulating unit 101 may receive a controlling signal, convert an ascending edge of the controlling signal into a first narrow pulse signal, and convert a descending edge of the controlling signal into a second narrow pulse signal. The low voltage transceiver 102 is connected with the pulse modulating unit 101 and may receive and transmit the first narrow pulse signal and the second narrow pulse signal. The signal transformer 103 is connected with the low voltage transceiver 102 and may transform a voltage of the first narrow pulse signal and a voltage of the second narrow pulse signal from a low voltage to a high voltage respectively. The high voltage transceiver 104 is connected with the signal transformer 103 and may receive and transmit the first narrow pulse signal and the second narrow pulse signal. The rectifying unit 105 is connected with the high voltage transceiver 104 and may rectify the first narrow pulse signal and the second narrow pulse signal received from the high voltage transceiver 104 to obtain the controlling signal. The driving unit 106 is connected with the rectifying unit 105 and may control a connected power module 107 according to the controlling signal.
The insertion unit 1 1 1 is connected with the high voltage transceiver 104 and may obtain a representation of a serial digital signal by using the first narrow pulse signal and the second narrow pulse signal to generate a signal with a first feature representing bit 0 of the serial signal and a second feature representing bit 1 of the serial signal and may transmit the signal with the first feature and the second feature to the high voltage transceiver 104. The high voltage transceiver 104 may receive and transmit the signal with the first feature and the second feature. The signal transformer 103 may transform the signal with the first feature and the second feature from the high voltage to the low voltage and may transmit the signal with the first feature and the second feature to the low voltage transceiver 102. The low voltage transceiver 102 may receive and transmit the signal with the first feature and the second feature. The de-insertion unit 1 12 is connected with the low voltage transceiver 102 and the pulse modulating unit 101 and may de-insert and obtain the serial digital signal from the first narrow pulse signal and the second narrow pulse signal according to the first feature and the second feature of the signal received from low voltage transceiver 102.
In one embodiment, the intelligent power circuit 100 may further comprise a multi-path sampling unit 108, a dual integral A/D unit 109, and a serial processing unit 1 10. The multi-path sampling unit 108 may sample and obtain an analog signal. The dual-integral A/D unit 109 is connected with the multi-path sampling unit 108 and may convert the analog signal into a digital signal. The serial processing unit 1 10 is connected with the dual-integral A/D unit 109 and may convert the digital signal into the serial digital signal.
In one embodiment, the de-insertion unit 1 12 receives the first narrow pulse signal and the second narrow pulse signal from the pulse modulating unit 101 , which are used for comparing time. The de-insertion unit 1 12 de-inserts and obtains the serial digital signal from the first narrow pulse signal by determining the signal sending from the low voltage transceiver is with the first feature or with the second feature.
In one embodiment, the intelligent power circuit 100 may further comprise an asynchronous processing unit 1 13. The asynchronous processing unit 1 13 is connected with the de-insertion unit 1 12 and may perform an asynchronous processing on the serial digital signal received from the de-insertion unit 1 12.
Fig. 2 is a schematic diagram showing a structure of a high voltage transceiver, a signal transformer and a low voltage transceiver according to an embodiment of the present disclosure.
As shown in Fig. 2, the high voltage transceiver 104 comprises: a first input, a second input, a first output, a second output, a first inverter (D1 ), a second inverter (D2), a first PMOS transistor (P1 ), a second PMOS transistor (P2), a first NMOS transistor (N1 ), a second NMOS transistor (N2), a first Schmitt trigger (S1 ) and a second Schmitt trigger (S2).
The first input is connected with an input of the first inverter (D1 ) and a gate of the first NMOS transistor (N1 ), an output of the first inverter (D1 ) is connected with a gate of the second PMOS transistor (P2), a source of the second PMOS transistor (P2) is connected with a power supply (VCC), a drain of the second PMOS (P2) is connected with a drain of the second NMOS transistor (N2), a source of the second NMOS transistor (N2) is grounded, a drain of the second PMOS (P2) and a drain of the second NMOS transistor (N2) are connected with an input of the second Schmitt trigger (S2) respectively and an output of the second Schmitt trigger (S2) is made as the first output.
The second input is connected with an input of the second inverter (D2) and a gate of the second NMOS transistor (N2), an output of the second inverter (D2) is connected with a gate of the first PMOS transistor (P1 ), a source of the first PMOS transistor (P1 ) is connected with a power supply (VCC), a drain of the first PMOS transistor (P1 ) is connected with a drain of the first NMOS transistor (N1 ), a source of the first NMOS transistor (N1 ) is grounded, a drain of the first PMOS transistor (P1 ) and a drain of the first NMOS transistor (N1 ) are connected with an input of the first Schmitt trigger (S1 ) respectively and an output of the first Schmitt trigger (S1 ) is made as the second output.
Also as shown in Fig. 2, the low voltage transceiver 103 comprises a third input, a fourth input, a third output, a fourth output, a third inverter (D3), a fourth inverter (D4), a third PMOS transistor (P3), a fourth PMOS transistor (P4), a third NMOS transistor (N3), a fourth NMOS transistor (N4), a third Schmitt trigger (S3) and a fourth Schmitt trigger (S4). The third input is connected with an input of the third inverter (D3) and agate of the third NMOS transistor (N3), an output of the third inverter (D3) is connected with a gate of the fourth PMOS transistor (P4), a source of the fourth PMOS transistor (P4) is connected with a power supply (VCC), a drain of the fourth PMOS transistor (P4) is connected with a drain of the fourth NMOS transistor (N4), a source of the fourth NMOS transistor (N4) is grounded, a drain of the fourth PMOS transistor (P4) and a drain of the fourth NMOS transistor (N4) are connected with an input of the fourth Schmitt trigger (S4) respectively and an output of the fourth Schmitt trigger (S4) is made as the third output
The fourth input is connected with an input of the fourth inverter (D4) and a gate of the fourth NMOS transistor (N4), an output of the fourth inverter (D4) is connected with a gate of the third PMOS transistor (P3), a source of the third PMOS transistor (P3) is connected with a power supply (VCC), a drain of the third PMOS (P3) is connected with a drain of the third NMOS transistor (N3), a source of the third NMOS transistor (N3) is grounded, a drain of the third PMOS transistor (P3) and a drain of the third NMOS (N3) are connected with an input of the third Schmitt trigger (S3) respectively and an output of the third Schmitt trigger (S3) is made as the fourth output.
As shown in Fig. 2, the signal transformer connects the low voltage transceiver 102 and the high voltage transceiver 104. A full-bridge driving is adopted and pulse signals may be transmitted bi-directionally. A first narrow pulse signal is input through the third input of the low voltage transceiver 103 and is output from the high voltage end due to a mutual induction of the signal transformer 103. A second narrow pulse signal is input through the fourth input of the low voltage transceiver 103 and is output from the second output of the high voltage transceiver 104; a third narrow pulse signal is input through the first input of the high voltage transceiver 104 and is output from the third output of the low voltage transceiver 103.
Fig. 3 is a schematic diagram showing obtaining a representation of a serial digital signal with a first narrow pulse and a second narrow pulse by an insertion unit according to an embodiment of the present disclosure.
As shown in Fig.3, the insertion unit obtains the first feature by inserting a third narrow pulse signal D at a first time period after sending the first narrow pulse signal LP and obtains the second feature by inserting a third narrow pulse signal D at a second time period after sending the first narrow pulse signal LP. Specifically, when a current bit of the serial digital signal to be transmitted is 0, the third narrow pulse signal D is inserted at the first time period after the first narrow pulse signal LP is sent; when a current bit of the serial digital signal to be transmitted is 1 , a third narrow pulse signal D is inserted at the second time period after the first narrow pulse signal LP is sent. The insertion unit 1 1 1 inserts one third narrow pulse signal D when it detects there is the first narrow pulse signal LP until all bits of the serial digital signal are represented.
A pulse width of the controlling signal is greater than or equal to a sum of a pulse width of the first narrow pulse signal LP, a longer one of the first time period and the second time period and a pulse width of the third narrow pulse signal D.
In one embodiment, since a jitter-elimination period is 700nm, the pulse width of the controlling signal PW is at least 700ns. Therefore, the sum of a pulse width of the first narrow pulse signal LP, a longer one of the first time period and the second time period and a pulse width of the third narrow pulse signal D must be less than 700ns. The pulse width of the first narrow pulse signal LP and the pulse width of the third narrow pulse signal D may be both set to 200ns, the first time period may be set to 100ns and the second time period may be set to 300ns. According to a change of the pulse width of the controlling signal PW, the pulse width of the first narrow pulse signal LP, the pulse width of the third narrow pulse signal D, the first time period and the second time period may be adjusted, but the second time period is larger than the first time period.
Fig. 4 is a schematic diagram showing obtaining a serial digital signal from a first narrow pulse and a second narrow pulse by a de-insertion unit according to an embodiment of the present disclosure.
As shown in Fig.4, the de-insertion unit 1 12 obtains a bit 0 of the serial digital signal if the signal with the first feature is received from low voltage transceiver and obtains a bit 1 of the serial digital signal if the signal with the second feature is received from low voltage transceiver and obtains the serial digital signal as a result of getting all the bit 0 and bit 1 . Specifically, when the third narrow pulse signal D is received at the first time period after receiving the first narrow pulse signal LP, the de-insertion unit 1 12 gets the bit 0; when a third narrow pulse signal D is received at a second time period after receiving the first narrow pulse signal LP, the de-insertion unit 1 12 gets the bit 1 . In one embodiment, the first time period may be set to 100ns and the second time period may be set to 300ns. When the third narrow pulse signal D is received at 100ns after receiving the first narrow pulse signal LP, the de-insertion unit 1 12 gets the bit 0; when the third narrow pulse signal D is received at 300ns after receiving the first narrow pulse signal LP, the de-insertion unit 1 12 gets the bit 1 .
Fig. 5 is a schematic diagram showing modulating a controlling signal by a pulse modulating unit according to an embodiment of the present disclosure. As shown in Fig.5, the pulse modulating unit 1 receives the controlling signal PW, converts the ascending edge of the controlling signal PW into the first narrow pulse signal LP, and converts the descending edge of the controlling signal PW into the second narrow pulse signal LN. In one embodiment, the pulse width of the first narrow pulse signal LP and the pulse width of the second narrow pulse signal LN are both 200ns and may be adjusted according to different pulse widths of the controlling signal PW.
Fig.6 is a schematic diagram showing converting a controlling signal from the first narrow pulse signal and the second narrow pulse signal by a rectifying unit according to an embodiment of the present disclosure. As shown in Fig.6, the rectifying unit 105 may rectify the first narrow pulse signal LP and the second narrow pulse signal LN from the high voltage transceiver 104 to get the controlling signals PW at the high voltage end. When the first narrow pulse signal LP is a high level signal, the controlling signals PW is also a high level signal and when the second narrow pulse signal LN becomes the high level signal, the controlling signal PW becomes a low level signal.
Fig.7 is a schematic diagram showing asynchronously processing the serial digital signal after a de-insertion process by an asynchronous processing unit according to an embodiment of the present disclosure. As shown in Fig.7, the asynchronous processing unit 1 13 may asynchronously process the serial digital signal DATE received from the de-insertion unit 1 12 to get an asynchronous signal DIG. The bit "1 " and bit "0" of the serial digital signal may be distinguished by using different duty cycles. In one embodiment, the duty cycle of "3/4" represents bit "1 " of the serial digital signal and the duty cycle of "1/4" represents bit "0" of the serial digital signal. Fig. 8 is a flow chart showing a method for controlling an intelligent power circuit according to an embodiment of the present disclosure. As shown in Fig. 8, the method comprises the following steps.
Step 801 , a controlling signal is received, an ascending edge of the controlling signal is converted into a first narrow pulse signal, and a descending edge of the controlling signal is converted into a second narrow pulse signal.
Step 802, the first narrow pulse signal and the second narrow pulse signal are transformed from a low voltage to a high voltage respectively.
Step 803, the first narrow pulse signal and the second narrow pulse signal are rectified to get the controlling signal.
Step 804, a power is controlled according to the controlling signal.
Step 805, a serial digital signal is obtained.
Step 806, a signal with a first feature representing bit 0 of the serial signal and a second feature representing bit 1 of the serial signal are generated and the signal with the first feature and the second feature is transmitted from the high voltage to the low voltage.
Step 807, the serial digital signal from the signals with features is de-inserted and obtained according to the first feature and the second feature of the signal with the low voltage.
In one embodiment, step S807 may comprise a step of receiving the first narrow pulse signal and the second narrow pulse signal, which are used for comparing time and may further comprise a step of determining the signal sending from the low voltage transceiver is with the first feature or with the second feature.
In one embodiment, step S806 may further comprise: inserting a third narrow pulse signal at a first time period after sending the first narrow pulse signal to obtain a first feature; and inserting a third narrow pulse signal at a second time period after sending the first narrow pulse signal to obtain a second feature.
In one embodiment, a pulse width of the controlling signal is greater than or equal to a sum of a pulse width of the first narrow pulse signal, a longer one of the first time period and the second time period and a pulse width of the third narrow pulse signal.
In one embodiment, step S807 may further comprise: de-inserting and obtaining a bit
0 of the serial digital signal if the signal with the first feature is received; and de-inserting and obtaining a bit 1 of the serial digital signal if the signal with the second feature is received.
In one embodiment, step S805 may further comprise: sampling and getting an analog signal; converting the analog signal into a digital signal; and performing a serial process on the digital signal.
In one embodiment, the method may further comprise step S808, in which an asynchronous processing is performed on the serial digital signal obtained from step S807.
According to the embodiments of the present disclosure, in the intelligent power circuit of high-voltage insulation, the insertion processing unit obtains the representation of the serial digital signal by using the first narrow pulse signal and the second narrow pulse signal and to generate a signal with a first feature representing bit 0 of the serial signal and a second feature representing bit 1 of the serial signal and to transmit the signal with the first feature and the second feature to the high voltage transceiver; the de-insertion unit de-inserts and obtains the serial digital signal from the first narrow pulse signal and the second narrow pulse signal according to the first feature and the second feature of the signal received from low voltage transceiver. The digital signals from the high voltage end and the controlling signals from the low voltage end may share a same high voltage transceiver, signal transformer and low voltage transceiver, thus reducing a number of components.
Although explanatory embodiments have been shown and described, it would be appreciated by those skilled in the art that changes, alternatives, and modifications may be made in the embodiments without departing from spirit and principles of the disclosure. Such changes, alternatives, and modifications all fall into the scope of the claims and their equivalents.
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