The present invention relates to intelligent signal processing and more particularly to a design methodology for achieving the same.

Signal processing is a well known technique to analyse signals with the purpose of modifying and or detecting component parts of a signal.

In many applications it is desirable that signal processing can be modified in response to the characteristics of the signal. For example, intelligent signal processing may be used to automatically alter a processing regime and information output in response to a perceived change in a received signal. The signal could be an analogue signal received from a sensor responsive to energy from a source which may be acoustic, optical, thermal etc. Consequently it is possible for such sensor derived electronic signals to be intelligently signal processed to selectively process those aspects of signals which are of particular interest. This capability can be used to filter unwanted information, or decode data embedded within a signal.

Electronic circuits capable of intelligent signal processing typically involve complex circuitry with large numbers of wire connections between the various components used. Consequently the size of intelligent signal processing circuits and their cost of production have been factors which have tended to restrict their use to certain specialised applications where space and cost is not a limiting factor.

A further disadvantage of known intelligent signal processors is relatively high power consumption and these are accordingly not suitable for applications where the available power is too limited.

It is the aim of the present invention to provide an intelligent signal processor which overcomes or at least mitigates these disadvantages and provides a relatively small, low cost alternative to those designs currently on the market.

Accordingly there is provided an intelligent digital signal processing circuit which comprises:

a) a digital signal processor (DSP) ;

b) a means for interfacing a plurality of serial data channels to the DSP, each channel comprising means for converting a received analogue signal to a digital signal;

c) means for providing a power supply to each channel, the power supply being modulated by a ¹ common clock signal, each channel including means to separate the clock signal from the power supply.

The use of a power supply modulated by a common clock signal is beneficial in allowing a reduction in the wiring normally associated with the transmission of data to the DSP. With the present invention it is possible to limit these transmission wires to just three per channel. These are one wire for serial data stream transmission, another for the power and timed pulse (clock) to synchronise the data transmission of

each channel and another as a ground (earth return) .

The means for converting the analogue into the digital signals may be provided by a suitable analogue to digital converter (ADC) . To enable the circuit to have increased resolution in respect of a component part of an analogue signal it is preferable for the ADC to be of a multibit type. This allows for the possibility of altering the number of bits used in digitising an analogue signal. Thus 2-bit resolution of a signal can be improved by instructing the ADC to switch to using more bits, for example 12. Conveniently a 16 bit analogue to digital converter is used. Such devices are readily available commercially, being used in the production of digital audio tape players. Preferably each serial data channel has a separate ADC.

The DSP receives the synchronised data from the analogue to digital converter and processes it in accordance with the programmed memory. Preferably the DSP is synchronised with a clock timing signal from a central unit which unit is also used to supply the basic clock signal to the ADC via a clock/power splitter. This enables synchronization of data transfer between the analogue to digital converter and the DSP memory.

Preferably a single DSP microprocessor provides the majority of functions as well as the signal processing functions. The memory of the DSP contains algorithms which may be used to filter out data which is not of interest. Consequently _the DSP can be programmed to switch its signal processing capabilities in response to receiving data of specific interest. Thus an algorithm can be designed to recognise data of

. interest and in this way concentrate the DSP's signal processing function upon this data. Consequently the processing resolution for specific data can be enhanced over that where all data is processed. This feature in combination with the variable resolution which can be attributed to the conversion of analogue to digital signals may be of particular benefit where transmission of the circuits output is necessarily waveband limited.

The present invention thus provides the means of acquiring and processing multiple analogue signals using a novel combination of commercially available components. The design is of particular benefit in applications where the number of interconnections between the analogue inputs and the digital signal processor must be kept to a minimum. It has utility to process multiple analogue signals in a pre-determined manner dependent upon the characteristics of the incoming signal.

The ability to construct the present invention's intelligent digital signal processing circuit from readily available commercial components means that the circuit is cheap and in addition it is of compact design.

Particularly useful features of circuits produced according to the present invention are the ability to handle multiple signals, real-time signal processing of incoming signals and the output of filtered signals in digitally multiplexed format.

The invention will now be described by way of example only and with reference to the accompanying figure which shows an intelligent digital

signal processing circuit according to the invention.

An intelligent digital signal processing circuit (1) comprises a plurality of 16-bit delta-sigma analogue to digital converters (ADC) (2) board mounted whose position is shown or indicated in sections (a - e) . The ADC's (2 a-e) can be replicated as necessary on further boards and another four are shown by 2i, 2ii, 2iii and 2iv. The ADC's (2) are linked to a central unit (3) which provides power and clock data to power/clock splitters (4 a - e) . Each ADC (2) has an associated power/clock splitter (4 a - e) with the power/clock splitters (4 a - e) all connected by common transmission line (5a) to the central unit (3) . The central unit (3) comprises a power supply (not shown) which is subjected to power conditioning (not shown) . This power supply is used to drive a crystal oscillator (6) whose output is fed to a timing generator (7) and also to an AT & T, DSP32C digital signal processor (DSP) (8) through port (8a) . The output of the timing generator (7) is also fed into the DSP (8) through port (8b) (interrupts) as well as being transmitted to a power/clock driver (9) which is used to provide a common power supply modulated by a clock signal to each of the power/clock splitters (4 a - e) .

Each of the power/clock splitter circuits (4 a - e) is used to extract a reference clock signal from the clock signal provided by the power/clock driver (9) for the synchronous generation of the serial data output of the ADC's (2) and also to supply DC power at 5 Volts to the ADC's (2).

This design of supplying clock signals superimposed onto DC power supply

enables a reduction in the number of interconnecting wires between the ADC's (2) and central unit (3). The wire (5b) also simplifies design by providing a common earth return or ground between all of the ADC's (2) and corresponding power/clock splitters (4 a - e) and the power/clock driver (9) of the central unit (3). Each of the ADC's (2) is linked by a corresponding wire (5c) to a memory port (8c) of the DSP (8) which enables the transfer of serial data from ADC's (2) to DSP (9).

The DSP (8) is a large scale integrated circuit which contains algorithms for signal processing. In addition to ports (8 a - c) the DSP (8) has further ports (8d & 8e) of which port 8d is a serial port suitable for serial output and port 8e is a parallel port suitable for inputting ancillary data.

In use analogue data received by the ADC's (2) from analogue sensors (10) is converted into a digital serial data stream and fed to DSP memory port (8c) with the data being synchronised by the clock signals to the ADC's (2) and the DSP (8) from the central unit (3). The digital data stream is processed by the DSP (8) using desired signal processing algorithms and the resultant processed signal is connected to the serial output port (8d) as a digital data stream whose format and content is dependent upon the preprogrammed algorithms. Where only specific signals in the digital serial data stream are of interest the algorithms can be designed to recognise these amongst the general data entering the DSP (8). When these specific signals are detected the DSP (8) will switch operation and disregard the general data enabling significantly more time to be given to processing the signals of interest and hence yielding a higher resolution output than would otherwise be achieved.

Furthermore if the specific signals of interest require higher digital signal resolution this can be achieved by instructing the ADC's (2) to increase the number of bits used in converting the analogue to the digital signal. The additional parallel input port (8e) is available for ancillary digital information to be transmitted into the DSP (8) . These data can be used to further modify the signal processors (1) capabilities.

The DSP (8) maybe programmed during manufacture with the algorithms required for a particular application in which it is intended to be used. Applications are widespread and include underwater mapping and intelligent acoustic telemetry etc.