Title:
INTERFACE CIRCUIT, DIGITAL CIRCUIT, COMMUNICATION MODULE, AND COMMUNICATION DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/032496
Kind Code:
A1
Abstract:
This interface circuit comprises: a first storage circuit that retains first timer selection information indicating which of a plurality of timers to select; a second circuit that can operate as any of the plurality of timers and that includes a first circuit which performs a counter operation and a register update signal generation circuit which outputs a first register update signal for updating a register on the basis of an output of the first circuit; and a control circuit that controls the advisability of writing into the first circuit or reading out from the first circuit on the basis of the first timer selection information from the first storage circuit and counter classification information which is input from an external device and indicates any of a plurality of counters corresponding to the plurality of timers.
Inventors:
NAKAMUTA KAZUHIRO (JP)
Application Number:
PCT/JP2022/028174
Publication Date:
March 09, 2023
Filing Date:
July 20, 2022
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
G06F13/38
Foreign References:
| JP2008077184A | 2008-04-03 | |||
| JP2010244445A | 2010-10-28 | |||
| JPH06110576A | 1994-04-22 | |||
| US4598360A | 1986-07-01 | |||
| US4479123A | 1984-10-23 |
Attorney, Agent or Firm:
INABA, Yoshiyuki et al. (JP)
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